Statistical analysis of key chapters for electronics engineering exams

9 Microprocessor 8086
Statistical Analysis of Chapter 9

Year 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
IES(obj) 1 2 1 2 1 2 2 1 2 2 1 1 2 1
IES(Con) 13 10 7 15 10 15
E&T 1
GATE 2 - - - - - - - - - - - - - - - - -
3 - - - - - - - - - - - - - - - - -
IES(obj) 3 1 4 1 2 5
IES(Con)
EE 1 - - - - - - - - - - - - - - - - -
GATE
2 - - - - - - - - - - - - - - - - -
IAS (mains) 20 20 12 20
IN GATE - - - - - - - - - - - - - - - - - -
* Number in box is no. of Questions for IES (obj) and marks for all other exams
Conclusion
This chapter should be studied for IES objective of Electricsl & Electronics
Engineering and IES conventional paper of Electronics Engineering only and
IAS mains.
9.1 Introduction
The 8086 is a 40 pin, 16-bits, N-channel and HMOS microprocessor. Its clock frequencies can be 5, 8 and
10 MHz. It was introduced in 1978. It is built on a single semiconductor chip having 29000 transistors. The
8086 has 16 data lines and 20 address lines. It can directly address up to 220 = 1 Mbytes of memory. The
16-bit data word is has two parts called low-order byte and a high-order byte. The 20 address lines are time
multiplexed with the data lines and status signals. The low-order 16 address lines are time multiplexed with
data, and the high-order 4 address lines are time multiplexed with status signals.
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Microprocessor 8086 [2]
9.2 Pin Diagram of 8086
GND 1 40 Vcc
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE / S7
Ad8 8 33 MN / MX
AD7 9 32 RD
AD6 10 31 RQ / GT0 (HOLD)
Intel
AD5 11 8086 30 RQ / GT1 (HLDA)
AD4 12 29 LOCK (WR)
AD3 13 28 S2 (M / IO)
AD2 14 27 S1 (DT / R)
AD1 15 26 S1 (DT / R)
AD0 16 25 QS0(ALE)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Fig. 9.1 Pin Diagram of 8086
9.3 Pin and Signals of 8086

i. AD0-AD15: These are bidirectional lower order address bus which are time multiplexed with data lines.
When these lines are used for carrying the memory address the symbol A0-A15 is used instead of AD0-
AD15 and when data are transmitted over AD lines the symbol D0-D15 is used in place of AD0-AD15.
ii. A16-A19 (Output): These are high order address lines which are time multiplexed with the status signals.
The signal on these lines are generated by microprocessor so these are called output lines.
iii. A16/S3 and A17/S4 : S3 and S4 are called segment identifiers. S3 is time multiplexed with A16 and S4 is
time multiplexed with S4.
iv. A18/S5: The S5 is an interrupt status signal. It is time multiplexed with higher order address line A18.
v. A19/S6: S6 is a status signal is it multiplexed with the A19 address line.
vi. BHE / S 7 (Output) : The signal BHE stands for Bus High Enable. It is an active low signal. This signal
is low during T-state T1 of the machine cycle. This signal is used to enable higher order data bus,
D8 – D15. When this signal is low that means higher order data bus D8-D15 is carrying the data. An 8-bit
device connected to upper half of the data bus use BHE signal. The BHE signal is time multiplexed
with status signal S7. The status signal S7 is available during T-state T3 and T4.
vii. RD(Read) : This is active low signal. When signal on this pin is low that means processor performs
reading operation with memory or I/O devices.
viii.READY (Input) : This signal is used for interfacing processor with slow peripherals. When signal on
this pin is high that means I/O device is ready to transfer data. The processor enters into wait state Tw
between T3 and T4 T-states when signal on this pin is low.
ix. RESET (Input): This signal is active high. When signal on this pin becomes high the system is reset.
x. CLK (Input). This signal is used as reference clock. Clock can be of 5, 8 or 10 MHz. In 8086
microprocessor the clock is generated using a 8284A. The Intel 8284 is an oscillator chip used as
a clock generator. It provides the basic functions of clock generation, RESEST synchronization,
READY synchronization, and a TTL level peripheral clock signal. The output clock frequency of
crystal oscillator is divided 3 by 8284 A before giving CLK to the 8086 microprocessors. Therefore,
8284A uses a crystal oscillator that must be 3 times the frequency of the 8086 microprocessor.
xi. INTR (Interrupt request): This is an input signal which is an interrupt request.
xii. NMT (Inputs): This pin is used for non maskable interrupt request.
xiii. TEST(Input) : It is an active low signal used for test control. The processor waits for control test
when this signal becomes high and continue execution when it is low.
xiv. VCC :This pin is used for connecting power supply + 5V d.c.
xv. GND: This pin is used for reference Ground.
9.4 Operating Modes of 8086

The 8086 microprocessor can be operated in two modes called minimum and maximum modes. In minimum
mode of operation one 8086 microprocessor is used in microcomputer system. In minimum mode operation
microprocessor itself generates the control signals for operation with memory and I/O devices. In maximum
mode operation a number of processors are used. In maximum mode the control signals are generated by
Intel 8288 bus controller which is used along with 8086 for this very purpose. A pin MN/MX of 8086 is
used for deciding the minimum and maximum mode of operation. When signal on this pin is high the
microprocessor operates in minimum mode and when it is low it operates in maximum mode of operation.
The pin number 24 to 31 are used to generate two different sets of signals with one set of signals used for
minimum mode and another set used for maximum mode. Thus, the pin number fom 24 to 31 are used to
perform alternate functions.
9.4.1 Pin Signals for Minimum mode operation
For operation of 8086 microprocessor in minimum mode pin MN/MX is kept at high level by connecting
it to VCC . Other used pins and their signals during minimum mode are as follows,
i. INTA (Output) : This is an active low output signal which is used for acknowledgment of an interrupt
request.
ii. ALE (Output): Address latch enable. This is active high signal. When ALE becomes high the data of
address bus is latched into Intel 8282/8283 latch. The ALE signal goes high during T-state T1 of every
machine cycle.
iii. DEN (Output) : Data enable. It is an active low output signal. This signal is used as output enable
when Intel 8286/8287 octal bus transceiver is used.
iv. DT / R (Output) : Data transmit/Receiver. This signal is used to control direction of flow of data when
Intel 8286/8287 octal bus transceiver is used. The data is sent out when the signal is high and data is
received when it is low.
v. M / IO(Output) : This signal is used for performing reading and writing operations with memory or
I/O devices. Operation is performed with memory when it is high and operation is performed with I/O
devices when it is low.
vi. WR (Output) : Write. This is active low signal. When signal on this pin is low that means processor
performs writing operation with memory or I/O devices.
vii. HOLD (Input) : Hold. It is active high signal. Hold request is sent to the microprocessor by external
device such as DMA to use address and data lines.
viii.HLDA (Output): HOLD acknowledge. This signal is generated by microprocessor in response to the
HOLD request. It is an active high signal. HLDA becomes low when HOLD request is removed.
9.4.2 Pin Signals for Maximum mode operation Mode
For operation of 8086 microprocessor in maximum mode pin MN / MX is kept at low level by connecting
it to ground. Other used pins and their signals during maximum mode are as follows
i. QS1, QS0 (Output) : Instruction Queue Status. The value of these signals and corresponding status is
as given below:
QS1 QS0
0 0 No operation
0 1 1st byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
ii. S0 S1 , S 2 (Output) : These are the status signals. These are connected to bus controller Intel 8288. The
bus controller generates suitable control signals for accessing the memory and I/O devices. The values
of these signals and corresponding operation is given in the table below
Table.9.1 Status signals and operation

S2 S1 S0 Operation
0 0 0 Interrupt acknowledgement
0 0 1 Read data from I/O port
0 1 0 Write data into I/O port
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive state
iii. LOCK (Output). It is an active low signal. When signal on this pin is low all the interrupts are masked
and HOLD request is also not granted. This signal is also used by 8086 to communicate other processors
or DMA that microprocessor cannot relinquish the control of address and data buses.
iv. RQ / GT1 , RQ / GT0 : These are bidirectional lines. These are used for Local Bus Priority Control.
These signals given by other processors to 8086 for release of local bus. The signal RQ / GT0 has
higher priority than RQ / GT1 .
The signals like WR , ALE, DEN , DT / R etc. are not directly available in a maximum mode operation.
These signals are generated by bus controller Intel 8288.
9.5 Architecture and Functional Units of Intel 8086

The microprocessor 8086 has two main functional units called bus interface unit (BIU) and execution
unit (EU). Both of these units work independently. Fig 9.2 demonstrates the block diagram of 8086
microprocessor comprising BIU and EU. The BIU comprises of segment registers, instruction pointer,
6-byte fisrt-in first-out instruction queue. The EU comprises of general purpose registers, base pointer, stack
pointer, index register, ALU, flag registers, instruction decoder and timing and control unit.
The BIU is responsible for accessing memory/IO devices, exchanging data with memory and I/O devices. It
accesses the memory location by computing addresses, fetches the instruction codes, stores the instruction
codes in instruction queue of 6-bytes. It does function of relocating the address of operands whose
unallocated address is obtained from EU. EU gives the information about from where next byte or data is to
be fetched. The EU first receive the operation code from instruction queue, decodes it and then execute it.
It is important to mention here that EU and BIU does operation in coherence but independently. While EU is
decodes and executes the instructions and BIU fetches codes from memory and puts in queue. Independent
working of BIU and EU makes processing faster except in JUMP and CALL instructions where execution
sequence is changed and queue must be dumped and reloaded form new address. This overlapped & parallel
operation of execution of instruction by EU and fetching of code by BIU is called pipelining.
9.6 Registers of Intel 8086

The Intel 8086 contains the following registers :
(i) General Purpose Registers
(ii) Pointer and Index Registers
(iii) Segment Registers
(iv) Instruction Pointer
(v) Status Flags
Fig. 9.3 shows the register organization of Intel 8086 microprocessor.
9.6.1 General Purpose Registers
The microprocessor 8086 has four general purpose registers called accumulator, base, count and data registers.
Accumulator : Accumulator register comprises of two 8-bit registers AL and AH. The 8-bit registers AL
and AH can be combined to form 16-bit register AX. Here, AL is used to store lower order and AH is higher
order bytes of 16-bit data. Accumulator can be used for I/O operations and string manipulation. It is used in
arithmetic, logic and data transfer instructions.
Base Register: Base register comprises of two 8-bit registers BL and BH. The 8-bit registers BL and BH
can be combined to form 16-bit register BX. Here, BL is used to store lower order and BH is higher order
bytes of 16-bit data. Base register usually contains a data pointer used for based, based indexed or register
indirect addressing.
Count Register: Count register comprises of two 8-bit registers CL and CH. The 8-bit registers CL and
CH can be combined to form 16 bit register CX. Here, CL is used to store lower order and CH is higher
order bytes of 16-bit data. Count register can be used as a counter in string manipulation and shift/rotate
instructions.
MEMORY
INTERFACE
UNIT
(BIU) C-BUS
6
5
6-BYTE 4
INSTRUCTION 3
QUEUE 2
ES 1
CS SEGMENT REGISTERS
SS AND
DS INSTRUCTION POINTER
IP
(EU)
A-BUS
Instruction
Temporary Registers
Decoder
AH AL and
BH BL Control unit
CH CL
DH DL
SP
BP Arithmetic and logic unit
SI
DI
General purpose registers,
pointers & index registers Flags
Fig. 9.2 Block Diagram of Intel 8086 Microprocessor

Data Register: Data register comprises of two 8-bit registers DL and DH. The 8-bit registers DL and DH
can be combined to form 16 bit register DX. Here, DL is used to store lower order and DH is higher order
bytes of 16-bit data. Data register can be used as a port number in I/O operations. Data register is also used
to store higher order word of initial or resulting number in a 32-bit multiply and divide instruction. DX:AX
are concatenated into 32 bit register for multiply and divide operations.
9.6.2 Pointers and Index Register
Intel 8086 has set of four registers for the purpose of pointers and index. These registers are discussed in
brief as under,
Stack Pointer (SP): Stack pointer (SP) is a 16-bit register used for pointing to top of the stack in stack
segment. It stores offset address relative to Stack Segment register. It is used to hold the base value in base
addressing in association with SS register (SS:SP) to access data from stack segment of the memory.
Base Pointer (BP): The 16-bit BP register mainly helps in referencing the parameter variables passed to a
subroutine. The address in SS register is combined with the offset in BP to get the location of the parameter.
Base pointer is a 16-bit register used for pointing to data in stack segment. It is used for based, based
indexed or register indirect addressing. BP can also be combined with DI and SI as base register for special
addressing.
Source Index (SI): SI is used as pointer for addressing of data in data segment. Source Index(SI) is a 16-
bit register used for indexed, based indexed and register indirect addressing, as well as a source data address
in string manipulation instructions. It stores offset address relative to DS register.
Destination Index (DI): Destination Index (DI) is a 16-bit register used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string manipulation instructions. DI is
used as implied memory pointer in string instructions. It stores offset address relative to ES register.
9.6.3 Memory Segmentation and Segment Registers
Data in memory is always stored as a byte and each byte has a specific address. Intel 8086 has 20 lines of the
address bus. With 20 address lines, the process can identify 220 memory locations. So, the memory that can
be addressed is 220 bytes (220 bytes= 1,048,576 bytes =1 MB). Thus, memory of the Intel 8086 has address
ranging from 00000 H to FFFFF H. In Intel 8086, memory has four different types of segments called Code
Segment, Data Segment, Stack Segment and Extra Segment. Each of the segment is of 64 KB memory.
Four different 16-bit segment registers are used to point to the starting or base addresses of these memory
segments. Thus, the Intel 8086 can directly address four segments ( ie.256 KB of memory out of 1 M B
of memory) at any instant of time. The 16 bit segment registers store only upper 16 bits of address which
is called logical address. The 20 bit physical address of memory location in the memory segment is in the
form of Base Address : Offset. Offset is the displacement or Effective Address (EA) of the memory location
from the starting address of the segment. The general purpose registers can be used to store the offset. The
physical address of a memory location is computed by BIU by appending 0H to four LSBs of base address
and then adding 16-bit offset to it. For example if segment register stores base address of 4422 H and offset
is 1423 H then physical address of memory location is 44220H +1423 H = 45643H. A program can access
the code and data in segments by changing the content of segment register. Segmentation is used to increase
the execution speed of computer system so that processor is able to fetch and execute the data from memory
easily and fastly. Four segment register of Intel 8086 are discussed as follows,
Code Segment Register (CS): The code segment of the memory is used to store the instruction codes of
the program. A code segment register is 16 bit register used to store the starting address of the code segment
currently being used. The processor uses CS for all accesses to instructions referenced by instruction
pointer (IP) register. IP contains offset of address of the next instruction byte to be fetched. CS register
cannot be changed directly. The CS register is automatically updated during far jump, far call and far return
instructions. BIU computes the 20-bit physical address by shifting the contents of CS 4-bits to the left and
then adding the 16-bit contents of IP.
Stack Segment Register (SS): Stack segment is used to store the data and instructions of a subroutine. It
also holds the data of registers or memory given in PUSH instruction. Stack segment register is a 16-bit
register containing base address of current stack. By default, the processor assumes that all data referenced
by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be
changed directly using POP instruction.
Data Segment Register (DS): The data, variables and constants are stored in data segment of the memory.
Data segment register is a 16-bit register used to store current address of 64KB data segment. By default, the
processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI,
DI) is stored in the data segment. Contents of DS can be changed directly using POP and LDS instructions.
Extra Segment Register (ES): Extra segment register is a 16-bit register containing address of 64KB
segment, usually with program data. By default, the processor assumes that the DI register references the
ES segment in string manipulation instructions. ES register can be changed directly using POP and LES
instructions.
The default segments used by general purpose registers and index registers can be changed by using CS, SS,
DS and ES as prefix of the instructions. Logical address used as operand in an instruction is always a 16-bit
address but physical address of a memory location has 20 bits. The 20-bit memory physical memory address
is computed using contents of segment register and effect memory address or offset. The offset depends on
the addressing mode of the instruction. For example the contents of stack segment register and stack pointer
are used to compute address in stack location to be accessed during execution of stack related instructions
such as PUSH, POP, CALL or RET. The index registers SI and DI together with segment registers DS
and ES are used to for calculation of physical address in instructions related to string manipulations. The
registers SI & DS are used to compute the source address and DI & ES are used to compute destination
address in string operations.
Note : The effective address (EA) is a 16-bit offset of the storage location of the operand from the current value in
the data segment (DS) register. EA is combined with the contents of DS in the BIU to produce the physical
address of the operand. By default BX, SI and DI registers work with DS segment register and BP & SP
work with SS segment register. Other general purpose registers cannot form an effective address. Also,
although BX can form an effective address, BH and BL cannot.
9.6.4 Instructions Pointer (IP)
The instruction pointer (IP) is used to point to the memory location of next instruction to be fetched from
the memory. Its function is similar the program counter of 8085 microprocessor. The instruction pointer
is incremented automatically by one after fetching a code /data from the memory. The address of next
instruction code to be fetched from the memory is computed with the help of contents of instruction pointer
and code segment (CS) register (as CS:IP). This is done during fetching of an instruction code.
AH
}
Accumulator AX AL
Base BX BH BL General Purpose
Counter CX
Data DX
Stack Pointer
CH
DH
SP
CL
DL
Registers
Segment
Registers
} CS
DS
SS
Code Segment
Data Segment
Stack Segment
Base Pinter
Sourse Index
Destination Index
Status Register
BP
SI
DI
FLAGS
} Pointer and
Index
Registers
ES
IP
Extra Segment
Instruction Pointer
9.3 Register Organization of Intel 8086

9.6.5 Status/Flag Register
The microprocessor 8086 has a 16-bit register to reflect the status of an operation performed by the processor.
This status register is also known as flag register or program status word (PSW). Only 9 bits out of 16 bits
of status register are used to reflect status of various flags. Out of 9 flags, 3 flags are used as control flags
and remaining 6 are used as condition flags. The bit positions of the all the 9 flags are shown in Fig. 9.5.
Conditional Flags : The six conditional flags are of microprocessor 8086 are carry flag (CF), auxiliary carry
flag (AF), zero flag (ZF), sign flag (SF), parity flag (PF) and overflow flag (OF). These flags are set/reset by
the processor after the execution of an arithmetic or logical instruction.
i. Carry Flag (CY) : The carry flag is set whenever a carry is generated during unsigned arithmetic. It is
also used in multiple-precision arithmetic.
ii. Auxiliary Flag (AC) : An auxiliary carry flag is set whenever a carry/barrow is generated from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7). In other words the AC flag is set when carry is given
by D3 bit to D4. This flag is not accessible to programmer. It is used by processor internally during
BCD arithmetic.
iii. Parity Flag (PF) : This flag is used to indicate the parity of result. If lower order 8-bits of the result
contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset.
iv Zero Flag (ZF) : It is set if the result of arithmetic or logical operation is zero else it is reset.
v. Sign Flag (SF) : In sign magnitude format the sign of number is indicated by MSB bit. The sign flag is
set if MSB of the result is set.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X OF DF IF TF SF ZF X AF X PF X CF
Over flow flag Carry flag

Parity flag
Direction flag Auxiliary carry flag
Interrupt enable flag Zero flag
Trap flag Sign flag
Fig. 9.5 StatusFlags of 8086
Control Flags :
Out of nine flags of Intel 8086 five flags i.e. carry, auxiliary carry, zero, sign and parity flags are same as
that of 8085 microprocessor. Overflow, trap, interrupt and direction flags are four new flags introduced in
8086. Control flags are set or reset deliberately to control the operations of the execution unit. These new
flags introduced in Intel 8086 are discussed as under,
i. Overflow Flag (OF) : The overflow flag (OF) is set if result of operation on signed numbers is out of
range else it is reset. Therefore, the overflow flag is set if the result of operation on signed numbers
is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of
16-bit sign operations.
ii. Trap Flag (TF) : Trap flag is used for single step control. It allows user to execute one instruction of
a program at a time for debugging. Program can be run in a single step mode when the trap flag (TF)
is set. If this flag is set, the processor enters the single step execution mode by generating internal
interrupts after the execution of each instruction
iii. Interrupt Flag (IF) : The interrupt flag (IF) is used to enable/disable interrupt INTR of 8086. INTR
is enabled when IF flag is set and it is disabled when IF flag is reset. The IF flag can be set using STI
instruction and reset using CLI instruction. The IF flag is automatically reset when an interrupt is
acknowledged. So, the interrupt INTR is disabled automatically whenever an interrupt is acknowledged.
The IF flag is again set at the end of a interrupt service subroutine (ISS) by using an instruction called
IRET.
iv. Directinal flag (DF) : The direction flag (DF) is used for string operation. When DF flag is set the
string bytes are fetched from higher memory address to lower memory addresses and when it is reset
the string bytes are fetched from lower memory address to higher memory addresses . The DF can
be set using STD instruction and reset using CLD instruction. If DF is set during execution of MOV
instructions the contents of index registers SI and DI are automatically decremented by the processor
to access the string from highest address to lowest address and if DF is reset during execution of MOV
instruction the contents of SI and DI are automatically incremented by processor to access the string
from lowest address to highest address.
9.7 Interrupts of 8086

Interrupts are nothing but interruption of normal execution of a program. Acknowledgment of an interrupt
means calling of interrupt service subroutine (ISS). An interrupt can be caused by either hardware or
software. Interrupt due to external device is called hardware interrupt. INTR and NMI are two hardware
interrupts of the 8086 microprocessor. The interrupts either due to internal abnormal condition such as
overflow, divide by zero etc. or due to software instruction INT are called software interrupts. The INT
instruction is inserted for debugging of a program. The Intel 8086 microprocessor can handle 256 different
hardware and software interrupts.
9.7.1 Interrupt Vector Table
A memory of 1 KB used from memory address 00000 to 003FF H is used specifically for storing starting
addresses of interrupt service subroutine (ISS). Four bytes of memory is required to store starting address
of each ISS where two bytes are used to store contents of code segment (CS) and two bytes for saving
of contents of instruction pointer (IP). The starting address of ISS is called interrupt vector or interrupt
pointer. The total memory space of 1 KB used for starting address of ISS is called interrupt vector table
or interrupt pointer table. The interrupt vector table of 8086 is shown in Fig. 9.6. The interrupt vector
table of 8086 contains 256 entries each of four byte,containing the CS:IP interrupt vectors for each of
the 256 possible interrupts. The table is used to locate the interrupt service routine addresses for each
interrupt. The Interrupt vector table is located in the first 1024 bytes of memory at addresses 00000H-
003FFH.It contains the address(segment and offset)of the interrupt service provider. The 256 interrupts
are numbered from 0 to 255 ( 00 to FF H) The number assigned to an interrupt is called its type number.
For example all the interrupts are numbered from Type 0, Type 1, Type 2........ Type 255. As four bytes
of memory are required to store starting address of an interrupt service routine therefore, Type × 4 gives
the starting address of ISS in interrupt pointer table. Out of 256 interrupts pointers first five interrupts are
used for specific purpose such as divide by zero, single step control, nonmaskable interrupt (NMI), break
point and overflow interrupts. The interrupt pointers from Type 5 to Type 31 can be used by processor
designed for some special purpose interrupts in 8086, however these interrupts have been reserved for other
advanced processors. The remaining upper 224 interrupts, from Type 32 to Type 255 are available to users
for hardware and software interrupts.
9.7.2 Hardware interrupts of 8086
The microprocessor 8086 has been provided with two hardware interrupts called NMI and INTR. These
two dedicated pins provided on 8086 chip. NMI stands for a non-maskable interrupt. This interrupt cannot
be masked using a software instruction. This interrupt is used for emergent situation such as power failure.
NMI can be used to save data in case of power failure of processor kit. The interrupt service subroutine
(ISS) for Type 2 interrupt is reserved for NMI interrupt. The ISS of Types 2 interrupt saves the program
after power failure in a RAM provided with battery back up. This program is saved in RAM can be restored
again from the point at which it was interrupted. INTR is a maskable hardware interrupt. It is enabled and
disabled using interrupt flag (IF). acknowledgment.
Request of INTR inerrupt is initiated by an external device and processor generates interrupt acknowledgment
signals on INTA pin. The microprocessor executes to bus cycles in reponse to INTR. During first cycle
the processor sends the signal signals on INTA pin to external device to be ready and then sends the signal
on the same INTA pin to ask the device to send the type of interrupt through lower order data bus. The
interrupt type is an eight bite number which is then multiplied by four to get starting address of ISS from
interrupt pointer table. When INTR interrupt is acknowledged the signal on pin LOCK goes low from T2
T-state of the 1st acknowledge cycle until T2 T-state of the 2nd acknowledge cycle. No request is acknowledged
by processor on HOLD pin till the end of the 2nd bus cycle of interrupt
003FF }
Available for users
from type 32 to
type 224 for INT
and INTR instructions
} 4N+4
~
~ ~
~
}
Pinjter for
Type 225
Pointer for
Type N
00080
Reserved
but unassigned
} 0007E
0007C
~ ~
~ ~
Reserved for INTO
instruction (overflow) } 00014 } Pointer for
Type 4
Reserved for
Break-point interrupt } 00010
} Pointer for
Type 3
Reserved for
nonmaskable interrupt
} 0000C
} Pointer for
Type 2
Reserved for
Single-step } 00008 [CS] for type1 } Pointer for
Type 1
[IP] for type1
Reserved for
divide by zero error } 00004 [CS] for type 0
} Pointer for
[IP] for type 0 Type 0
00000
Fig. 9.6 The interrupt pointers of 8086
9.7.3 LOCK
LOCK can be used as prefix to an instruction of microprocessor 8086. The instruction becomes non-
interruptible when prefix LOCK is used with an instruction. LOCK is used in multiprocessor system with
common resources. When a processor executes an instruction which uses common resources with a common
system bus it should not be interrupted. In such case any other processor must be prevented from using the
common resources and system bus. This can be done by prefixing instruction with LOCK. The pin LOCK
of 8086 becomes low when prefix LOCK is used with an instruction. The pin LOCK remains low until
the instruction with LOCK prefix is completed. The bus controller does not allow any other processor to
take control of the system bus if LOCK pin is low.
9.8 Bus Cycle of 8086

The microprocessor 8086 requires four clock cycles for accessing memory or I/O devices this group of four
clock cycles is called bus cycle. The bus cycles can be a read cycle and write cycle. For reading operation
with memory or I/O devices is called memory read or I/O read bus cycle and for writing on memory or I/O
devices is called memory write and I/O write cycle. The concept of machine cycle is no longer applicable
for 8086 microprocessor. The execution unit takes a few clock cycles for execution of an instruction but this
group of clock cycles does constitute a machine cycle. Bus Interface Unit (BIU) fetches instructions and
operands from the memory which requires one bus cycle during every reading or fetching operation. Fig.
9.7 demonstrates the timing diagram for memory read for minimum mode of operation.
During clock T1 the memory is accessed by sending 20-bit address of memory location on address, ALE
signal is goes high so that address lines AD0-AD15 carry 16 LSBs of the address and A16-A19 carry four MSBs
of the address. M / IO is high during T1 because it is memory read operation. The address remains on the
address lines only during T1 because these lines operate in multiplexed mode. During T2 the ALE signal goes
low, AD0-AD15 lines enter into high impedance state and read signal RD goes low.
The 16-bit data are transmitted on lines AD0-AD15 during T3 and T4. The higher order address lines A16-A19
carry the status signals S3, S4, S5 and S6 during T2, T3 and T4 . The signal on line MN / MX is high which
indicates that microprocessor operates in minimum mode. RD signal goes high again in T4. The signal
DT / R is used with transceiver 8286 or 8287. It goes low during T1 because processor is in data receiving
mode in memory read bus cycle. The signal DEN is also used for data enable of transceiver 8286/8287.
It goes low during T2 and becomes high again during T4. The signals DT / R and DEN are used to control
bidirectional flow of data through latched buffers. These signals are specially designed to work with
transceiver 8286/8287. The combination of BHE and A0 is used to decide data to be transferred from/to
memory location is 16-bit data word or a single byte. The signal BHE is used to identify high order byte of
word and A0 is used to indentify low order byte. During T2, T3 and T4 the signal on BHE line is status signal S7.
One Bus Cycle

T1 T2 T3 T4
CLK
AD0-AD15 Address Data

A16-A19
Address Status
S3-S6
MN/MX
M/IO
ALE
S7
BHE/S7 BHE
RD
DT/R
DEN
Fig. 9.7 Timing Diagram of Intel 8086 for Memory Read in Minimum Mode
For transferred of whole 16-bit word or a single byte byte of the work the status of BHE and A0 is as follows :
BHE A0
0 0 Whole word is transferred
0 1 Upper byte from/to odd address
1 1 Lower byte from/to even address
1 1 None
The status signals S3 and S4 are responsible for identification of a memory segment to be accessed. The
signal S5 is interrupt enable status. The signal S6 is always zero for memory access. The combination of
signals S3 and S4 for access of memory is as follows :
S4 S3
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access or no access
1 1 Data segment access
Data reading and writing operations with the Memory:

I. One word or 16-bit data reading operation with memory
If first byte of the data is stored at an even address , 8086 can read the entire word in one operation. For
example the instruction MOV BX, [00220] reads the first byte from 00220 and stores the data in BL
then reads the second byte from 00221 location and stores it in BH.
If the first byte of the data is stored at an odd address, 8086 needs two operations to read the 16-bit data.
For example the instruction MOV BX, [00221] first reads the data from the 00220 location discards it
then processor reads the first byte of 16-bit data from 00221 location and stores it in register BL. In 2nd
operation, 8086 reads the second byte of 16-bit data from the 00222 location and stores it in register BH
and discards the data of 00223 location.
II. One byte or 8-bit data reading operation with memory
Byte reading or writing from memory always require single operation. For example the instruction
MOV BH, [00220] reads the first byte from 00220 location and stores the data in BH then reads the 2nd
byte from the 00221 location and ignores it
Similarly, the instruction MOV BH, [ 00521] reads the first byte from 00520 location and ignores it then
reads the 2nd byte from the 00521 location and stores the data in BH.
9.9 Configurations of 8086 System for Minimum and Maximum Modes

i. Minimum mode configuration
The typical configuration of a 8086 microprocessor based system for minimum mode operation is
demonstrated in Fig. 9.8. The 8086 is operated in maximum mode by connecting MN/MX pin to +VCC.
The microprocessor itself generates all the control signals in minimum mode of operation. There is a one
microprocessor in the minimum mode system. The configuration of 8086 microprocessor based system
consists of 8282 based latches, 8286/8287 based 8bit bipolar trans-receivers with 3-state outputs, 8284 A
based clock generator, memory and I/O devices. The 8287 inverts the input data at its output terminals
whereas the 8286 does not. The latches are controlled using ALE signal. These are used for separating the
address from address/data signals. Trans-receiver 8286 is a bidirectional buffer or data amplifier. Trans-
receivers are used to separate the valid data from the time multiplexed address/data signal. Trans-receivers
are controlled by two signals, namely, DEN and DT/R . Since 8086 CPU has 20 address lines and 16 data
lines, so it requires three octal address latches and two octal data buffers for the complete address and data
separation.
Crystal Oscillator vCC

MN/MX
RD
WR
Clock Generator CLK M/IO
8284A
READY
RST RDY RESET
8086 ALE STB

CPU RAM,
From Interrupt GND OE PROM,
Controller INTR BHE Latch Address Peripherals,
8282 Interrupt
AD0-AD15 ADDR/DATA (3 no.) Controller,
To Interrupt
Controller INTA A16-A19 DMA
Controller
From DMA etc.
HOLD
Controller
Transceiver
To DMA 8286 Data
HLDA DT/R
Controller T (2 no.)
DEN DE
Fig. 9.8 Configuration of a 8086 system in the minimum mode .

ii. Maximum mode configuration
The typical configuration of a 8086 microprocessor based system for maximum mode operation is shown
in Fig. 9.9. In addition to latches and bus transceivers, a bus controller 8288 is also employed in maximum
mode configuration. The 8086 is operated in maximum mode by connecting MN/MX pin to ground. In
maximum mode operation 8086 generates status signals S0 , S1 and S2 . Bus controller 8288 takes
S0 , S1 , S2 and CLK signals as input and generates the control signals MRDC (Memory read command),
MWTC (Memory write command), IORC (I/O read command), IOWC (I/O write command), AMWC
(Advanced memory write command), AIOWC (Advanced I/O write command), INTA , ALE, DT / R and
DEN . There may be more than one processor in maximum mode of operation. The other components
used in maximum mode are 8282 based latches, 8286/8287 based 8bit bipolar transreceivers with 3-state
outputs, 8284 A based clock generator, memory and I/O devices.
9.10 Addressing Modes of Intel 8086

The addressing mode of an instruction is the way in which an operand is specified in the instruction. The
Intel 8086 has 8 different addressing modes. There are 2 addressing modes in which operands are placed
in registers. In remaining 6 addressing modes operand is placed in a memory. The memory address of an
operand has two components called starting address of memory segment and offset. A segment register
is used to stores the 16 MSBs of the starting address of the memory segment. How an operand stored in
memory is located from starting address of memory segment is called offset or effective address. The
memory address of an operand is sum of starting address of memory segment and the offset. An offset can
be determined by adding any combination of three address elements: base, index and displacement.
Displacement : An 8-bit or 16-bit immediate value given in the instruction is called displacement.
Base : The content of the base register, BX or BP is called a base.
Index : The content of the index register, SI or DI is called an index.
The addressing mode of instruction decides the combination of these address elements. The Intel 8086
has 20 address lines. The starting address of a segment is obtained by BIU by shifting 16 bits of segment
register to left by 4 bits and adding four bits of offset to it.
GND
Crystal Oscillator CLK
MN/MX
S0 MRDC (MEMR)
RAM,
S1 MWTC (MEMW)
PROM,
BUS Peripherals,
Clock Generator CLK Controller IORC (IOR)
S2 Interrupt
8284A READY 8288 Controller,
IOWC (IOR)
RST RDY RESET AMWC DMA
NC
INTA Controller
DEN etc.
8086
CPU
DT/R ALOWC
NC
ALE
From Interrupt
Controller INTR
To Interrupt STB
Controller INTA
GND OE
From DMA Latch
Controller HOLD BHE Address BUS
8282
AD0-AD15 ADDR/DATA (3 no.)
To DMA
HLDA A16-A19
Controller
Transceiver
DE 8286 DATA BUS
(2 no.)
Fig. 9.9 Configuration of a 8086 system in the maximum mode .

The addressing mode of Intel 8086 are discussed as follows,
i. Register Addressing : In register addressing the operand is placed in one of the 16-bit or 8-bit general
purpose registers and operation is performed on the contents of registers only. Examples : MOV CX,BX
; ADD DL,AL
ii Immediate Addressing : In immediate addressing the operand is a data which included in the instruction
itself. Examples : MOV BL, 40H ; ADD AX, 4365 H
iii. Direct Addressing : When offset of an operand is given in instruction as an 8-bit or 16-bit displacement
element, the addressing mode called direct addressing Examples : ADD AL, [0301];
ADD [0301], AX
iv. Register Indirect Addressing : In register indirect addressing mode the offset of the operand is stored
in a memory pointer. The memory pointer can be any one of the registers BX, BP, SI or DI. Examples
: MOV AX,[BX]; ADD AL, [SI]
v. Based Addressing : In based addressing, the offset of an operand is sum of an 8-bit or 16 bit displacement
and the contents of the base register BX or BP. Here, BX is used as a base resister for data segment, and
BP is usd as a base register for stack segment. Examples : MOV AL, [BX + 05H]; MOV AL, [BX +
1346H]
vi. Indexed Addressing : In indexed addressing mde the offset of an operand is sum of an 8-bit or 16-bit
displacement and the contents of an index register SI or DI. Examples : MOV AX, [SI + 05H]; MOV
AX, [SI + 1528H]
vii. Based Indexed Addressing : In based indexed addressing mode the offset of an operand is sum of
contents of a base register BX or BP and an index register SI or DI. Examples : ADD AX,[BX + SI],
MOV CX,[BX + SI]
viii. Based Indexed with Displacement : In this mode of addressing the offset of operand is sum of of
an 8-bit or 16 bit displacement, contents of a base register BX or BP and an index register SI or DI.
Examples : MOV AX, [BX + SI + 05]; MOV AX, [BX + SI + 1235H]
9.10.1 Segment Override Prefix(SOP)
A segment override prefix allows any segment register (DS, ES, SS, or CS) to be used as the segment when
evaluating addresses in an instruction. It is used when a default offset register is not used with its default
base segment register, but with a different base register. An override is made by adding the segment register
plus a colon to the beginning of the memory reference of the instruction as in the following examples:
MOV AX, [ES:60126] ; Use ES as the segment
MOV AX, [CS:BX] ; Use CS as the segment
MOV AX, [SS:BP+SI+3] ; Use SS as the segment
The registers and their override prefix are shown in the table below,
Register Default Segment Segment with override prefix
IP CS Never
SP SS Never
BP SS BP+DS or ES or CS
SI or DI DS ES,SS or CS
SI DS ES,SS or CS
DI ES Never
9.11 Instruction set and Programming of Intel 8086

The instruction set of 8086 can be classified in the following categories,
i. Data Transfer Instructions
ii. Arithmetic Instructions
iii. Logical or Bit Manipulation Instructions
iv. Branch Instructions
v. String Manipulation Instructions
vi. Flag Manipulation
vii. Processor Control Instructions
Note : The 8086 is two address processor and 8085 is one address processor.
Terms used in instructions and their meanings :

reg : I t stands for AX, BX, CX, DX, AH, AL, BH, BL, CH, CL, DH, DL, DI, SI, SP, BP
A : It stands for accumulator AX, AL or AH
sreg : I t stands for segment registers DS, ES, SS and CS ( CS is used only as second operand)
data : I t stands for immediate data of 8 bit or 16 bit included in instruction as operand.
disp : It stands for displacement of an 8-bit or 16-bit number.
disp8 : It stands for displacement of an 8-bit number.
disp16 : It stands for displacement of a 16-bit number.
op : op stands for operand. It can be register, memory or 8 bit or 16 bit data
addr8 : It stands for 8 bit port address
addr16 : I t stands for 16 bit address
data8 : It stands for 8 bit immediate data
data16 : It stands for 16 bit immediate data
des : It stands for destination which may be register, memory location or port
src : It stands for source which may be register, memory location or port.
mem : I t stands for the memory. Data of 8-bit or 16-bit may be transferred from memory specified in
the instruction. Four registers BX, SI, DI, BP are used to access the memory. We access different memory
locations (effective address) by using different combination of these registers inside [ ] symbols. The
supported combinations are:
[ BX + SI] [SI]
[ BX + DI] [ DI]
[ BP + SI] [16 bit data]
[ BP + DI] [BX]
[SI + disp] [ BX + SI + disp]
[ DI + disp] [ BX + DI + disp]
[ BP + disp] [ BP + SI + disp]
[ BX + disp] [ BP + DI + disp]
Note : [16 bit data] indicates the offset of memory location within Data Segemnt.
9.11.1 Data Transfer Instructions
Data transfer instructions are used to transfer the data from a source to a destination. The source can be
a registers, memory location or port address of I/O device and the destination can be register, memory
location or a port. Most of the data transfer instructions have source and destination operands of same size.
The data transfer instructions of 8086 are MOV, XCHG, PUSH, POP, IN, OUT, LOAD and STORE. No
flag is affected by data transfer instructions.
1. MOV des, src i. Copies the data from source to destination.

ii. No flag is affected.

Examples :
i. MOV reg, mem ; Copies the data from memory location to the specified register..
ii. MOV mem, reg ; Copies the data from general purpose register to memory location.
iii. MOV reg1, reg2 ; Copies the data from the specified register 2 to the register 1.
iv. MOV mem, data ; Copies the 8 or 16 bit immediate data to memory location.
v. MOV reg, data ; Copies the 8 or 16 bit immediate data to the specified register.
vi. MOV sreg, mem ; Copies the 16 bit data from memory location to the segment register.
vii. MOV mem, sreg ; Copies the 16 bit data from the segment register to memory location.
viii. MOV reg, sreg ; Copies the 16 bit data from the segment register to the specified register.
ix. MOV sreg, reg ; Copies the 16 bit data from the segment register to the specified register.
Note : i. Source and destination must have same size of data to be transferred.
ii. The move instruction cannot set value of CS and IP registers.
iii. It cannot copy contents of one segment register to another segement register.
iv. It cannot transfer data directly from one memory location to another memory location.
v. It cannot copy immediate data to a segment register.
2. XCHG op1, op2 i. Exchanges the contents of operand op1 and operand op2.
Examples :
i. XCHG reg, mem ; Exchanges the data of memory location with the specified register
ii. XCHG mem, reg ; Exchanges the data the specified register with memory location.
iii. XCHG reg1, reg2 ; Exchanges the specified register 2 with register 1
Note :
i. operand 1 and operand 2 must have same size of data to be exchanged.
ii. It cannot exchange data directly from one memory location to another memory location.
iii. It cannot exchange contents of one segment register to another segment register.
iv. No flag is affected by XCHG instruction.
3. XCHG reg i. Exchanges the contents of 16 bit specified register with AX.
4. PUSH reg/mem i. Writes the 16 bit data from specified register or memory to stack.
Examples :
i. PUSH reg ; Writes the content of 16 bit specified register on top of the stack.
ii. PUSH mem ; Writes the content of 16 bit data from memory location on top of the stack.
iii. PUSH sreg ; Writes the content of 16 bit segment register on top of the stack.
iv. PUSHF ; Writes the content of flag register on top of the stack.
Note : i. register used as operand with PUSH instruction must be of 16 bit.
ii. Stack pointer (SP) is decremented by two after execution of PUSH instruction.
5. POP reg/sreg/mem i. Reads 16 bit data from top of stack into reg/sreg/mem
Examples :
i. POP reg ; Reads the two bytes of data from top of the stack into 16 bit specified register
ii. POP sreg ; Reads the two bytes of data from top of the stack into 16 bit segment register
iii. POP mem ; Reads the two bytes of data from top of the stack into memory locations
iv. POPF ; Reads the two bytes of data from top of the stack into flag register.
Note : i. register used as operand with PUSH instruction must be of 16 bit.
ii. Stack pointer (SP) is incremented by two after execution of PUSH instruction.
6. IN A, addr i. Reads the data from I/O device connected at port address (addr) to accumulator (A).
Examples :
i. IN AL, addr8 ; Reads 8 bit data from port address addr8 to AL
ii. IN AL, DX ; Reads 8 bit data from I/O device whose port address is stored in DX to AL
iii. IN AX, addr8 ; Reads 16 bit data from port address addr8 to AX
iv. IN AX, DX ; Reads 16 bit data from I/O device whose port address is stored in DX to AX
Note : i. If port address is more than FF H or (255)10 then pointer DX should be used for storing port address.
ii. DX can be used to store the variable port address that can be changed dynamically during execution of
a program.
7. OUT addr, A i. Writes the data from accumulator (A) to I/O device connected at port address (addr).
Examples :
i. OUT addr8, AL ; Writes the 8 bit data from AL to I/O device connected at port address addr8.
ii. OUT DX, AL ; Writes the 8 bit data from AL to I/O device whose port address is stored in DX.
iii. OUT addr8, AX ; Writes the 16 bit data from AX to I/O device connected at port address addr8.
iv. OUT DX, AX ; Writes the 16 bit data from AX to I/O device whose port address is stored in DX.
Note : i. If port address is more than FF H or (255)10 then pointer DX should be used.
ii. DX can be used to store the variable port address that can be changed dynamically
8. LDS reg, mem i. Loads two words ( i.e. two 16 bit data) into specified register and data segment
register DS from the specified memory locations. First word from first two
memory locations is moved to specified register and second word from next
two memory locations is moved to DS.
Note : The specified register in LDS instruction must be a16 bit register.
9. LES reg, mem i. Loads two words ( i.e. two 16 bit data) into specified register and extra
segment register ES from the specified memory locations. First word (i.e.
offset) from first two memory locations is moved to specified register and
second word (i.e. segment) from next two memory locations is moved to ES.
Note : The specified register in LES instruction must be a16 bit register.
10. LEA reg, mem i. Load Effective Address. Loads off set address into specified register. This
instruction can also be used to determine the offset address of a variable
memory locations specified in the instruction to load it into the specified
register.
Note : The specified register in LEA instruction must be a16 bit register.
11. LAHF
i. Loads accumulator AH with lower order byte of flag register. Thus flags
loaded into AH are SF, ZF, AF, PF and CF. After execution of the instruction
contents of AH will be as under,
D7 D6 D5 D 4 D3 D 2 D1 D0
AH =
AH = SF ZF X AF X PF X CF
Note : Bits 1, 3 and 5 are reserved with D1 =1, D3 = 0, D5 = 0
12. SAHF i. Stores accumulator AH in lower order byte of flag register. Thus flags SF,
ZF, AF, PF and CF are affected by contents of AH.
Let AH = D7D6D5D4D3D2D1D0

After execution of SAHF instruction,
SF ZF AF PF CF
Lower order by of F =
F = D7 D6 D5 D 4 D3 D 2 D1 D0
ii. Flags SF, ZF, AF, PF and CF are affected.

Note : Bits 1, 3 and 5 are reserved with D1 =1, D3 = 0, D5 = 0
13.
XLAT/XLATB i. Loads data from the lookup table to AL. The register BX is loaded with
starting address of the lookup table and AL is loaded with a 8 bit data. The
offset address of lookup table is obtained by adding contents of BX and AL.
The content of memory location having an offset address of [BX]+ [AL] is
moved to AL. This instruction is used for code conversion. An element of
one code is placed in AL and corresponding other code is in the lookup table.
9.11.2 Arithmetic Instructions
Arithmetic instructions are used to perform arithmetic operation such as addition, subtraction, multiplication,
division, increment, decrement, comparison, ASCII and decimal adjustment etc.
1. ADD des, src i. Adds the content of source to content of destination and stores the result in
destination.
ii. Flags affected are OF, SF, ZF, AF, PF and CF
Examples :
i. ADD reg, mem ; Adds the contents of memory location to the contents of specified register
and stores the result in specified register.
ii. ADD mem, reg ; Adds the contents of specified register to the contents of memory location
and stores the result in the memory location.
iii. ADD reg1, reg2 ; Adds the contents of specified register 2 to the contents of specified register
1 and stores the result in the specified register 1.
iv. ADD mem, data ; Adds the given 8/16 bit immediate data to the contents memory location and
stores the result in the memory location.
v. ADD reg, data ; Adds the given 8/16 bit immediate data to the contents specified register and
stores the result in the specified register.
Note : i. Source and destination must have same size of data to be added.
ii. ADD instruction cannot be used to add contents of one memory location to another memory location.

2. ADC des, src i. Adds the content of source to content of destination along with status of carry
flag and stores the result in destination.
Examples :
i. ADC reg, mem ; Adds the contents of memory location to the contents of specified register
along with carry flag and stores the result in specified register.
ii. ADC mem, reg ; Adds the contents of specified register to the contents of memory location
along with carry flag and stores the result in the memory location.
iii. ADC reg1, reg2 ; Adds the contents of specified register 2 to the contents of specified register
1 along with carry flag and stores the result in the specified register 1.
iv. ADC mem, data ; Adds the given 8/16 bit immediate data to the contents memory location
along with carry flag and stores the result in the memory location.
v. ADC reg, data ; Adds the given 8/16 bit immediate data to the contents specified register
along with carry flag and stores the result in the specified register.
Note : i. Source and destination must have same size of data to be added.
ii. ADC instruction cannot be used to add contents of one memory location to another memory location.
3. SUB des, src i. Subtracts the content of source from content of destination and stores the
result in destination.
Examples :
i. SUB reg, mem ; Subtracts the contents of memory location from the contents of specified
register and stores the result in specified register.
ii. SUB mem, reg ; Subtracts the contents of specified register from the contents of memory
location and stores the result in the memory location.
iii. SUB reg1, reg2 ; Subtracts the contents of specified register 2 from the contents of specified
register 1 and stores the result in the specified register 1.
iv. SUB mem, data ; Subtracts the given 8/16 bit immediate data from the contents memory
location and stores the result in the memory location.
v. SUB reg, data ; Subtracts the given 8/16 bit immediate data from the contents specified
register and stores the result in the specified register.
Note : i. Source and destination must have same size of data.
ii. SUB instruction cannot be used to subtract contents of one memory location from another memory location.

4. SBB des, src i. Subtracts the content of source from content of destination along with borrow
and stores the result in destination.
Examples :
i. SBB reg, mem ; Subtracts the contents of memory location from the contents of specified
register along with borrow and stores the result in specified register.
ii. SBB mem, reg ; Subtracts the contents of specified register from the contents of memory
location along with borrow and stores the result in the memory location.
iii. SBB reg1, reg2 ; Subtracts the contents of specified register 2 from the contents of specified
register 1 along with borrow and stores the result in the specified register 1.
iv. SBB mem, data ; Subtracts the given 8/16 bit immediate data from the contents memory
location along with borrow and stores the result in the memory location.
v. SBB reg, data ; Subtracts the given 8/16 bit immediate data from the contents specified
register along with borrow and stores the result in the specified register.
ii. SUB instruction cannot be used to subtract contents of one memory location from another memory location.
5. MUL reg/mem i. Multiplies two unsigned numbers. If operand has 8 bit data (i.e. a byte)
then content of operand is multiplied with AL and result is stored in AX. If
operand has 16 bit data (i.e. a word) then operand is multiplied with AX and
lower order byte of result is stored in AX and higher order byte of result is
stored in DX. If the higher order half of result (i.e. content of AH for 8 bit
multiplication and content of DX for 16 bit multiplication) is zero overflow
flag (OF) and carry flag (CF) are reset. If higher order half is non zero then
OF and CF are set to indicate that significant bits of result are in AH and DX.
If a byte and word are multiplied then byte is extended to a word by putting
zeros in bit positions of higher order byte.
ii. Only OF and CF are affected. Remaining conditional flags are undefined.
6. IMUL reg/mem i. Multiplies two signed numbers. If operand has 8 bit data (i.e. a byte) then
content of operand is multiplied with AL and result is stored in AX. If
operand has 16 bit data (i.e. a word) then operand is multiplied with AX and
lower order byte of result is stored in AX and higher order byte of result is
stored in DX. If the higher order half of result (i.e. content of AH for 8 bit
multiplication and content of DX for 16 bit multiplication) is sign extension
of result then overflow flag (OF) and carry flag (CF) are reset. If higher order
half is not sign extension of the result then OF and CF are set to indicate that
significant bits of result are in AH and DX. If a byte and word are multiplied
then byte is extended to a word before multiplication.
ii. Only OF and CF are affected. Remaining conditional flags are undefined.
7. DIV reg/mem i. Divides one 16-bit unsigned number by an 8-bit unsigned number and
unsigned 32-bit number by a 16-bit unsigned number.
ii. The division of 32-bit number by a 16 bit number is called a 16-bit operation.
In 16-bit operation the 32-bit dividend is placed in DX and AX with higher
order word in DX and lower order word in AX and 16-bit divisor is placed
in specified register or memory location. After execution of the instruction, the
16-bit quotient of result is placed in AX and 16-bit remainder is placed in DX.
iii. The division of 16-bit number by a 8-bit number is called a 8-bit operation. In
8-bit operation the 16-bit dividend is placed in AX and 8-bit divisor is placed
in specified register or memory location. After execution of the instruction,
the 8-bit quotient of result is placed in AL and 8-bit remainder is placed in
AH.
iv. For division of an 8-bit number by an 8-bit number, the dividend is extended
to 16 bit by putting zeros in MSBs positions of AX. For division of 16-bit
number by a 16-bit number, the dividend is extended to 32 bits by putting
zeros in MSBs positions. For this purpose the 16-bit dividend is placed in
AX and zero are put in DX register. If a 32-bit number is to be divided by an
8-bit number, the 8-bit divisor is extended to 16-bit by putting zeros in all bit
positions of AH.
v. A divide by zero (Type 0) interrupt is generated if the quotient is greater than
FFFF in case 16 bit operation and greater than FF in case of 8-bit operation.
vi. No flag is affected and all conditional flags remain undefined.
8. IDIV reg/mem i. Divides one 16-bit signed number by an 8-bit signed number and signed 32-
bit number by a 16-bit signed number.
ii. The division of 32-bit number by a 16 bit number is called a 16-bit operation.
In 16-bit operation the 32-bit dividend is placed in DX and AX with higher
order word in DX and lower order word in AX and 16-bit divisor is placed
the 16-bit quotient of result is placed in AX and 16-bit remainder is placed in
DX.
iii. The division of 16-bit number by a 8-bit number is called a 8-bit operation. In
8-bit operation the 16-bit dividend is placed in AX and 8-bit divisor is placed
the 8-bit quotient of result is placed in AL and 8-bit remainder is placed in
AH.
iv. For division of an 8-bit number by an 8-bit number, the dividend is extended
to 16 bit by putting zeros in MSBs positions of AX. For division of 16-bit
number by a 16-bit number, the dividend is extended to 32 bits by putting
zeros in MSBs positions. For this purpose the 16-bit dividend is placed in
AX and zero are put in DX register. If a 32-bit number is to be divided by an
8-bit number, the 8-bit divisor is extended to 16-bit by putting zeros in all bit
positions of AH.
v. A divide by zero (Type 0) interrupt is generated if the quotient is greater than
7FFF in case 16 bit operation and greater than 7F in case of 8-bit operation.
vi. No flag is affected and all conditional flags remain undefined.
9. INC reg/mem i. Increments the contents of specified register or memory location by one.
ii. Flags affected are OF, SF, ZF, AF and PF
Note : i. Carry Flag (CF) is not affected by INC instruction
ii. Segment registers are not incremented using INC instruction.
10. DEC reg/mem i. Decrements the contents of specified register or memory location by one.
ii. Flags affected are OF, SF, ZF, AF and PF
Note : i. Carry Flag (CF) is not affected by DEC instruction
ii. Segment registers are not incremented using DEC instruction.
11. DAA i. Decimal Adjust after Addition. This instruction adjusts the result of a packed
BCD addition stored in AL to its equivalent BCD number. The equivalent
BCD in AL is obtained by using following algorithm,
step 1 : If lower nibble of result in AL > 9 or AF = 1 then:
AL = AL + 06H ;
AF = 1
step 2 : If upper nibble in AL > 9 or CF = 1 then
AL = AL + 60H ;
CF = 1
ii. Flags affected are SF, ZF, AF, PF and CF
Note : i. Overflow Flag (OF) is undefined after execution of DAA
ii. DAA works only on contents of AL.
12. DAS i. Decimal Adjust after Subtraction. This instruction adjusts the result of a
packed BCD subtraction stored in AL to its equivalent BCD number. The
equivalent BCD in AL is obtained by using algorithm,
step 1 : If lower nibble of result in AL > 9 or AF = 1 then
AL = AL − 06H ;
AF = 1
step 2 : If upper nibble in AL > 9 or CF = 1 then
AL = AL − 60H ;
CF = 1
ii. Flags affected are SF, ZF, AF, PF and CF
Note: i. Overflow Flag (OF) is undefined after execution of DAA
ii. DAS works only on contents of AL.
13. AAA i. ASCII Ajust after Addition. This instruction is used to perform operation
on data read from I/O device such as key board in ASCII format. This
instruction works on the basis of result in AL register only. It adjusts the
result of an addition stored in AH and AL when working with BCD. It works
on following algorithm,
If lower nibble of result in AL > 9 or AF = 1 then:
AL = AL + 06H
AH = AH + 01 H
AF = 1 and
CF = 1.
else
AF = 0 and CF = 0.
ii. Flags affected are AF and CF only.
Note : PF, SF, ZF and OF are undefined after execution of AAA.
14. AAD i. ASCII Ajust before Division. This instruction assumes that AH and AL
register are having unpacked BCD numbers. It adjusts two unpacked BCD
numbers in AX to its equivalent binary number. The equivalent binary number
is placed in AL. This adjustment is done before dividing two unpacked BCD
numbers in AX with an unpacked BCD number. After division unpacked
BCD quotient is stored in AL and unpacked BCD remainder is stored in AH.
The algorithm used is as under,
AL = AL + (AH * 0AH)
AH = 0
in both cases clear the upper nibble of AL.
ii. Flags affected are PF, SF and ZF.
Note : i. AF, CF and OF are undefined after execution of AAD.
ii. Numbers represented as one BCD digit per byte are called unpacked BCD. When two BCD digits are
in a single byte, such representation is called packed BCD.
15. AAM i. ASCII Adjust after Multiplication. This instruction is used after multiplication
of two unpacked BCD to get a correct result in unpacked BCD format. This
instruction work only when result of multiplication is in AL and result in
unpacked BCD format is placed in AX after execution of this instruction. The
algorithm used is as under,
AH = AL / 0AH
AL = Remainder
ii. Flags affected are SF, ZF and PF.
Note : AF, CF and OF are undefined after execution of AAM.
16. AAS i. ASCII Adjust after Subtraction. This instruction is used to convert result of
subtraction of ASCII code of number from ASCII code of another number to
it BCD equivalent. This instruction is used to subtract ASCII code from input
device of 8086. It works on the basis of result in AL register only. It works on
following algorithm,
If lower nibble of result in AL > 9 or AF = 1 then :
AL = AL − 06H
AH = AH − 01 H
AF = 1 and
CF = 1.
else
AF = 0 and CF = 0.
in both cases clear the upper nibble of AL.
ii. Flags affected are AF and CF.
Note : SF, ZF, PF and OF are undefined after execution of AAS.
17. CBW i. Convert Byte to Word. This instruction converts a byte in AL to a word in
AX. It replaces all bit positions of AH with value of MSB of AL. If MSB
of AL is ‘1’ then content of AH becomes FFH and if MSB of AL is ‘0’ then
content of AH beocomes 00H.
Note : This instruction is used before a signed operation using IDIV and IMUL instructions.
18. CWD i. Convert Word to Double Word. This instruction converts a word in AX to a
double word stored in DX and AX. It replaces all bit positions of DX with
value of MSB of AX. If MSB of AX is ‘1’ then content of DX becomes FFFF
H and if MSB of AL is ‘0’ then content of DX becomes 0000 H.
Note : This instruction is used before a signed operation using IDIV instruction.
18. NEG reg/mem i. This instruction is used to makes contents of operand negative. It gets 2’s
complement of number stored in specified register or memory. The operation
is performed by inverting bit of number and then adding 01H to the inverted
number.
ii. Flags affected are SF, ZF, AF, PF , OF and CF
19. CMP op1, op2 i. This instruction compares the contents of operand 2 with operand 1. The
comparison is done by subtracting the contents operand 2 from contents of
operand 1 without changing contents operand 1 and operand 2. The result of
comparison is reflected by status of conditional flags.
Examples :
i. CMP reg, mem ; Compares the contents of memory location with the contents of specified
register.
ii. CMP mem, reg ; Compares the contents of specified register with the contents of memory
location.
iii. CMP reg1, reg2 ; Compares the contents of specified register 2 with the contents of specified
register 1.
iv. CMP mem, data ; Compares the given 8/16 bit immediate data with the contents memory
location.
v. CMP reg, data ; Compares the given 8/16 bit immediate data with the contents specified
register.
Note : i. Both operands must be having same size of data.
ii. CMP instruction cannot be used to add contents of one memory location to another memory location.
9.11.3 Logical Instructions

This group of instruction is used to perform logical , shifting and rotate operations. Thses instructions are
discussed as under,
1. AND des, src i. Performs logical AND operation between contents of source and destination
and result is stored in destination.
ii. CF and OF are reset. SF, ZF and PF are affected according to the result and
AF is undefined.
Examples :
i. AND reg, mem ; Performs logical AND operation between the contents of memory location
and the contents of specified register and stores the result in specified register.
ii. AND mem, reg ; Performs logical AND operation between the contents of specified register
and the contents of memory location and stores the result in the memory
location.
iii. AND reg1, reg2 ; Performs logical AND operation between the contents of specified register
2 and the contents of specified register 1 and stores the result in the specified
register 1.
iv. AND mem, data ; Performs logical AND operation between the given 8/16 bit immediate
data and the contents memory location and stores the result in the memory
location.
v. AND reg, data ; Performs logical AND operation between the given 8/16 bit immediate
data and the contents specified register and stores the result in the specified
register.
ii. AND instruction cannot be used perform AND operation on contents of one memory location to another
memory location.
2. OR des, src i. Performs logical OR operation between contents of source and destination
AF is undefined.
Examples :
i. OR reg, mem ; Performs logical OR operation between the contents of memory location and
the contents of specified register and stores the result in specified register.
ii. OR mem, reg ; Performs logical OR operation between the contents of specified register and
the contents of memory location and stores the result in the memory location.
iii. OR reg1, reg2 ; Performs logical OR operation between the contents of specified register 2
and the contents of specified register 1 and stores the result in the specified
register 1.
iv. OR mem, data ; Performs logical OR operation between the given 8/16 bit immediate data and
the contents memory location and stores the result in the memory location.
v. OR reg, data ; Performs logical OR operation between the given 8/16 bit immediate data and
the contents specified register and stores the result in the specified register.
ii. OR instruction cannot be used perform OR operation on contents of one memory location to another
memory location.
3. XOR des, src i. Performs logical XOR operation between contents of source and destination
AF is undefined.
Examples :
i. XOR reg, mem ; Performs logical XOR operation between the contents of memory location
and the contents of specified register and stores the result in specified register.
ii. XOR mem, reg ; Performs logical XOR operation between the contents of specified register
and the contents of memory location and stores the result in the memory
location.
iii. XOR reg1, reg2 ; Performs logical XOR operation between the contents of specified register
2 and the contents of specified register 1 and stores the result in the specified
register 1.
iv. XOR mem, data ; Performs logical XOR operation between the given 8/16 bit immediate
data and the contents memory location and stores the result in the memory
location.
v. XOR reg, data ; Performs logical XOR operation between the given 8/16 bit immediate
data and the contents specified register and stores the result in the specified
register.
ii. XOR instruction cannot be used perform XOR operation on contents of one memory location to another
memory location.
4. NOT reg/mem i. Performs logical NOT operation on contents of specified register or memory.
5. TEST des, src i. Performs logical AND operation between contents of source and destination
and contents of destination and source remain unaffected after operation. The
result is not stored anywhere.
AF is undefined.
Examples :
i. TEST reg, mem ; Performs logical AND operation between the contents of memory location
and the contents of specified register. The contents of register and memory
remain unaffected after operation.
ii. TEST mem, reg ; Performs logical AND operation between the contents of specified register
and the contents of memory location. The contents of memory and register
iii. TEST reg1, reg2 ; Performs logical AND operation between the contents of specified register 2
and the contents of specified register 1. The contents of register 2 and register
1 remain unaffected after operation.
iv. TEST mem, data ; Performs logical AND operation between the given 8/16 bit immediate data
and the contents memory location. The contents of memory and the given
data remain unaffected after operation.
v. TEST reg, data ; Performs logical AND operation between the given 8/16 bit immediate data
and the contents specified register. The contents of register and the given data
6. RCL reg/mem, count i. This instruction rotates all bits of specified register or memory to left by
specified count number through carry flag. The rotation is performed by
shifting MSB of operand to CF and CF to LSB.
CF Register /memory
MSB LSB

ii. If the count number is one then it is included in instruction as an operand. If
the count is more than one then it is specified by the content of CL register.
iii. Only CF and OF are affected.
Examples :
i. RCL reg, 01H ; Rotates all bits of specified register to left by one position through carry flag.
ii. RCL mem, 01H ; Rotates all bits of specified memory location to left by one position through
carry flag.
iii. RCL reg, CL ; Rotates all bits of specified register to left by a count number stored in CL
through carry flag.
iv. RCL mem, CL ; Rotates all bits of specified memory location to left by a count number stored
in CL through carry flag.
7. RCR reg/mem, count i. This instruction rotates all bits of specified register or memory to right by
specified count number through carry flag. Operation is performed by shifting
CF to MSB and LSB to CF.
CF Register/memory
MSB LSB

Examples :
i. RCR reg, 01H ; Rotates all bits of specified register to right by one position through carry
flag.
ii. RCR mem, 01H ; Rotates all bits of specified memory location to right by one position through
carry flag.
iii. RCR reg, CL ; Rotates all bits of specified register to right by a count number stored in CL
through carry flag..
iv. RCR mem, CL ; Rotates all bits of specified memory location to right by a count number
stored in CL through carry flag..
8. ROL reg/mem, count i. This instruction rotates all bits of specified register or memory to left by
specified count number. The rotation is performed by shifting MSB of
operand to CF as well as to LSB of operand.
CF Register /memory
MSB LSB

Examples :
i. ROL reg, 01H ; Rotates all bits of specified register to left by one position.
ii. ROL mem, 01H ; Rotates all bits of specified memory location to left by one position.
iii. ROL reg, CL ; Rotates all bits of specified register to left by a count number stored in CL.
iv. ROL mem, CL ; Rotates all bits of specified memory location to left by a count number stored
in CL.
9. ROR reg/mem, count i. This instruction rotates all bits of specified register or memory to right by
specified count number. The rotation is performed by shifting LSB of operand
to CF as well as to MSB of operand.
CF Register/memory
MSB LSB
0000
Examples :
i. ROR reg, 01H ; Rotates all bits of specified register to right by one position.
ii. ROR mem, 01H ; Rotates all bits of specified memory location to right by one position.
iii. ROR reg, CL ; Rotates all bits of specified register to right by a count number stored in CL.
iv. ROR mem, CL ; Rotates all bits of specified memory location to right by a count number
stored in CL.
10. SAL reg/mem, count i. This instruction shifts all bits of specified register or memory to left by
specified count number. The shifting is performed by shifting MSB of
operand to CF and inserting ‘0’ in LSB position of operand.
CF Register /memory
MSB LSB
0

Examples :
i. SAL reg, 01H ; Shifts all bits of specified register to left by one position.
ii. SAL mem, 01H ; Shifts all bits of specified memory location to left by one position.
iii. SAL reg, CL ; Shifts all bits of specified register to left by a count number stored in CL.
iv. SAL mem, CL ; Shifts all bits of specified memory location to left by a count number stored
in CL.
11. SHL reg/mem, count i. This instruction shifts all bits of specified register or memory to left by
specified count number. The shifting is performed by shifting MSB of
operand to CF and inserting ‘0’ in LSB position of operand.
CF Register /memory
MSB LSB
0

iii. Flags affected are CF and OF.
Examples :
i. SHL reg, 01H ; Shifts all bits of specified register to left by one position.
ii. SHL mem, 01H ; Shifts all bits of specified memory location to left by one position.
iii. SHL reg, CL ; Shifts all bits of specified register to left by a count number stored in CL.
iv. SHL mem, CL ; Shifts all bits of specified memory location to left by a count number stored
in CL.
12. SAR reg/mem, count i. This instruction shifts all bits of specified register or memory to right by
specified count number. This instruction is used for shifting of a signed
number. The shifting is performed by shifting LSB of operand to CF and
MSB which is sign bit is retained in MSB position.
CF Register/memory
MSB LSB

Examples :
i. SAR reg, 01H ; Shifts all bits of specified register to right by one position.
ii. SAR mem, 01H ; Shifts all bits of specified memory location to right by one position.
iii. SAR reg, CL ; Shifts all bits of specified register to right by a count number stored in CL.
iv. SAR mem, CL ; Shifts all bits of specified memory location to right by a count number stored
in CL.
13. SHR reg/mem, count i. This instruction shifts all bits of specified register or memory to right by
specified count number. The shifting is performed by shifting LSB of
operand to CF and inserting ‘0’ in MSB position of operand.
CF Register/memory
MSB LSB
0

iii. Flags affected are CF and OF.
Examples :
i. SHR reg, 01H ; Shifts all bits of specified register to right by one position with ‘0’ in MSB.
ii. SHR mem, 01H ; Shifts all bits of specified memory location to right by one position. with ‘0’
in MSB.
iii. SHR reg, CL ; Shifts all bits of specified register to right by a count number stored in CL
with ‘0’ in MSB..
iv. SHR mem, CL ; Shifts all bits of specified memory location to right by a count number stored
in CL with ‘0’ in MSB.
9.11.4 Branch Instructions

Program execution control instructions include jump, call and return instructions. These instructions are
discussed as follows:
I. Jump Instructions
Jump instructions are used to change the sequence of execution of a program conditionally or unconditionally.
When the execution is transferred to another segment the jump is termed as inter-segment or far jump and
when the execution is transferred within same segment the jump is known as near jump. Both IP and CS are
updated with new values in far jump whereas only IP is updated with new value and CS remains unchanged
in near jump.
A. Unconditional Jump
1. JMP des i. Jump the execution to destination address unconditionally.
Examples :
i. JMP addr ; Jump the execution to specified memory address unconditionally. It is far
jump. IP carries the offset address and CS carries segment 16-bit segment
address. It is inter-segment or far jump. Here addr has two parts first part is
16-bit offset and second part is 16 bit segment address. e.g. addr = 1243H :
5432H, where 1243H represent offset and 5432 H represent segment address.
When processor executes this instruction first two bytes of addr are loaded
in IP and remaining two bytes are loaded in CS.
ii. JMP disp8 ; Jump the execution to the label unconditionally. Here disp8 is an 8-bit signed
displacement. The signed displacement of 8-bit is added to contents IP and
CS remains unchanged. It is intra-segment or near jump.
iii. JMP disp16 ; Jump the execution to the label unconditionally. Here disp16 is a 16-bit
unsigned displacement. The unsigned displacement of 16-bit is added to
contents IP and CS remains unchanged. It is an intra-segment or near jump.
iv. JMP mem ; It is inter-segment or far jump. The 16-bit content of given memory location
is loaded in IP and 16-bit content of next memory locations is placed in CS.
It uses indirect addressing.
v. JMP reg/mem ; It is an intra-segment or near jump. The contents of specified register or
memory are loaded in IP and CS remains unchanged.
B. Conditional Jump
These instructions have signed 8-bit displacement as label. Conditional jumps are always intra-segment or
near jumps. The near jump must in the range of –128 bytes to +127 bytes.
i. JA disp8 ; Jump if above
JNBE disp 8 ; Jump is not below or equal.
; Execution jumps to label if both CF and ZF are reset (i.e. zero).
; Both of these instructions perform same operation and have same instruction
code.
; The terms above and below are used when we consider the magnitude of two
unsigned numbers.
ii. JAE disp8 ; Jump if above or equal
JNB disp 8 ; Jump if not below
JNC disp 8 ; Jump if no carry
; Execution jumps if CF is reset.
; All of these instructions perform same operation and have same instruction
code.
iii. JB disp8 ; Jump if below
JNAE disp 8 ; Jump if not above or equal
JC disp 8 ; Jump if carry
; Execution jumps if CF is set.
; All of these instructions perform same operation and have same instruction code.
unsigned numbers.
iv. JBE disp8 ; Jump if below or equal.
JNA disp 8 ; Jump if not above
; Execution jumps if bot CF and ZF are set.
; Both of these instructions perform same operation and have same instruction code.
unsigned numbers.
v. JE disp8 ; Jump if equal
JZ disp 8 ; Jump if zero
; Execution jumps if ZF is set.
; Both of these instructions perform same operation and have same instruction code.
vi. JG disp8 ; Jump if greater
JNLE disp 8 ; Jump if not less or equal
; These instructions are used after comparison of two signed numbers. Here
greater means more positive.
code.
vii. JGE disp8 ; Jump if greater or equal
JNL disp 8 ; Jump if not less
; Execution jumps if SF = OF.
code.
viii. JNGE disp 8 ; Jump if not greater or equal
JL disp8 ; Jump if less
; Execution jumps if SF ≠ OF.
code.
ix. JNG disp 8 ; Jump if not greater
JLE disp8 ; Jump if less or equal
; Execution jumps if ZF is set and SF ≠ OF.
code.
x. JCXZ disp8 ; Jump if contents of count register CX = 0
Note : Unconditional jump can be near or far jump whereas conditional jumps are always near jumps.
II. Call Instructions
CALL instructions are used to transfer execution control of program to a subroutine either stored within
the current code segment or stored in a different code segment. Near CALL is used to access the subroutine
stored with the current code segment where as far CALL is used to access the subroutine stored in a segment
different from current segment. When far CALL is executed the processor saves the value of CS followed
by value of IP on the top of the stack and then transfer the execution to subroutine. The new values of IP
and CS are obtained by loading IP and CS from given operand. The far call is also called inter-segment call.
When near CALL is executed the processor saves the value of IP on the top of the stack and then transfer
the execution to subroutine. The new values of IP is obtained by loading IP from given operand. The value
of CS remains unchanged in a near CALL. The near call is also called intra-segment call. At the end of the
subroutine a return instruction is included to return the execution back to the main program.
1. CALL des i. Call the subroutine stored at address beginning with given destination
address.
Examples :
i. CALL addr ; Call the subroutine from the specified memory address. IP carries the offset
address and CS carries segment 16-bit segment address. Here addr has 4
bytes. For two bytes are used for 16-bit offset and second two bytes are used
16 bit segment address. e.g. addr = 1243H : 5432H, where 1243H represent
offset and 5432 H represent content of segment address. When processor
executes this instruction the value of CS followed by value of IP for the next
instruction of the main program are saved in the top of the stack. The new
values of IP and CS are obtained by loading first two bytes of addr in IP and
remaining two bytes of addr loaded in CS. It is a inter-segment or far call.
ii. CALL mem ; Call the subroutine from address stored at given memory locations. It is
also a inter-segment or far call. The offset of address is stored at first two
locations and address of code segment is stored at next two locations of the
given memory address. Thus new value of IP is loaded with content of first
two memory locations and new value of CS is loaded with contents of next
two memory locations.
iii. CALL disp16 ; Call the subroutine having address with displacement specified in the
instruction. Here disp16 is a 16-bit unsigned displacement. The unsigned
displacement of 16-bit is added to contents IP to get effective address. CS
remains unchanged. It is an intra-segment or near call.
v. CALL reg/mem ; It is an intra-segment or near call. The contents of specified register or
memory are loaded as new value of IP and CS remains unchanged.
III. Return Instructions

Return instructions are used for return of execution from a subroutine to the calling main program. Return
instruction is always the last instruction to be executed in the subroutine. When return instruction is executed
the processor loads IP and then CS with the contents of top of the stack and execution is returned to the next
instruction to CALL instruction in the main program.
1. RET i. Return to the calling program. IP is loaded with offset from the top of the
stack. It is an intra-segment or near return.
2. RET disp16 i. Return to the calling program. First IP is loaded with offset from the top
of the stack. It is an intra-segment or near return. Further, 16-bit unsigned
displacement is added to the stack pointer SP. This has the effect of adjusting
stack pointer past parameters that might have been placed onto the stack
prior to the CALL that corresponds this RET.
3. RETF i. Return to the calling program. First IP is loaded with offset from the top
of the stack and then CS is loaded with address of code segment from next
locations of the stack. It is an inter-segment or far return.
4. RETF disp16 i. Return to the calling program. First IP is loaded with offset from the top
of the stack and then CS is loaded with address of code segment from next
locations of the stack. It is an inter-segment or far return. Further, 16-bit
unsigned displacement is added to the stack pointer SP. This has the effect of
adjusting stack pointer past parameters that might have been placed onto the
stack prior to the CALL that corresponds this RET.
5. IRET i. This instruction is used to return the execution from an interrupt service
routine to the main program. First IP is loaded with offset from the top of
the stack and then CS is loaded with address of code segment from next
locations of the stack. It is an inter-segment return. Furthermore, two bytes
from the top of the stack are poped in Flag register to restore the flag status
which were before acknowledgment of the interrupt.
ii. All flags are affected.
IV. Interrupt Instructions

1. INT data8 i. INT is a software interrupt. The operand of instruction specifies the interrupt
number. Intel 8086 can handle 256 different interrupts so the value of data8
can vary from 00 H to FF H. When this instruction is executed the contents
of flag register followed by contents of code segment (CS) register and then
contents of instruction pointer (IP) are saved on the top of the stack one by
one.
ii. IF and TF flags are reset.
2. INTO i. It is a software interrupt used to indicate condition of overflow after an

arithmetic operation. This interrupt is acknowledged if over flaw flag (OF) is
set after an arithmetic operation. Therefore, this instruction should be used
after an arithmetic instruction. When this instruction is executed the contents
of flag register followed by contents of code segment (CS) register and then
contents of instruction pointer (IP) are saved on the top of the stack one by
one.
ii. IF and TF flags are reset.
V. LOOP Instructions
Loop instructions are used to execute the same set of instructions repeatedly. These instructions require a
counter to come out of loop.
1. LOOP Label
i. Decrease CX and jump to specified label until CX = 0. When content of CX
becomes zero the execution comes out of loop to the next instruction after
LOOP.
2. LOOPZ label i. Decrement CX register and jump to specified label until
or CX ≠ 0 and ZF = 1. For jumping both conditions must be
LOOPE label
satisfied. The execution comes out of loop to the next instruction
after LOOP when either CX = 0 or ZF = 0.
3. LOOPNZ label i. Decrement CX register and jump to specified label until

or CX ≠ 0 and ZF = 0. For jumping both conditions must be
LOOPNE label satisfied. The execution comes out of loop to the next instruction
after LOOP when either CX = 0 or ZF = 1
9.11.5 String Manipulation Instructions

I. MOVS instructions
1. MOVSB i. Moves 8-bit data or a byte from the memory location pointed by SI register
to the memory location pointed by DI register. SI and DI are automatically
decremented or incremented by one to point to next elements in two strings
after execution of the instruction depending on the value of direction flag
(DF). SI and DI are incremented when DF = 0 and these registers are
decremented when DF = 1.
2. MOVSW i. Moves 16-bit data or a word from the memory locations pointed by SI register
to the memory locations pointed by DI register. SI and DI are automatically
decremented or incremented by two to point to next elements in two strings
after execution of the instruction depending on the value of direction flag
(DF). SI and DI are incremented bye 2 each when DF = 0 and these registers
are decremented by 2 each when DF = 1.
Note : i. With MOVS instructions, the count register CX can be used to hold count number of elements of string.
REP instruction is used as a prefix instruction for MOVS instruction to handle the string. Alternately,
LOOP instruction can be used after MOVS instruction for repetition.
ii. The register DI is used as a pointer to extra segment (ES) and the register SI is a used as a pointer to
data segment (DS)
II. CMPS instructions

3. CMPSB i. It is a string instruction used to compare 8-bit data or byte from the memory
location pointed by DI register with data from the memory location pointed
by SI register. For comparison data of memory location pointed by DI is
subtracted from data of memory location pointed by SI. The result is not
stored and data of operands remains unaffected. The status of conditional
flags is changed according to result of subtraction. The SI and DI are
automatically decremented or incremented by one to point to next elements
in two strings after execution of the instruction depending on the value
of direction flag (DF). SI and DI are incremented when DF = 0 and these
registers are decremented when DF = 1.
ii. All conditional flags (i.e. OF, SF, ZF, AF, PF and CF) are affected.
4. CMPSW i. It is a string instruction used to compare 16-bit data or word from the memory
location pointed by DI register with data from memory location pointed by SI
register. For comparison data of memory location pointed by DI is subtracted
from data of memory location pointed by SI. The result is not stored and
data of operands remains unaffected. The status of conditional flags is
changed according to result of subtraction. The SI and DI are automatically
decremented or incremented by two each to point to next elements in two
strings after execution of the instruction depending on the value of direction
flag (DF). SI and DI are incremented by 2 when DF = 0 and these registers
are decremented by 2 when DF = 1.
Note : i. The count register CX can be used to hold count number of elements of string. REPE or REPNE
instruction are used as a prefix instruction for CMPS instructions to handle the string. Alternately,
LOOP instruction can be used after CMPS instruction for repetition.
ii. The register DI is used as a pointer to extra segment (ES) and the register SI is a used as a pointer to
data segment (DS)
III. SCAS instructions

5. SCASB i. This instruction compares 8-bit data or byte stored in AL with data stored in
memory location from Extra segment (ES) pointed by DI register. DI regiter
stores offset of data in ES. For comparison the data of memory location
pointed by DI is subtracted from the accumulator. The result is not stored
and data of operands remains unaffected. The status of conditional flags is
changed according to result of subtraction. After execution of the instruction
the register DI is automatically decremented or incremented by one to point
to next element of the string in ES depending on the value of direction flag
(DF). DI is incremented by one when DF = 0 and decremented by one when
DF = 1.
6. SCASW i. This instruction compares 16-bit data or word stored in AX with data stored
in memory locations from Extra segment (ES) pointed by DI register. DI
register stores offset of data in ES. For comparison the data of memory
locations pointed by DI is subtracted from the accumulator. The result is not
stored and data of operands remains unaffected. The status of conditional
flags is changed according to result of subtraction. After execution of the
instruction the register DI is automatically decremented or incremented by
two to point to next element of the string in ES depending on the value of
direction flag (DF). DI is incremented by one when DF = 0 and decremented
by one when DF = 1.
Note : i. The count register CX can be used to hold count number of elements of string. REPE or REPNE
instruction are used as a prefix instruction for SCAS instructions to handle the string. Alternately,
LOOP instruction can be used after SCAS instruction for repetition.
ii. The register DI is used as a pointer to extra segment (ES).
IV. LODS instructions

7. LODSB i. Loads 8-bit data or a byte from the memory location of data segment (DS)
pointed by SI register to AL. SI is automatically decremented or incremented
by one to point to next element after execution of the instruction depending
on the value of direction flag (DF). SI is incremented when DF = 0 and
8. LODSW i. Loads 16-bit data or a word from the memory locations of data segment (DS)
pointed by SI register to AX. SI is automatically decremented or incremented
by two to point to next element after execution of the instruction depending
on the value of direction flag (DF). SI is incremented when DF = 0 and
Note : i. The count register CX can be used to hold count number of elements of string. REP instruction is used
as a prefix instruction for LODS instructions to handle the string. Alternately, LOOP instruction can be
used after LODS instruction for repetition.
ii. The register SI is used as a pointer to extra segment (DS).
V. STOS instructions
9. STOSB i. Stores 8-bit data or a byte from AL to the memory location of extra segment
(ES) pointed by DI register. DI is automatically decremented or incremented
by one to point to next element of the string after execution of the instruction
depending on the value of direction flag (DF). SI is incremented when
DF = 0 and decremented when DF = 1.
10. STOSW i. Stores 16-bit data or a word from AX to the memory locations of extra segment
(ES) pointed by DI register. DI is automatically decremented or incremented
by two to point to next element of the string after execution of the instruction
depending on the value of direction flag (DF). SI is incremented when
DF = 0 and decremented when DF = 1.
Note : i. The count register CX can be used to hold count number of elements of string. REP instruction is used
as a prefix instruction for STOS instructions to handle the string. Alternately, LOOP instruction can be
used after STOS instruction for repetition.
ii. The register DI is used as a pointer to extra segment (ES).
VI. Repeat instructions
11. REP i. This instruction is used as a prefix to a string instructions MOVS, LODS or
STOS for repetition of operation performed by the given string instruction.
It uses CX as counter and decrements the CX and repeats execution of string
instruction until CX becomes zero. CX is used to store the count number of
elements of the string.
ii. Only ZF is affected.
12. REPE/REPZ
i. REPE/REPZ is used as a prefix to a string instructions CMPS or SCAS for
repetition of operation performed by the given string instruction. It uses CX
as counter and decrements the CX and repeats execution of string instruction
till CX ≠ 0 and ZF = 1. Repetition stops when either CX = 0 or ZF = 0. CX
is used to store the count number of elements of the string.
13. REPNE/REPNZ i. REPNE/REPNZ is used as a prefix to a string instructions CMPS or SCAS for
repetition of operation performed by the given string instruction. It uses CX
as counter and decrements the CX and repeats execution of string instruction
till CX ≠ 0 and ZF = 0. Repetition stops when either CX = 0 or ZF = 1. CX
is used to store the count number of elements of the string.
9.11.6 Flag Manipulation Instructions

1. CLC i. Clear Carry Flag. This instruction resets the CF.
ii. Only CF is affected.
2. STC i. Set Carry Flag. This instruction sets the CF.
3. CMC i. Complement Carry Flag. This instruction complements the CF.
4. CLD i. Clear Direction Flag. This instruction resets the DF.
ii. Only DF is affected.
5. STD i. Set Direction Flag. This instruction sets the DF.
ii. Only DF is affected.
6. CLI i. Clear Interrupt Flag. This instruction resets the interrupt flag IF. It is used to
disable the interrupt INTR.
ii. Only IF is affected.
7. STI i. Set Interrupt Flag. This instruction sets the interrupt flag IF.
9.11.7 Processor Control Instructions

1. HLT
i. Halts the execution of the program. The processor enters in to half state and
comes out of it only under one of the following situations occurs:
(a) An interrupt signal on INTR pin
(b) An interrupt signal on NMI pin
(c) Reset signal is on RESET pin
2. NOP i. No Operation. It takes 3 clock cycles to execute this instruction. It is used to
introduce a delay before execution of next instruction.
3. ESC i. Escape. This instruction is used to pass instruction to a co-processor such as
8087 math co-processor which shares the address and data bus with the 8086.
Is is used to release buses for external peripheral device or co-processor.
Instruction for the co-processor is represented by a 6 bit code embedded in
the escape instruction. As the 8086 fetches instruction byte, the co-processor
also catches these bytes from data bus and puts them in its queue. The co-
processor treats all of the 8086 instructions as an NOP. When 8086 fetches
an ESC instruction, the coprocessor decodes the instruction and carries out
the action specified by the 6 bit code. In most of the case 8086 treats ESC
instruction as an NOP. With a 6-bit code, 26 number of external opcodes are
specified for the co-processor.
4. WAIT i. Process enters in to idle state and does no processing. It waits for following
to occur,
(a) Making of TEST pin low
(b) Occurring of signal on INTR pin
(c) Occurring of signal on NMI pin
If an interrupt occurs when processor is idle then processor again becomes
idle after execution the interrupt service subroutine because processor saves
address of WAIT instruction on top of stack when either of INTR or NMI
interrupts are acknowledged. This instruction is used to synchronize the
slow peripherals such as 8087 math co-processor with Intel 8086.
5. LOCK i. This instruction is used as prefix to an instruction. This instruction makes
signal on LOCK pin low till execution of the next instruction. When the
signal on LOCK pin low no other processor can take control of system bus
in a multiprocessor system.
9.12 Assembler Directives

An assembly language program has two parts called instructions and assembler directives. The assembler
directives are statements used start of program to guide assembler to perform a task. During assembly
process the instructions of the program are converted to machine code whereas assembler directives are not
converted to machine codes. The assembler directives are used for many purposes such as to define data, to
organize segments etc. Assembler directives are used to assign names to variables and constants used in the
program and during assembly process these names are replaced by corresponding variables and constants.
For examples the directives DB, DW, DD, DQ and DT are used to assign names to the variables and specify
their types. The directive EQU is used to give names to constants. Similarly Labels are used to assign name
to the addresses.
9.12.1 Assembler Directives of Intel 8086
1. ASSUME : This directive is used to assign name to segments. Names to segments can be assigned
individually or with single directive.
Ex. ASSUME CS : CODE, DS : DATA, SS : STACK, ES : EXTRA
2. DB (Define Byte) : This directive is used to define a byte-type variable. It reserve one or more bytes in
memory.
Examples
i VALUE DB 32 : Declare VALUE as a byte type variable and reserve one byte of memory space for it.
ii. PRICE DB 12, 9, 2 : Declare PRICE as an array of 3bytes and initialize it.
iii. NAME DB ‘ABCDEF’ : Declare NAME as an array of 6 bytes and initialize it with ASCII code for
letters.
Note : When value is enclosed within inverted comma the processor initialize the variable with ASCII code of
letters, numbers or symbols within inverted comma.
iv. TEMP DB 100 DUP(?) : Declare TEMP as an array of 100 bytes for storage in memory and leave
the 100 bytes uninitialized whose values are not known. Program instructions load values into these
locations. Here DUP stands for duplicate. 100 DUP (?) tells the processor to duplicate ‘?’ hundred
times.
3. DW (Define Word) : This directive is used to define a word-type variable. It reserve two or multiple of
two bytes of memory space at consecutive memory locations.
Examples
i. SUM DW 3212 : Declare SUM as word type variable with initial value of 3212 H and reserve two
bytes of memory space at consecutive memory locations for it.
ii. NUM DW ‘23’ : Declare NUM as an word type variable and initialize it with ASCII code of digits 2 &
3. Processor reserves two bytes of memory space. First byte for ASCII code of ‘2’ and second byte for
ASCII code of ‘3’.
iii. ARRAY DW 2354 , 56 , 8795 : Declare ARRAY as an array of words. Processor reserve two bytes for
each number. For value of four digits (e.g. 2354 H), first byte goes to first memory (23 H) and second
byte goes to second memory location (54H). For a two digit number (e.g 56 H) the processor reserves
two bytes with given byte (i.e.56 H) at first memory location and 00 H at second memory location. The
initial values stored in memory space will be 2354 H, 0056H, 8795H
iv. STORAGE DW 100 DUP (0) : Declare STORAGE as an array of 100 Words with all initialized with
0000H. Total 200 bytes of memory space is reserved for the array.
v. STORAGE DW 100 DUP(?) ; Declare STORAGE as an array of 100 Words with all no initial value.
Total 200 bytes of memory space is reserved for the array. 100 DUP (?) tells the processor to duplicate
‘?’ hundred times.
vi. STORAGE DW 5384, 6932, 5 DUP (3456), 7384 : Declare STORAGE as an array of 8 words and
reserve 16 bytes of consecutive memory locations. Here 5 DUP (3456) means the number 3456 is
repeated five times. Memory locations are initialized with 5384, 6932, 3456, 3456, 3456, 3456 and
7384.
4. DW (Define Word) : This directive is used to define a double word-type variable. It reserve four or
multiple of four bytes of memory space at consecutive memory locations.
Examples
NUM DD 32418631 : Declare NUM as double word type variable with initial value of 32418631 H
and reserve four bytes of memory space at consecutive memory locations for it.
Note: All other examples are similar to DB and DW.
5. DQ (Define Quadword) : This directive is used to define a quadword-type variable. Quadword type of
variable occupies 8 bytes of consecutive memory locations. Therefore, this directive reserves eight or
multiple of either bytes of memory space at consecutive memory locations.
Examples
NUM DQ 4352931893841254 : Declare NUM as quadword type variable with initial value of
4352931893841254 H and reserve eight bytes of memory space at consecutive memory locations for it.
Note: All other examples are similar to DB and DW.
6. DT (Define Tenbytes) : This directive is used to define a variable of ten bytes. Therefore, this directive
reserves ten or mulitple of ten bytes of memory space at consecutive memory locations.
7. END (End of Program): It is used at end of program.
8. ENDP (End Procedure) : It is used at end of a procedure or subroutine.
9. EQU (Equate): This directive is used to assign a name to some value or to a symbol. The assembler
replaces all these names with the value or symbol during assembling process.
Examples
i. NUM EQU 03H
ii. SET_CARRY EQU
STC
10. INCLUDE (Include Source Code from File) : This directive is used to insert a block of source code
from the named file into the current source module.
Example:
INCLUDE C:\myfile\math.lev; includes source code of math.lev from ‘myfile’ folder.
11. LABEL (label) : Labels are assembler directives used to assign name to memory addresses. It assigns
a name to the current content of the location counter. A LABEL directive can be used to make a far
jump. The label directive can be used to refer to the data segment along with the data type, byte or word
12. MACRO : MACRO is an assembler directive which assigns a name to a sequence of instructions. A
macro is similar to subroutine. A macro executes faster than a subroutine. A subroutine requires a CALL
and RET instructions whereas a macro does not. A macro can have arguments. ENDM directive is at
end of macro.
13. ORG (Originate) : This directive assign starting address for particular segment, block or code from
declared address in the ORG statement. For example, the statement ORG 2000H tells the assembler to
set the location counter to 2000H.
14. FAR PTR: This assembler directive is used to tell the assembler that the target address lies in the
another segment. So, the address indicated by label following the FAR PTR has two parts called segment
base address and offset. Label of FAR PTR has four bytes in which two bytes are used for offset and
remaining two bytes for base address of segment.
Examples
i. JMP FAR PTR label1
ii. JMP FAR PTR [SI] ; Jump to location whose address is pointed by SI.
iii. CALL FAR PTR label2
iv. CALL FAR PTR MULTI
15. NEAR PTR: This assembler directive is used to tell the assembler that the target address lies in the same
segment. So, the address indicated by label following the NEAR PTR has only two bytes indicating the
offset in current segment.
Exaples
i. JMP NEAR PTR label1
ii. CALL NEAR PTR label2
iii. CALL NEAR PTR DIVISION
16 PROC (Procedure): This directive is used to identity the start of a named subroutine or procedure. The
terms FAR and NEAR are used to specifies the type of the procedure.
Example :
i. MULTI PROC FAR
ii. DIVISION PROC NEAR
17. PTR (Pointer): This directive is used to declare the type of a label, variable or memory operand. The
directive PTR is prefixed by either BYTE or WORD.
Examples :
i. WORD PTR [DI] ; It indicates type of data pointed by DI is a word.
ii. BYTE PTR [SI] ; It indicates the type of data pointed by SI is a byte.
9.13 Microprocessor 8088

The Intel 8088 microprocessor is a 40 pin CHMOS device. It has 8 data lines and 20 address lines. The 8-bit
data bus AD0-AD7 multiplexed with address lines. It employs 8-bit I/O devices. It can address a 1 MB of
memory. It has 16-bit internal registers similar to 8086. It operates at 5 Vdc. Its has clock of 5-8 MHz. The
register set, instructions and addressing modes of 8088 are same as those of 8086. It uses 8087 math co-
processor. The queue length in 8088 is of 4 bytes only whereas that in 8086 is of 6 bites.

OBJECTIVE TYPE PRACTICE QUESTIONS
IES QUESTIONS
Q.1 Consider the following assembly language program for string comparison :
REPE CMPS STRG1, STRG2
JNE EXIT
JMP NEAR PTR SAME
The same result can be obtained by the following program that does not use REP prefix
NEXT : CMPS STRG1, STRG2
JNE EXIT
..................................................
JMP NEAR PTR SAME
The missing instruction (denoted by dashed line,.....) should be
(a) LOOP NEXT (b) JE NEXT
(c) JMP NEXT (d) JNZ NEXT
IES(E&T,97)
Q.2 If we use 3 bits in the instruction word to indicate an index register is to be used and if necessary, which one
is to be used, then the number of index registers to be used in the machine will be
(a) 3 (b) 6
(c) 7 (d) 8
IES(E&T,97)
Q.3 In a multi - processor configuration, two co-processors are connected to the host 8086 processor. The two
co-processor instruction sets
(a) must be the same (b) may overlap
(c) must be disjoint (d) must be the same as that of the host
IES(E&T,97)
Q.4 DB, DW and DD directives are used to place data in particular locations or to simply allocate space without
per-assigning anything to space. The DW and DD directions are used to generate
(a) offsets
(b) full address of variables
(c) full address of labels
(d) offsets of full address of labels and variables
IES(EE,97)
Q.5 The ESC instruction of 8086 may have two formats. In one of the formats, no memory operand is used.
Under this format, the number of external op-codes (for the co-processor) which can be specified is
(a) 64 (b) 128
(c) 256 (d) 512
IES(EE,97)
Q.6 In a 16-bit microprocessor, words are stored in two consecutive memory locations. The entire word can be
read in one operation provided the first
(a) word is even (b) word is odd
(c) memory location is odd (d) memory address is even
IES(EE,97)
Q.7 Each instruction in an assembly program has the following field :
1. Label field. 2. Mnemonic field
3. Operand field 4. Comment field.
The correct sequence/order of these fields is :
(a) 1, 2, 3, 4 (b) 1, 2, 4, 3
(c) 2, 1, 3, 4 (d) 2, 1, 4, 3
IES(E&T,98)
Q.8 Consider the following statements :
1. A total of about one million bytes can be directly addressed by the 8086 microprocessor.
2. The 8086 has thirteen 16-bit registers.
3. The 8086 has eight flag.
4. Compared to 8086, the 80286 provides a higher degree of memory protection.
Of these statements
(a) 2, 3 and 4 are correct (b) 1, 3 and 4 are correct
(c) 1, 2 and 4 are correct (d) 1, 2 and 3 are correct
IES(E&T,98)
Q.9 The interface chip used for data transmission between 8086 and a 16-bit ADC is
(a) 8259 (b) 8255
(c) 8253 (d) 8251
IES(E&T,98)
Q.10 In 8086 microprocessor, if the code segment register contains 1FAB and IP register contains 10A1, the
effective memory address is
(a) 20B51 (b) 304C
(c) FBC0 (d) FDB5
IES(E&T,99)
Q.11 To have the multiprocessing capabilities of the 8086 microprocessor, the pin connected to the ground is
(a) DEN (b) ALE
(c) INTR (d) MN / MX
IES(E&T,99)
Q.12 If the clock has a frequency of 5 MHz, then the execution time for ADD memory to register instruction
using based indexed relative addressing (result put in register) required is
(a) 4.8 µs (b) 4.9 µs
(c) 5 µs (d) 5.1 µs
IES(EE,99)
Q.13 The instruction queue length in INTEL 8086 and 8088 are
(a) 6 bytes in both processors (b) 4 bytes in both processors
(c) 4 bytes in 8086 and 6 bytes in 8088 (d) 6 bytes in 8086 and 4 bytes in 8088
IES(EE,99)
Q.14 The suitable programmable counter for 8086 microprocessors is
(a) 8253 chip (b) 8254 chip
(c) 8359 A chip (d) 8251 chip
IES(EE,99)
Q.15 Consider the following instructions executed in 8086.
PUSH AX ; AX has 20 Hex in it
PUSH BX ; BX has 34 Hex in it
POP AX ;
ADD AX , BX ;
POP G
The value stored in G would be
(a) 20 Hex (b) 34 Hex
(c) 54 Hex (d) 68 Hex
IES(E&T,00)
Q.16 In the case of a 16-bit processor, a single instruction is enough to process a function. For processing the
same function,
(a) more than one 8-bit processors will be required to work in sequence
(b) more than one 8-bit processors will be required to work in parallel
(c) a long sequence of instructions will be required for a 8-bit processor
(d) the same instruction will do for a 8-bit processor also
IES(EE,00)
Q.17 Consider the following functions of an 8086 microprocessor :
1. Temporary storage of data.
2. Storing offset of a memory address in DS.
3. String instructions.
4. JNLE instructions.
5. JCXZ instructions.
Which of these functions require the use of the SI and DI registers ?
(a) 1, 2 and 3 (b) 1, 2 and 4
(c) 2, 3 and 5 (d) 3, 4 and 5
IES(EE,00)
Q.18 If (BX) = 0158
(DI) = 10A5
Displacement = 1B57
(DS) = 2100
(where DS is used as a segment register) then the effective and physical addresses produced using
“RELATIVE BASE INDEXED INDIRECT ADDRESSING” will be respectively
(a) 2D54 and 23D54 (b) 23D54 and 2D54
(c) 1B57 and 1CAF (d) 1CAF and 1B57
IES(EE,00)
Q.19 The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of
wait state clock cycles denoted by Tw. The wait states are always inserted between
(a) T1 and T2 (b) T3 and T4
(c) T2 and T3 (d) T4 and T1
IES(EE,01)
Q.20 Effective address is calculated by adding or subtracting displacement value to
(a) immediate address (b) relative address
(c) absolute address (d) base address
IES(E&T,01)
Q.21 The 8086 arithmetic instructions work on
1. signed and unsigned numbers
2. ASCII data
3. unpacked BCD data
Select the correct answer using the codes given below:
Codes:
(a) 1 and 2 (b) 2 and 3
(c) 1 and 3 (d) 1,2 and 3
IES(E&T,01)
Q.22 In the 8086 instruction ADD DX, [BX] [DI], the addressing mode of source operand is
(a) Register (b) Register Indirect
(c) Based Indexed (d) Direct
IES(E&T,02)
Q.23 Consider the assembler directives:
ORG 8000
T : DW OFAOFH
Which one of the following is correct?
(a) The contents of the locations 8000 and 8001 get erased
(b) The contents of the locations 8000 and 8001 remain unchanged
(c) The least significant byte OF will be stored at location 8000 and the most significant byte FA will be
stored at location 8001
(d) The least significant byte OF will be stored at location 8001 and the most significant byte FA will be
stored at location 8000
IES(E&T,03)
Q.24 Match List-I (8085 Register) with List-II (8086 Register) and select the correct answer using the codes
given below the List:
List-I List-II
(8085 Register) (8086 Register)
A. A 1. CH
B. H 2. AL
C. L 3. BL
D. B 4. BH
Codes:
A B C D
(a) 4 2 3 1
(b) 2 4 1 3
(c) 4 2 1 3
(d) 2 4 3 1
IES(E&T,03)
Q.25 When an 8086 executes an INT type instruction, it :
(a) Resets both IF and TF flags (b) Resets all flags
(c) Sets both IF and TF (d) Resets the CF and TF
IES(EE,05)
Q.26 Match List-I with List-II and select the correct answer using the code given below the lists :
List-I List-II
A. Modified during fetch phase 1. DI
B. Holds subscripts of arrays 2. DS
C. Needed by the DEBUG program 3. IP
D. Calculates addresses of data in 4. TF
data-segment
Codes :
A B C D
(a) 2 4 1 3
(b) 3 1 4 2
(c) 2 1 4 3
(d) 3 4 1 2
IES(EE,05)
Q.27 The interrupt vector table IVT of 8086 contains
(a) The contents of CS and IP of the main program address at which the interrupt has occurred
(b) The contents of CS and IP of the main program address to which the control has to come back after the
service routine
(c) The starting CS and IP values of the interrupt service routine
(d) The starting address of the IVT
IES(EE,05)
Q.28 Consider the following statements :
2. 8086 has thirteen 16-bit registers.
3. 8086 has eight flags.
Which of the statements given above are correct ?
(a) 2,3 and 4 (b) 1,3 and 4
(c) 1,2 and 4 (d) 1,2 and 3
IES(EE,05)
Q. 29 Match List-I (2 Pins of 8086) with List-II (Status) and select the correct answer using the code given below
the lists :
List-I List-II
(2 Pins of 8086) (Status)
BHE A0 What is read/written ?
A. 0 0 1.one byte from/to odd address
B. 0 1 2.one byte from/to even address
C. 1 0 3. one 16-bit word
D. 1 1 4. NOP
Code :
A B C D
(a) 4 2 1 3
(b) 3 1 2 4
(c) 4 1 2 3
(d) 3 2 1 4
IES(E&T,05)
Q.30 Which of the following instruction of an 8086 microprocessor uses the contents of a CX register as a
counter?
1. LOCK
2. LOOP
3. ROTATE
Select the correct answer using the code give below:
(a) Only 1 and 2 (b) Only 1 and 3
(c) Only 2 and 3 (d) 1,2 and 3
IES(E&T,06)
Q.31 Which one of the following pairs of 8086 microprocessor’s interrupt is not correctly matched?
(a) INT 0 : Divide by zero
(b) INT 1 : Single step
(c) INT 2 : Break point
(d) INT 4 : Overflow
IES(E&T,06)
Q.32 Which one of the following is used as the interface chip for data transmission between 8086 and a 16-bit ADC ?
(a) 8259 (b) 8255
(c) 8253 (d) 8251
IES (E&T,09)
Q.33 What is the address space of 8086 CPU ?
(a) One Megabyte (b) 256 Kilobyte
(c) 1 K Megabytes (d) 64 Kilobytes
IES (E&T, 09)
Q.34 The interface chip used for data transmission between 8086 and a 16 bit ADC is :
(a) 8251 (b) 8253
(c) 8255 (d) 8259
IES(E&T, 10)
Q.35 Which one of the following control bits of 8086 flag register is used to put the 8086 in single step mode ?
(a) DF (b) IF
(c) TF (d) ZF
IES(E&T,11)
Q.36 As compared to 16 bit microprocessor, 8 bit microprocessors are limited in :
1. Speed
2. Directly addressable memory
3. Data handling capability
(a) 1 and 2 only (b) 2 and 3 only
(c) 1 and 3 only (d) 1, 2 and 3
IES(E&T,11)
Q.37 For 8086 microprocessor, the jump distance in bytes for short jump range is
(a) Forward 255 and Backward 256 (b) Forward 127 and Backward 128
(c) Forward 31 and Backward 32 (d) Forward 15 and Backward 16
IES(E&T,12)
Q.38 The action performed by the following instruction of 8086 :
MOV [1234h], AX
(a) Move contents of memory location 1234h to register AX
(b) Move the contents of register AX to memory offset 1234h
(c) Add contents at 1234h to register AX
(d) Add contents of 1234h and AX and store the result in 1234h
IES(E&T,12)
Q.39 Statement I: Segment Override Prefix (SOP) is used when a default offset register is not used with its
default base segment register, but with a different base register.
Statement II: The offset registers IP and SP can never be associated with any other segment registers apart
from their respective default segments.
(a) Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation
of Statement (I)
(b) Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation
of Statement (I)
(c) Statement (I) is true but Statement (II) is false
(d) Statement (I) is false but Statement (II) is true
IES(EE,14)
Q.40 Direction flag is used with
(a) String instructions (b) Stack instructions
(c) Arithmetic instructions (d) Branch instructions
IES(EE,15)
Q.41 Which one of the following statements is correct about 8086?
(a) It is 46 PM IC and uses 5V dc supply
(b) It uses 20 lines for data bus
(c) It multiplexes status signals with address bus
(d) It is manufactured using CMOS technology
IES(EE,15)
Q.42 What is the activity of the microprocessor 8086/8088 when the signals SSo , DT / R and IO / M are 1, 0 and
1 respectively in minimum mode?
(a) Read memory (b) Read I/O port
(c) Code Access (d) Write I/O port
IES(E&T,15)
Q.43 Consider the symbol shown below.
What function does the above symbol represent in a program flow chart?
(a) A process (b) Decision making
(c) A subroutine (d) Continuation
IES(EE,16)
Q.44 Consider the following instructions:
1. LOCK 2. STD
3. HLT 4. CLI
Which of the above are machine control instructions?
(a) 1 and 4 (b) 1 and 3
(c) 2 and 3 (d) 2 and 4
IES(EE,16)
Q.45 What is the assembler directive statement used to reserve an array of 100 words in memory and initialize
all 100 words with 0000 and give it a name STORAGE?
(a) STORAGE DW 100 (b) STORAGE DW 100 DUP (0)
(c) STORAGE DW 100 DUP (?) (d) STORAGE DB 100
IES(EE,16)
Q.46 Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
(a) 1, 2 and 3 (b) 1 and 2 only
(c) 1 and 3 only (d) 2 and 3 only
IES(EE,16)
Q.47 Consider the following statements:
1. Semiconductor memories are organized as linear array of memory locations.
2. To address a memory location out of N memory locations, at least log N bits of address are required.
3. 8086 can address 1048576 addresses.
4. Memory for an 8086 is set up as two banks to make it possible to read or write a word with one machine
cycle.
Which of the above statements are correct?
(a) 1, 2 and 3 only (b) 1, 2 and 4 only
(c) 3 and 4 only (d) 1, 2, 3 and 4
IES(EE,16)
Q.48 Which addressing mode helps to access table data in memory efficiently?
(a) Indirect mode (b) Immediate mode
(c) Auto-decrement or Auto-increment mode (d) Index mode
IES(E&T,16)
Q.49 Statement (I): The direction flag D in 8086 selects increment or decrement mode for DI and/or SI registers.
Statement (II) : If D = 0, the registers are automatically decremented.
(a) Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation
of Statement (I).
(b) Both Statement (I) and Statement (II) are individually true but Statement (II) is not the correct explanation
of Statement (I).
(c) Statement (I) is true but Statement (II) is false.
(d) Statement (I) is false but Statement (II) is true.
IES(E&T,16)
Q.50 If the operating frequency of an 8086 microprocessor is 10 MHz and, if, for the given instruction, the
machine cycle consists of 4 T-states, what will be the time taken by the machine cycle to complete the
execution of that same instruction when three wait states are inserted?
(a) 0.4 µs (b) 0.7 µs
(c) 7 µs (d) 70 µs
IES(E&T, 17)
Q.51 Consider the following loop
MOV CX, 8000h
L1: DEC CX
JNZ L1
The processor is running at 14.7456/3 MHz and DEC CX requires 2 clock cycles and JNZ requires 16 clock
cycles. The total time taken is nearly
(a) 0.01s (b) 0.12s
(c) 3.66s (d) 4.19s
IES(E&T, 17)
ANSWERS AND EXPLANATIONS

Q.1 Ans.(a)
Program 1:
REPE CMPS STRG1, STRG2
JNE EXIT
JMP NEAR PTR SAME
Program 2 :
NEXT : CMPS STRG1, STRG2
JNE EXIT
..................................................
JMP NEAR PTR SAME
The same result can be obtained by the program 1 and program 2 if the missing instruction in program 2 is
LOOP NEXT.
Q.2 Ans.(d)
If 3 bits of the instruction code are used to indicate an index register then 23 (=8) number of index registers
can be used in the machine.
Q.3 Ans.(d)
In a multi - processor configuration, two co-processors are connected to the host 8086 rocessor. The two
co-processor instruction sets must be the same as that of the host.
Q.4 Ans.(d)
DB, DW and DD directives are used to place data in particular locations or to simply allocate space without
pre-assigning anything to space. The DW and DD directions are used to generate offsets of full address of
labels and variables.
Q.5 Ans.(a)
ESC instruction is used to pass instruction to a co-processor such as 8087 math co-processor which shares
the address and data bus with the 8086. Is is used to release buses for external peripheral device or co-
processor. Instruction for the co-processor is represented by a 6 bit code embedded in the escape instruction.
As the 8086 fetches instruction byte, the co-processor also catches these 6- bits from data bus and puts them
in its queue. The co-processor treats all of the 8086 instructions as an NOP. When 8086 fetches an ESC
instruction, the co-processor decodes the instruction and carries out the action specified by the 6 bit code.
In most of the case 8086 treats ESC instruction as an NOP. With a 6-bit code, 26 (= 64 )number of external
opcodes are specified for the co-processor.
Q.6 Ans.(d)
In a 16-bit microprocessor, words are stored in two consecutive memory locations. The entire word can be
read in one operation provided the first word is at even address.
Note : If the first byte of the data is stored at an ODD address then 8086 needs two operation to read the 16 bit
data.
Q.7 Ans.(a)
Each instruction in an assembly program has the following field :
i. Label field.
ii. Mnemonic field
iii. Operand field
iv. Comment field.
Q.8 Ans.(c)
Facts about 8086 microprocessor,
3. 8086 has nine flags. Out of 9 flags, 3 flags are used as control flags and remaining 6 are used as
condition flags.
Q.9 Ans.(b)
The interface chip used for data transmission between 8086 and a 16-bit ADC is 8255.
Q.10 Ans.(a)
The effective memory address (EMA) is computed by shifting contents of code segment register by four
bits to left & inserting four 0s in LSBs and then adding the contents of IP register to it.
EMA = 1FAB0 + 10A1 = 20B51
Q.11 Ans.(d)
To have the multiprocessing capabilities of the 8086 microprocessor, the pin connected to the ground is
MN / MX .
Q.12 Ans.(c)
The execution time of an instruction is time required for memory accesses and time required for calculation
of effective address by BIU. ADD memory to register requires 9 or 13 clock cycles for fetching the code
and data from and memory and 12 clock pulses for calculation of effective address (EA). If the clock has
a frequency of 5 MHz (its period is 0.2 µs), then execution times for of the ADD memory to register using
based indexed relative addressing (result put in register) requires:
Case - I: For a data stored at even address
Not of clock cycles = 9 + 12 = 21 cycles
Total Time = 21 × 0.2 = 4.2 µs
Case - II: For a data stored at even address
Not of clock cycles = 13 + 12 = 25 cycles
Total Time = 25 × 0.2 = 5 µs
Q.13 Ans.(d)
The instruction queue length in INTEL 8086 and 8088 are 6 bytes in 8086 and 4 bytes in 8088.
Q.14 Ans.(a)
The suitable programmable counter for 8086 microprocessors is 8253 chip.
Q.15 Ans.(a)
Given data in AX is 20 H and data in BX is 30 H.
PUSH AX ; Saves the contents of AX on the top of the stack. Now top of the stack has 20H.
PUSH BX ; Further saves contents of BX on top of the stack. Now current top of the
stack has 30H.
POP AX ; Loads data from top of stack which is 30 H in AX. So, contents in AX =
30H. And now top of stack consists of data 20H.
ADD AX , BX ; Adds contents of BX to contents of AX and stores result in AX.
AX = 30H+30H = 60 H.
POP G ; Saves contents of top of stack which is now 20 H in register G.
So, value stored in G is 20 H.
Q.16 Ans.(c)
In the case of a 16-bit processor, a single instruction is enough to process a function. For processing the
same function, a long sequence of instructions will be required for a 8-bit processor. For example the
multiplication operation can be done with single instruction in 8086 but it requires a long sequence of
instructions in case of 8085 microprocessor.
Q.17 Ans.(a)
SI and DI registers are used for,
1. Temporary storage of data.
2. Storing offset of a memory address in DS.
3. String instructions.
Q.18 Ans.(a)
Effective address (EA) is an offset from starting address of the given segment. Here effective address is sum
of (BX) + (DI) + Displacement.
i.e. EA = 0158 + 10A5+ 1B57 = 2D54
The physical address is computed by shifting contents of DS by four bits to left and inserting 0s in four
LSBs and then adding effective address to it.
Physical Address = DS + EA = 21000 + 2D54 = 23D54
Q.19 Ans.(b)
The length of a bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of
wait state clock cycles denoted by Tw. The wait states are always inserted between T3 and T4
Q.20 Ans.(d)
Effective address is calculated by adding or subtracting displacement value to base address.
Q.21 Ans.(a)
The 8086 arithmetic instructions work on
1. signed and unsigned numbers
2. ASCII data
3. Packed BCD data
Q.22 Ans.(c)
In the 8086 instruction ADD DX, [BX] [DI], the addressing mode of source operand is Based Indexed.
Q.23 Ans.(c)
Consider the assembler directives:
ORG 8000
T : DW OFAOFH
The given assembler directive is used to store the least significant byte OF at location 8000 and the most
significant byte FA at location 8001.
Q.24 Ans.(d)
(8085 Register) (8086 Register)
A. A 1. AL
B. H 2. BH
C. L 3. BL
D. B 4. CH
Q.25 Ans.(c)
When an 8086 executes an INT type instruction, it resets both IF and TF flags.
Q.26 Ans.(b)
A. IP is always modified during fetch phase
B. DI holds subscripts of arrays
C. TF is used for single step control. It allows user to execute one instruction of a program at a time for
debugging.
D. DS is used to calculate the addresses
of data in data-segment
Q.27 Ans.(c)
The interrupt vector table IVT of 8086 contains the starting CS and IP values of the interrupt service
routine.
Q.28 Ans.(c)
3. 8086 has nine flags. Out of 9 flags, 3 flags are used as control flags and remaining 6 are used as
condition flags.
Q.29 Ans.(b)
Correct match is as given below,
(2 Pins of 8086) (Status)
BHE A0 What is read/written ?
A. 0 0 1. one 16-bit word
B. 0 1 2. one upper byte from/to odd address
C. 1 0 3. No operation
D. 1 1 4. one lower byte from/to even address
Q.30 Ans.(c)
Facts about given instructions,
1. LOCK : Prohibits control to any other co-processor. It does not use CX as counter.
2. LOOP : Used for looping operation. It uses CX as counter.
3. ROTATE : Used to rotate contents of a register or memory. It uses CX as counter.
Q.31 Ans.(c)
Interrupt Operation
i. INT 0 : Divide by zero
ii. INT 1 : Single step
iii. INT 2 : non maskable
iv. INT 3 : Break point
v. INT 4 : Overflow
Q.32 Ans. (b)
The interface chip used for data transmission between 8086 and a 16 bit ADC is 8255.
Q.33 Ans. (a)
The microprocessor 8086 has 20 address lines so its address space is 220 bytes or 1 MB. CPU.
Q.34 Ans. (b)
The interface chip used for data transmission between 8086 and a 16 bit ADC is 8255.
Q.35 Ans (c)
Trap flag of 8086 is used to put the 8086 in single step mode. If this flag is set, the processor enters the
single step execution mode by generating internal interrupts after the execution of each instruction.
Q.36 Ans (d)
As compared to 16 bit microprocessor, 8 bit microprocessors are limited in :
1. Speed
2. Directly addressable memory
3. Data handling capability
Q.37 Ans(b)
For 8086 microprocessor, the jump distance in bytes for short jump range is Forward 127 and Backward
128.
Q.38 Ans(b)
MOV [1234h], AX : Move the contents of register AX to memory offset 1234h
Q.39 Ans (b)
Statement I: Segment Override Prefix (SOP) is used when a default offset register is not used with its
default base segment register, but with a different base register. A segment override prefix allows any
segment register (DS, ES, SS, or CS) to be used as the segment when evaluating addresses in an instruction.
So, statement I is true.
Statement II: The offset registers IP and SP can never be associated with any other segment registers apart
from their respective default segments. The statement II is also true but it is not correct explanation of
statement I.
Q.40 Ans (a)
Direction flag is used with string instructions.
Q.41 Ans (c)
i. It is 40 IC and uses 5V dc supply
ii. It uses 20 lines for address bus and 16 lines for data bus.
iii. It multiplexes status signals with address bus (A16-A19)
iv. It is manufactured using HMOS technology
Q.42 Ans (b)
Here, IO / M is 1 that means it must be operation related to I/O device. DT / R = 0 indicates that
microprocessor receives the data. So, the processor is performing I/O read operation.
Q.43 Ans(a)
The above symbol is used in flow chart to represent a predefined process.

Q.44 Ans(b)
LOCK and HLT are machine control instructions. STD and CLI are bit manipulation instructions.
Q.45 Ans (c)
STORAGE DW 100 DUP (0); This assembler directive declare STORAGE as and array or array of 100
words. It reserves space of 100 words in memory and initialize all words with value 0000 H.
Q.46 Ans(b)
Facts about given statements,
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are short type jumps.
Q.47 Ans(a)
Correct statements are,
1. Semiconductor memories are organized as linear array of memory locations.
2. To address a memory location out of N memory locations, at least log2 N bits of address are required.
3. The 8086 microprocessor has 20 address lines so it can address 220 or 1048576 addresses.
Q.48 Ans(d)
The indexed addressing modes are key to efficiently addressing tables and other data structures
Q.49 Ans(c)
Statement (I): The direction flag D in 8086 selects increment or decrement mode for DI and/or SI registers.
The statement (I) is true.
Statement (II) : If D = 0, the registers are automatically incremented. The statement (II) is false.
Q.50 Ans.(b
Duration of one T-State,
1 1
T = = = 0.1 µs
Clock Frequency 10MHz
Total time required for execution of instruction when 3 wait states are introduced will we equal to 7 T states.
∴ Total time required = 4T+3T = 7T = 7 × 0.1 µs = 0.7 µs
Q.51 Ans.(b)
MOV CX, 8000h ; Moves 8000h in register CX
L1: DEC CX ; Decrement CX by one
JNZ L1 ; Jumps execution to L1 until zero flag is set.
The zero flags sets here only when contents of CX become zero. The program execution enters into the
loop and comes out of loop only when contents of CX become zero. The contents of CX are decremented
by one every time when DEC CX is executed. The DEC CX and JNZ L1 are executed 8000 h times before
execution comes out of loop.
The decimal equivalent of 8000 h is 32768. Thus the instructions DEC CX and JNZ L1 are executed 32768
times.
Total time required for execution of DEC CX and JNZ L1 once is 18 cycles.
The approximate time required for execution of the program will be,
Total time = 18 × 32768 clocks
14.7456 3
Time period of one clock cycle = = µs
3MHz 14.7456
3
∴ Total time = × 18 × 32768 µs = 0.12 s
14.7456


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9 Microprocessor 8086

 Statistical Analysis of Chapter 9

Fig. 9.1 Pin Diagram of 8086

9.3 Pin and Signals of 8086

9.4 Operating Modes of 8086

Table.9.1 Status signals and operation

9.5 Architecture and Functional Units of Intel 8086

9.6 Registers of Intel 8086

Fig. 9.2 Block Diagram of Intel 8086 Microprocessor

9.3 Register Organization of Intel 8086

Over flow flag Carry flag

9.7 Interrupts of 8086

9.8 Bus Cycle of 8086

One Bus Cycle

AD0-AD15 Address Data

Data reading and writing operations with the Memory:

9.9 Configurations of 8086 System for Minimum and Maximum Modes

Crystal Oscillator vCC

8086 ALE STB

Fig. 9.8 Configuration of a 8086 system in the minimum mode .

9.10 Addressing Modes of Intel 8086

Fig. 9.9 Configuration of a 8086 system in the maximum mode .

9.11 Instruction set and Programming of Intel 8086

Terms used in instructions and their meanings :

1. MOV des, src i. Copies the data from source to destination.

ii. No flag is affected.

ii. Flags SF, ZF, AF, PF and CF are affected.

9.11.3 Logical Instructions

9.11.4 Branch Instructions

III. Return Instructions

IV. Interrupt Instructions

2. INTO i. It is a software interrupt used to indicate condition of overflow after an

3. LOOPNZ label i. Decrement CX register and jump to specified label until

9.11.5 String Manipulation Instructions

II. CMPS instructions

III. SCAS instructions

IV. LODS instructions

9.11.6 Flag Manipulation Instructions

9.11.7 Processor Control Instructions

9.12 Assembler Directives

9.13 Microprocessor 8088

OBJECTIVE TYPE PRACTICE QUESTIONS

ANSWERS AND EXPLANATIONS

The above symbol is used in flow chart to represent a predefined process.

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Statistical Analysis of Chapter 9