The ARM Architecture
T
TM
1L
Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
When used in relation to the ARM:
Most ARMs implement two instruction sets
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode
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Processor Modes
The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor : entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access violations
Undef : used to handle undefined instructions
System : privileged mode using the same registers as user mode
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The ARM Register Set
Current Visible Registers
Abort
Mode
Undef
SVC
Mode
IRQ
FIQ
User
Mode
Mode
Mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
spsr
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Banked
Banked
out
Registers
Registers
User
FIQ
IRQ
SVC
Undef
Abort
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
r13 (sp)
r14 (lr)
spsr
spsr
spsr
spsr
spsr
TM
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Changing mode on an
Exception
There are total 37
registers in the
register file,of those,
20 registers are
hidden from a program
at user mode. These
registers are called
banked registers
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Interrupt Masks
Interrupt masks are used to stop specific interrupt requests from
interrupting the processor.
There are two interrupt request levels available on the ARM
processor coreinterrupt request (IRQ) and fast interrupt request
(FIQ).
The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which
control the masking of IRQ and FIQ, respectively.
The I bit masks IRQ when set to binary 1, and similarly the F bit
masks FIQ when set to binary 1.
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Processor Modes
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Condition Flags
Condition flags are updated by comparisons and the result of ALU operations
that specify the S instruction suffix.
For example, if a SUBS subtract instruction results in a register value of zero,
then the Z flag in the cpsr is set. This particular subtract instruction specifically
updates the cpsr.
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PIPELINE
A pipeline is the mechanism a RISC processor uses to execute instructions.
Using a pipeline processor speeds up execution by fetching the next instruction
while other instructions are being decoded and executed.
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PIPELINE
In the first cycle the core fetches the ADD instruction from memory.
In the second cycle the core fetches the SUB instruction and decodes the
ADD instruction.
In the third cycle, both the SUB and ADD instructions are moved along
the pipeline.
The ADD instruction is executed, the SUB instruction is decoded, and
the CMP instruction is fetched. This procedure is called filling the
pipeline.
The pipeline allows the core to execute an instruction every cycle.
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PIPELINE EXECUTION
In the execute stage, the pc always points to the address of the
instruction plus 8 bytes.
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EXCEPTIONS/INTERRUPTS
Reset vector is the location of the first instruction executed by the processor
when power is applied.
Undefined instruction vector is used when the processor cannot decode an
instruction.
Software interrupt vector is called when you execute a SWI instruction
Prefetch abort vector occurs when the processor attempts to fetch an
instruction from an address without the correct access permissions. The actual
abort occurs in the decode stage.
Data abort vector is similar to a prefetch abort but is raised when an instruction
attempts to access data memory without the correct access permissions.
Interrupt request vector is used by external hardware to interrupt the normal
execution flow of the processor.
Fast interrupt request vector is similar to the interrupt request but is reserved
for hardware requiring faster response times.
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THE VECTOR TABLE
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Core Extensions
The hardware extensions are standard components placed next to the ARM core.
They improve performance, manage resources, and provide extra functionality and
are designed to provide flexibility in handling particular applications.
There are three hardware extensions ARM wraps around the core:
Cache and tightly coupled memory (TCM)
Memory management
Coprocessor interface.
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CACHE & TCM
The cache is a block of fast memory placed between main memory and the
core
ARM has two forms of cache. The first is found attached to the Von
Neumannstyle cores. It combines both data and instruction into a single
unified cache, as shown in figure
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CACHE & TCM
TCM is fast SRAM located close to the core
A simplified Harvard architecture with TCMs.
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MEMORY MANAGEMENT
ARM cores have three different types of memory management hardware
No extensions providing no protection
Memory protection unit (MPU) providing limited protection
Memory management unit (MMU) providing full protection
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COPROCESSORS
Coprocessors can be attached to the ARM processor. A
coprocessor extends the processing features of a core by
extending the instruction set or by providing
configuration registers.
More than one coprocessor can be added to the ARM
core via the coprocessor interface.
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THE ARM INSTRUCTION
SET
T
TM
21L
DATA PROCESSING
INSTRUCTIONS
The data processing instructions manipulate data within registers.
They are
Move instructions
Arithmetic instructions
Logical instructions
Comparison instructions
Multiplyinstructions
Most data processing instructions can process one of their operands using
the barrel shifter.
If you use the S suffix on a data processing instruction, then it updates
the flags in the cpsr
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Move Instructions
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Move Instructions
Barrel Shifter
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Move Instructions
Barrel shifter operations
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Move Instructions
Logical shift left by one.
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Example of a MOVS instruction shifts register r1 left by one bit
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Arithmetic Instructions
The arithmetic instructions implement addition and subtraction of
32-bit signed and unsigned values.
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Arithmetic Instructions
Example 1
Example 2
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Arithmetic Instructions
Example 3
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Using the Barrel Shifter with Arithmetic Instructions
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Logical Instructions
Logical instructions perform bitwise logical operations on
the two source registers
Example 1
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Logical Instructions
Example 2
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Comparison Instructions
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Comparison Instructions
Example
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Multiply Instructions
The multiply instructions multiply the contents of a pair of registers
and, depending upon the instruction, accumulate the results in with
another register. The long multiplies accumulate onto a pair of
registers representing a 64-bit value. The final result is placed in a
destination register or a pair of registers
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Multiply Instructions
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Multiply Instructions
Example 1
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Multiply Instructions
Example 2
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Branch Instructions
Example 1
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Example 2
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Load-Store Instructions
Load-store instructions transfer data between memory and
processor registers. There are three types of load-store instructions:
single-register transfer
multiple-register transfer,
swap.
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Load-Store Instructions
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Load-Store Instructions
Example 1
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Single-Register Load-Store
Addressing Modes
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Single-Register Load-Store
Addressing Modes
Example 1
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Multiple-Register Transfer
Load-store multiple instructions can transfer multiple registers between memory and
the processor in a single instruction. The transfer occurs from a base address register
Rn pointing into memory. Multiple-register transfer instructions are more efficient
from single-register transfers for moving blocks of data around memory
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Multiple-Register Transfer
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Multiple-Register Transfer
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Multiple-Register Transfer
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Multiple-Register Transfer
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Stack Operations
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Stack Operations
When you use a full stack (F), the stack pointer sp points to an address that is
the last used or full location (i.e., sp points to the last item on the stack).
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Stack Operations
If you use an empty stack (E) the sp points to
an address that is the first unused or empty
location
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Swap Instruction
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Swap Instruction
Example 1
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Software Interrupt Instruction
Example 1
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Program Status Register
Instructions
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Program Status Register
Instructions
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Coprocessor Instructions
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Count Leading Zeros Instruction
The count leading zeros instruction counts the number of zeros between
the most significant bit and the first bit set to 1.
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ARM Processor Exceptions and
Modes
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Exception Priorities
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Interrupts
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IRQ & FIQ Exceptions
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Interrupt Handling Schemes
A nonnested interrupt handler handles and services individual interrupts
sequentially. It is the simplest interrupt handler.
A nested interrupt handler handles multiple interrupts without a priority
assignment.
A reentrant interrupt handler handles multiple interrupts that can be prioritized.
A prioritized simple interrupt handler handles prioritized interrupts.
A prioritized standard interrupt handler handles higher-priority interrupts in a
shortertime than lower-priority interrupts.
A prioritized direct interrupt handler handles higher-priority interrupts in a
shorter time and goes directly to a specific service routine.
A prioritized grouped interrupt handler is a mechanism for handling interrupts
that are grouped into different priority levels.
A VIC based interrupt service routine shows how the vector interrupt
controller (VIC) changes the design of an interrupt service routine.
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Non-nested Interrupt Handler
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Nested Interrupt Handler
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Reentrant Interrupt Handler
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Prioritized Simple Interrupt
Handler
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Prioritized Standard Interrupt
Handler
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Prioritized Direct Interrupt
Handler
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Prioritized Grouped Interrupt
Handler
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