UNIT – 4

ARM ARCHITECTURE

-- Ashish Thakur
SYLLABUS :

 RISC Vs CISC systems

 ARM Philosophy , ARM7 TDMI Core Architecture

 Functional Diagram, Programmer’s Model

 ARM State Register Set.

 THUMB state register set, Current Program Status Register

 ARM 7 TDMI Operating modes ,mode bits, Exceptions

 Interrupt Vector Table , Interrupt Processing.

UNIT -5 ARM INSTRUCTION SET
SYLLABUS :

 ARM Assembly Language ,

 Instruction Syntax ,ARM Instruction Set

 Data processing, Branch, Load/Store Instructions.

 Miscellaneous Instructions.
4.1 ARM BASICS: RISC VS CISC
 32 bit Processor.
 ARM – Advanced RISC Machine
 RISC– Reduced instruction set computers
 CISC– Complexed instruction set computers
CISC RISC

1. Intel x86 uses CISC Arch. 1. ARM uses RISC Arch.

2. Complex Instruction. 2. Simple Instruction.
3. Complexity will be on Hardware. 3. Complexity will be on
compiler.
 CISC RISC

4. Variable length Instructions. 4. Fixed length Instructions.

5. It has multiple cycles to 5. It has a single cycle to execute

execute.

6. It is flexible. i.e, it is smooth 6. It is Rigid i.e, it is performance

oriented processor. oriented processor..

7. No pipelining mechanism is 7. Pipelining mechanism is

present. present.

8. Speed is Less. 8. High speed.

4.2 ARM DESIGN PHILOSOPHY :

There are a number of physical features that have driven the ARM
processor design.

1) Battery concern
Portable embedded systems require some form of battery power. The ARM
processor has been specifically designed to be small to reduce power
consumption and extend battery operation—essential for applications
such as mobile phones and personal digital assistants (PDAs).

2) Memory Concern
High code density is another major requirement since embedded systems
have limited memory due to cost or physical size restrictions. High code
density is useful for applications that have limited on-board memory,
such as mobile phones and mass storage devices.
3) Cost concern
Embedded systems are price sensitive and use slow and low-cost
memory devices. For high-volume applications like digital cameras,
every cent has to be accounted for in the design. The ability to use
low-cost memory devices produces substantial savings.

4) Area Concern
Another important requirement is to reduce the area of the die taken
up by the embedded processor. For a single-chip solution, the
smaller the area used by the embedded processor, the more
available space for specialized peripherals. This in turn reduces the
cost of the design and manufacturing since fewer discrete chips are
required for the end product.
5) Time to Market
ARM has hardware debug technology within the processor so that
software engineers can view what is happening while the processor
is executing code. With greater visibility, software engineers can
resolve issues faster, which has a direct effect on the Time to market
and reduces overall development costs.

6) System Performance
The ARM core is not a pure RISC architecture because of the
constraints of its primary application (the embedded system). In
today’s ARM systems the key is not raw processor speed but total
effective system performance and power consumption.
4.2.1 Instruction Set for Embedded Systems :

The ARM instruction set differs from the pure RISC definition in
several ways that make the ARM instruction set suitable for embedded
applications:

Variable cycle execution for certain instructions :

•Not every ARM instruction executes in a single cycle. For

example, load-store-multiple instructions vary in the number of
execution cycles.
•The transfer can occur on sequential memory addresses, which
increases performance.
•Code density is also improved.
 Inline barrel shifter leading to more complex instructions :

• It is a hardware component that preprocesses one of the input

registers before it is used by an instruction.
• This expands the capability of many instructions to improve core
performance and code density.

 Thumb 16-bit instruction set

• ARM enhanced the processor core by adding a second 16-bit

instruction set called Thumb that permits the ARM core to
execute either 16- or 32-bit instructions.
 Conditional execution

• An instruction is only executed when a specific condition

has been satisfied. This feature improves performance and
code density by reducing branch
instructions.

 Enhanced instructions

• The enhanced digital signal processor (DSP) instructions

were added to the standard ARM instruction set to support
fast 16×16-bit multiplier operations.
• These instructions allow a faster-performing ARM
processor
4.3 ARM FEATURES:

 32 Bit Microcontroller/Embedded processor i.e, 32 bit ALU.

 32 Bit Data buses & Address buses.

 32 bit Add. Buses i.e, ARM can access 4 GB memory.

 ARM follows 3 stage pipeline

 Fetch
 Decode

 Execute

 ARM follows Von Neumann architecture in which data and

instructions (code) share the same bus.
 In contrast, Harvard implementations of the ARM use two
different buses.
4.3 ARM FEATURES CONT’D…
 Most ARM processors implement two instruction sets

 32-bit ARM Instruction Set

 16-bit Thumb Instruction Set

 ARM has 37 registers all of which are 32-bits long.

 1 dedicated program counter (PC)

 1 dedicated current program status register

 5 dedicated saved program status registers

 30 general purpose registers

 When used in relation to the ARM:

 Byte means 8 bits

 Half word means 16 bits (two bytes)

 Word means 32 bits (four bytes)

4.3 ARM FEATURES CONT’D…
 The ARM has seven basic operating modes:

 User : unprivileged mode under which most tasks run

 FIQ : entered when a high priority (fast) interrupt is raised

 IRQ : entered when a low priority (normal) interrupt is
raised
 Supervisor : entered on reset and when a Software Interrupt
instruction is executed
 Abort : used to handle memory access violations

 Undef : used to handle undefined instructions

 System : privileged mode using the same registers as user

mode
4.4 ARM CORE DATA FLOW MODEL :
 4.4 ARM CORE DATA FLOW MODEL CONT’D….
 Arrows represent the flow of data, lines represent the buses, and
the boxes represent either an operation unit or a storage area.
 Data enters the processor core through the Data bus. It can be an
instruction or data.
 The instruction decoder translates instructions before they are
executed.
 The ARM processor uses a load-store architecture. This means it
has two instruction types for transferring data in and out of the
processor:
 Load instructions copy data from memory to registers in the core.
 Store instructions copy data from registers to memory.
 4.4 ARM CORE DATA FLOW MODEL CONT’D….

 Data processing is carried out solely in registers.

 Register file : Data items are placed in this.

 It is a storage bank made up of 32-bit registers.

 Sign extend : It is a hardware, converts signed 8-bit and 16-bit no. to 32-bit
values, Since ARM core is a 32-bit processor, most instructions treat
registers as holding signed/unsigned 32-bit values.
 ARM instructions typically have two source registers, Rn and Rm, and a
destination register, Rd. Source operands are read from the register file using
the internal buses A and B.
 ALU & MAC : Arithmetic logic unit or Multiply-accumulate unit takes the
register values Rn and Rm from the A and B buses and computes a result and
store it to Rd register.
4.4 ARM CORE DATA FLOW MODEL CONT’D….

 Load and store instructions use the ALU to generate an address

to be held in the address register and broadcast on the Address
bus.
 Register Rm can be preprocessed in the barrel shifter before it
enters the ALU. Together barrel shifter and ALU can calculate a
wide range of expressions and addresses.
 Incrementer : It updates the address register before the core
reads/writes the next register value from/to the next sequential
memory location. (For load and store instructions).
 The processor continues executing instructions until an
exception/interrupt changes the normal execution flow.
4.5 REGISTERS:
 Fig. shows active registers available in user
mode -- a protected mode normally used when
executing applications.
 All the registers shown are 32 bits in size.
 There are up to 18 active registers:

 16 data registers and 2 processor status

registers.
 The data registers are visible to the programmer
as r0 to r15.
 The ARM processor has three registers assigned
to a particular task or special function:
 r13, r14, and r15.
4.5 REGISTERS CONT’D….
The shaded registers identify the assigned special-purpose
registers:

 Stack Pointer (SP) – Stores the address of the top element of

stack.

 Link Register (LR) – Register used to save the PC when

entering a subroutine.

 Program Counter (PC) – The address of next instruction.

 Current Program Status Register (CPSR) – Stores the results

of most recent operation including Flags, Interrupts
(Enable/Disable) and Modes.
4.6 CURRENT PROGRAM STATUS REGISTER :

 The cpsr is a dedicated 32-bit register.

 The shaded parts are reserved for future expansion.

 The cpsr is divided into four fields, each 8 bits wide: flags,
status, extension and control.
4.6 CURRENT PROGRAM STATUS REGISTER
CONT’D…

 In current designs the Extension and Status fields are

reserved for future use.
 The Control field contains the processor mode, state, and
interrupt mask bits.
 The Flags field contains the condition flags.

 Some ARM processor cores have extra bits allocated. For

example J bit, which can be found in the flags field, is
only available on Jazelle-enabled processors, which
execute 8-bit instructions.
4.6 CURRENT PROGRAM STATUS REGISTER
CONT’D…

 N: Negative; the last ALU operation which changed the

flags produced a negative result.
 Z: Zero; the last ALU operation which changed the flags
produced a zero result (every bit of the 32-bit result was
zero).
 C: Carry; the last ALU operation which changed the
flags generated a carry-out, either as a result of an
arithmetic operation or from the shifter.
 V: Overflow; the last ALU operation which changed the
flags generated an overflow into the sign bit.