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Unit 3 - Week
1 : Pipelined Instruction Execution Principles

Course
outline
Assignment 1
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the portal assignment.

Week 0 : Course
Introduction
***** You are allowed to submit this assignment only once *****
Week 1 :
Pipelined
Instruction 1) Which all stages in a 5-stage RISC-MIPS instruction pipeline access the cache memory? 1 point
Execution
Principles
IF only
Lecture 01 - IF and ID
Instruction
Execution IF and MEM
Principles
MEM only
Lecture 02 -
Introduction to No, the answer is incorrect.
Instruction Score: 0
Pipeline
Accepted Answers:
Lecture 03 - IF and MEM
Introduction to
Superscalar 2) An instruction pipeline was designed with four stages. Individually each of the stage will 1 point
Pipelines take 2.8 ns, 3.2 ns, 1.9 ns and 3.5 ns, respectively for completion of its operation. The pipeline latch
Tutorial 1A - latency is 0.5 ns. What is the minimum cycle time of the pipeline?
Instruction
Pipeline & 2.4 ns
Performance
4.0 ns
Tutorial 1B -
Instruction 3.35 ns
Pipeline &
Performance
11.9 ns

Tutorial 1A - No, the answer is incorrect.

Minor Score: 0
Correction
Accepted Answers:
Quiz : 4.0 ns
Assignment 1 © 2014 NPTEL - Privacy & Terms - Honor Code - FAQs -
3) Which of the following can be a valid instruction for an Accumulator machine? (Hint: B is 1 point
A project of In association with
Solution - the address of a memory location and R is the name of a register)
Assignment 1

Load B
Week 2 : Cache
Funded by
Memory Design Push B

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Concepts Powered by
Load R, B

Week 3 : Basic Add R, B

Cache
Optimizations No, the answer is incorrect.
Score: 0
Week 4 : Accepted Answers:
Advanced Cache
Load B
Optimizations
4) If a 32-bit value (0xA1B2C3D4) is stored in memory addresses 200, 201, 202, and 203 in 1 point
Week 5 : DRAM little endian format, then the location 201 holds the value ____.
Technology

0x2B
Week 6 : Tiled
Chip Multi-Core 0xB2
Processors &
Network-on-Chip 0xC3

0x3C
Week 7 :
Network-on-Chip No, the answer is incorrect.
Architectures
Score: 0

Week 8 : QoS for Accepted Answers:

TCMPs at 0xC3
Storage and
Interconnect 5) The technique of separating dependent instruction from the source instruction by pipeline 1 point
Levels latency of the source instruction is called:

score boarding

compiler scheduling

operand forwarding

hyperthreading

No, the answer is incorrect.

Score: 0
Accepted Answers:
compiler scheduling

6) Which of the following statement is TRUE? 1 point

Structural hazards could be reduced by operand forwarding.

In a dynamically scheduled pipeline, instructions can pass through the issue stage out of
order.

During the execution of the MIPS instruction Add R1, R2, R3 some contents stored in its
EX/MEM pipeline register will bypass the MEM stage directly to MEM/WB pipeline register.

MIPS floating point adder needs 7 cycles in its execution stage.

No, the answer is incorrect.

Score: 0
Accepted Answers:
During the execution of the MIPS instruction Add R1, R2, R3 some contents stored in its EX/MEM pipeline
register will bypass the MEM stage directly to MEM/WB pipeline register.

7) A program which has 4000 instructions has 20% branch instructions, 32% load-store instructions
and the rest are ALU instructions. The program is running on a processor operating at 2 GHz. The
CPI of branch, load-store and ALU instructions are 2, 2.5, and 1.25, respectively. The execution time of
this program is ____ microseconds

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Hint

No, the answer is incorrect.

Score: 0
Accepted Answers:
(Type: Range) 3.59,3.61

1 point

8) A new floating-point unit speeds up floating point operations by 2.5 times. In an application one
fourth of the instructions are floating-point operations. What is the overall speedup?

Hint

No, the answer is incorrect.

Score: 0
Accepted Answers:
(Type: Range) 1.17,1.18

1 point

9) A processor with 10-stage instruction pipeline incurs three stalls due to data hazards for every 7
instructions. In addition to it, branch mis-prediction causes 5 cycles stall. If branches constitute 40% of
the instructions, and branch mis-prediction rate is 10%, what is the effective CPI considering both data
hazards and branch mis-predictions?

Hint

No, the answer is incorrect.

Score: 0
Accepted Answers:
(Type: Range) 1.62,1.63

1 point

10)Consider a MIPS multicycle instruction pipeline that executes the following instruction in sequence.
Assume that operand forwarding is enabled. The IF stage for the first LOAD instruction is at clock cycle
1, then the FADD instruction will write the result to F5 in ____ clock cycle. (Hint: LOAD uses integer
EX unit, FMUL and FADD uses 7-stage multiplier and 4-stage adder, respectively)

LOAD F2, 8(R2) // Load the value from the address [R2+8] to F4
FMUL F4, F2, F2 // F4 <- F2xF2
LOAD F3, 16(R1) // Load the value from the address of [R1+16] to F3
FADD F5, F4, F3 // F5 <- F4+F3

Hint

No, the answer is incorrect.

Score: 0
Accepted Answers:
(Type: Numeric) 17

1 point

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