Aim: - To design and implement Half Adder using Dataflow, Structural and Behavioural modeling

style.

Tools used: - Xilinx ISE Design Suite 12.4_5

Simulator Tool - ISim 12.3
Synthesis Tool – XST

Code (Dataflow Modeling):

module HALF_ADDER(input InputA,input InputB,output Sum,output
Carry);

assign Sum = InputA^InputB;

assign Carry = InputA&InputB;

endmodule
Results (Dataflow Modeling):
1. Module

2. Detailed RTL Schematic

3. Detailed Technological Schematic

4. Simulation Waveform
Code (Structural Modeling):
module Half_Adder(input IN1,input IN2,output Sum,output Carry);
xor2 x1(IN1,IN2,Sum);
and2 a1(.I1(IN1), .I2(IN2), .OUT_A(Carry));
endmodule

module xor2(input I1, input I2, output OUT_X);

assign OUT_X=I1^I2;
endmodule

module and2(input I1, input I2, output OUT_A);

assign OUT_A=I1&I2;
endmodule
Results (Structural Modeling):
1. Module

2. Detailed RTL Schematic

3. Detailed Technological Schematic

4. Simulation Waveform
Code (Behavioural Modeling):
module Behave_HA(input INA,input INB,
output reg Sum,
output reg Carry
);

always @(INA,INB)
begin
case({INA,INB})
 2'b00 : begin
Sum<=0;
Carry<=0;
end
2'b01 : begin
Sum<=1;
Carry<=0;
end
2'b10 : begin
Sum<=1;
Carry<=0;
end
2'b11 : begin
Sum<=0;
Carry<=1;
end
default: begin
Sum<=1;
Carry<=1;
end
endcase
end

endmodule

Results (Behavioural Modeling):

1. Module
2. Detailed RTL Schematic

3. Detailed Technological Schematic

Test Bench:
module TestBench_HalfAdder();

reg INA,INB;
wire Sum,Carry;
HALF_ADDER DUT(INA,INB,Sum,Carry);
Behave_HA DUT1(INA,INB,Sum,Carry);

initial
begin

INA=0;INB=0;
#10 INA=0;INB=1;
#10 INA=1;INB=0;
#10 INA=1;INB=1;
#10 $finish;

end

always @(INA,INB)
begin

$monitor("Time: %d , A: %b , B: %b , Sum: %b , Carry:

%b",$time,INA,INB,Sum,Carry);

end

endmodule
Results (Test Bench):
1. Simulation Waveform

2. Console Window

Conclusion:
In this experiment, we implemented Half-Adder in Verilog using Dataflow, Structural &
Behavioural Modeling style in Xilinx ISE Design Suite and observed the simulation waveform of
Half-Adder in ISim.