Unit 2 - Week 1: Assignment 1

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Unit 2 - Week 1
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outline Assignment 1
The due date for submitting this assignment has passed. Due on 2018-02-21, 23:59 IST.
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Week 1 1) Which one of the following is an important characteristic of a hard 1 point

real-time task and distinguishes hard real-time tasks from soft and firm real-
Lecture 1 : time tasks?
Introduction
The result produced by a task is discarded if produced after deadline
Lecture 2 :
Basics of Tast Application fails if the task produces result after its deadline
scheduling The utility of the result produced by a task decreases with time if the
Lecture 3: result is produced after the deadline
Cyclic The earlier is the result produced by a task, the higher is its utility.
executives
No, the answer is incorrect.
Lecture 4:
Score: 0
Cyclic
Scheduler Accepted Answers:
Application fails if the task produces result after its deadline
Lecture 5 :
Cyclic 2) Which one of the following is an important characteristic of a soft real- 1 point
Scheduler
time task and distinguishes it from hard and firm real-time tasks?
Week 1 Lecture
Material The result produced by the task is discarded if produced after deadline
Application fails if the task produces result after its deadline
Quiz :
Assignment 1 The utility of the result produced by a task decreases with time if the
result is produced after the deadline
Assignment-1
Solutions The utility of the result is independent of the time at which it is
produced.
Week 2
Week 3 Score: 0
Accepted Answers:
Week 4 The utility of the result produced by a task decreases with time if the result is
produced after the deadline
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VIDEOS 3) Which one of the following is an important characteristic of a firm 1 point
real-time task that distinguishes it from soft and hard real-time tasks?
The result produced by the task is discarded if produced after deadline

Application fails if the task produces a result after its deadline
Utility of the result produced by a task decreases with time if the result
is produced after the deadline
The earlier is the result produced by a task, the higher is its utility.
Score: 0
Accepted Answers:
https://onlinecourses.nptel.ac.in/noc18_cs12/unit?unit=5&assessment=36 1/3
The result produced by the task is discarded if produced after deadline
4) Which one of the following tasks can be considered to be a hard real- 1 point
time task?
Issue a book using a library management system

Withdraw cash from a bank ATM
Planning of the next step by a robot
Saving an opened file by a word processor

Score: 0
Accepted Answers:
Planning of the next step by a robot
5) Which one of the following is an important objective of a real-time 1 point
operating system?
Maximization of throughput

Guaranteeing fairness in task executions
Minimization of the response time of tasks
Production of the result of a task within a certain stipulated time period
Score: 0
Accepted Answers:
Production of the result of a task within a certain stipulated time period
6) Which one of the following is a satisfactory definition of the response 1 point
time of a job?
The time between a job becoming ready and the job completing
The time between a job starting to execute and the job completing
The time between a job becoming ready and the job being taken up for
execution
The total time a job waits before becoming ready
Score: 0
Accepted Answers:
The time between a job becoming ready and the job completing
7) Given that two tasks have different phases, which one of the 1 point
following can be inferred?
They have different periods

They have different execution times
Some of the instances of the two tasks may arrive exactly at the same
time
They have different deadlines
Score: 0
Accepted Answers:
Some of the instances of the two tasks may arrive exactly at the same time
8) For a periodic real-time task, which one of the following is true? 1 point
The absolute deadline changes for different task instances, but the
relative deadline is fixed
The relative deadline changes for different task instances, but the
absolute deadline is fixed
Both the relative deadline for different task instances, as well as the
absolute deadline are fixed
Both the relative deadline as well as the absolute deadline change for
different task instances
Score: 0
Accepted Answers:
The absolute deadline changes for different task instances, but the relative
deadline is fixed
9) Which one of the following is not true of a cyclic scheduler? 1 point
Computationally efficient
Takes very little memory space
Tolerant to changing execution times and periods of tasks
Can be used to schedule tasks with widely varying periods
Score: 0
Accepted Answers:
Tolerant to changing execution times and periods of tasks
10)Suppose a cyclic scheduler is used to schedule a set of periodic real-time tasks {Ti}. The 1 point
execution time, period, and deadline of a task Ti is given by <ei,Pi,di>. If the frame size chosen is F,
then which one of the following must be false?
F>max({ei})
F divides the major cycle
F –(gcd(F,Pi)/2) < di/2 for every task Ti
2×F – gcd(F,Pi) > di for every task Ti

Score: 0
Accepted Answers:
2×F – gcd(F,Pi) > di for every task Ti
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Unit 3 - Week 2
Course
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Week 1 1) Regarding rate monotonic scheduler (RMS) and earliest deadline first 1 point
scheduler (EDF), which one of the following can be said?
Week 2
EDF is more proficient than RMS
Lecture 6: RMS is more proficient than EDF
Exercises on
RMS and EDF are equally proficient
Frame size
Selection The proficiency of RMS and EDF cannot be compared
Lecture 7 : No, the answer is incorrect.
Event-driven Score: 0
schedulers
Accepted Answers:
Lecture 8 : Rate EDF is more proficient than RMS
Monotonic
Algorithm 2) Which one of the following types of events best define the scheduling 1 point
points for a rate monotonic scheduler
Lecture 9 : RMA
Task
Schedulability
Arrival of task instances
Completion of task instances
Lecture 10 :
Rate Monotonic
Both arrival and completion of task instances
Analysis Interrupts generated from a periodic timer
Feedback for No, the answer is incorrect.
Week 2 Score: 0
Quiz : Accepted Answers:
Assignment 2 Both arrival and completion of task instances
Week 2 Lecture
3) Which one the following is considered as a dynamic priority real-time 1 point
Material
task scheduler?
Assignment-2
Solutions Rate monotonic scheduler
Cyclic scheduler
Week 3
Deadline monotonic scheduler
Week 4 Earliest deadline first scheduler
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Score: 0
VIDEOS
Accepted Answers:
Earliest deadline first scheduler
4) Suppose three periodic tasks with execution times of 20 millisecond, 1 point
30 millisecond, and 40 millisecond, and periods of 150 millisecond, 250
millisecond, and 350 millisecond are to be run using a basic table-driven
scheduler. What is the minimum time period for which the task schedule
should be stored in a schedule table?
750 milliseconds
120 milliseconds
80 milliseconds
5250 milliseconds
Score: 0
Accepted Answers:
5250 milliseconds
5) In a foreground-background scheduler, a background task requiring 1 point
1400 milliseconds is to be run. Two foreground tasks T1 and T2 with execution
times 10 milliseconds and 15 milliseconds and periods of 50 milliseconds and
100 milliseconds respectively are also to be run. Assume all tasks have zero
phasing. What is the expected completion time for the background task?
1792 milliseconds
1876 milliseconds
2018 milliseconds
2154 milliseconds
Score: 0
Accepted Answers:
2154 milliseconds
6) What would be the processor utilization due to the following three 1 point
tasks when run on a uni-processor?
Task Execution Time (in millisec) Period (in millisec) Deadline (in millisec)
T1 10 100 100
T2 20 150 150
T3 5 50 50
0.68
0.44
0.34
0.24
Score: 0
Accepted Answers:
0.34
7) 7. If the tasks shown in the following table are to be run on a 1 point
uniprocessor by a rate monotonic scheduler, which one of the following is a
correct priority assignment to the tasks? Assume that the higher is the priority
value assigned to a task, the lower is its priority.
Task Execution Time (in millisec) Period (in millisec) Deadline (in millisec)
T1 10 100 100
T2 20 150 150
T3 5 50 50
Priority(T1)=1, Priority(T2)=2, Priority(T3)=3


Score: 0
Accepted Answers:
8) The utilization of an arbitrary set of periodic real-time tasks should be 1 point
at most which one of the following values for it to be guaranteed of feasible
scheduling by a rate monotonic scheduler?
1
0.87
0.73
0.69

Score: 0
Accepted Answers:
0.69
9) Which one of the following is not true of the EDF (Earliest Deadline 1 point
First) scheduling algorithm?
Poor transient overload handling

Non-optimal schedule
Runtime inefficiency
Poor support for resource sharing among tasks.
Score: 0
Accepted Answers:
Non-optimal schedule
10)What is the time complexity of an EDF scheduler in terms of the 1 point
number of tasks (n) to be scheduled, when tasks are maintained by the
scheduler using a priority queue?
O(n)
O(n2)
O(logn)
O(nlogn)
Score: 0
Accepted Answers:
O(nlogn)
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Unit 4 - Week 3
Course
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Week 1 1) Consider a certain application in which two periodic real-time tasks 1 point
are to be run on a uniprocessor using a rate monotonic scheduler. What should
Week 2 be the maximum processor utilization due to the two tasks, if it is required that
the two tasks should run without missing any deadlines?
Week 3
0.88
Lecture 11 : 0.82
RMA
0.76
Generalizations
0.73
Lecture 12 :
Further RMA No, the answer is incorrect.
Generalizations Score: 0
Lecture 13 : Accepted Answers:
Resource 0.82
Sharing among
Real-Time 2) Suppose a single periodic real-time task is to be run on a uniprocessor 1 point
Tasks using a rate monotonic scheduler. For the task to run without missing any
Lecture 14 : deadlines, what should be the maximum processor utilization due the task?
Solution to
Priority 1
Inversion 0.88
Problem
0.82
Lecture 15 : 0.76
Highest Locker
Protocol No, the answer is incorrect.
Feedback for
Score: 0
Week 3 Accepted Answers:
Quiz :
1
Assignment 3
3) Consider a periodic task set whose characteristics are shown in the 1 point
Week 3 Lecture following table. Would this task set be schedulable on a uniprocessor under
Material rate monotonic scheduling based on the Liu-Layland criterion for determining
Assignment-3
schedulability?
Solutions Task Set (All data in milliseconds)
Week 4 Task Execution Time Period Deadline
Task1 20 100 100

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Task3 40 400 400
Not likely to be schedulable but no guarantee can be given
Likely to be schedulable but no guarantee can be given

Guaranteed to be schedulable
Guaranteed to be unschedulable
Score: 0
Accepted Answers:
Guaranteed to be schedulable
4) 4. Consider a set of three periodic real-time tasks that are to be run 1 point
on a uniprocessor using a rate monotonic scheduler. The task characteristics
are given in the following table. What would be the worst case completion time
for Task1?
Task Set (All data in milliseconds)
Task Phase Execution Time Period Deadline
Task1 200 20 100 100
Task2 150 25 150 150
Task3 100 20 50 50
20 milliseconds
40 milliseconds
60 milliseconds
70 milliseconds
Score: 0
Accepted Answers:
60 milliseconds
5) Consider an application in which a set of periodic real-time tasks 1 point
share a set of non-preemptable resources and are scheduled using a rate
monotonic scheduler. Which one of the following problems cannot be
completely prevented even when choice can be made from any of the
available resource sharing protocols?
Deadlock
Chain blocking
Priority inversion
Unbounded priority inversion
Score: 0
Accepted Answers:
Priority inversion
6) Which one of the following is the closest definition of a critical 1 point
section?
A piece of code in which a shared non-preemptable resource is

accessed by a task
Any non-preemptable resource
Any shared non-preemptable resource
A piece of code in which a shared serially-preemptable resource is
accessed by a task
Score: 0
Accepted Answers:
A piece of code in which a shared non-preemptable resource is accessed by a
task
7) Consider an application in which a set of periodic real-time tasks 1 point
share a set of non-preeemptable resources and are scheduled using a rate
monotonic scheduler incorporating the basic priority inheritance protocol.
Which one of the following problems cannot occur in this situation?
Deadlock
Chain blocking
Priority inversion
Score: 0
Accepted Answers:
8) Assume that four periodic real-time tasks T1, T2, T3, and T4 share three non- 1 point
preemptable resources R1, R2, and R3 as shown in the following diagram. The
time for which each task needs a resource is annotated on the arrow connecting the task
to the corresponding resource. The tasks are arranged in decreasing order of their
priorities, with T1 being the highest priority task and T4 the lowest priority task. The tasks
are scheduled using a rate monotonic scheduler incorporating the basic priority
inheritance protocol. Which tasks would undergo direct blocking?
T1, T2, and T4

T1 and T2
T2 and T4
T2 only
Score: 0
Accepted Answers:
T1 and T2
9) Assume that four periodic real-time tasks T1, T2, T3, and T4 share three non- 1 point
are scheduled using a rate monotonic scheduler incorporating the basic priority
inheritance protocol. What is the maximum duration for which the Task T2 would undergo
direct blocking?
5 units
2 units
10 units
It does not undergo any direct inversion
Score: 0
Accepted Answers:
10 units
10)Assume that four periodic real-time tasks T1, T2, T3, and T4 share three non- 1 point
are scheduled using a rate monotonic scheduler with the basic priority inheritance
protocol. The task T3 would undergo inheritance blocking due to which tasks?
T1
T2
T4
Both T2 and T4
Score: 0
Accepted Answers:
T4
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Unit 5 - Week 4
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Week 1 1) ssume that four periodic real-time tasks T1, T2, T3, and T4 share 1 point
three non-preemptable resources R1, R2, and R3 as shown in the following
Week 2 diagram. The time for which a task needs a resource is annotated on the arrow
connecting the task to the resource. The tasks are arranged in decreasing
Week 3 order of their priorities. That is, T1 is the highest priority task and T4 is the
lowest priority task. The tasks are scheduled using a rate monotonic scheduler
Week 4 incorporating the basic priority inheritance protocol. What is the maximum
duration for which the task T3 would undergo inheritance blocking?
Lecture 16 :
Priority Ceiling
Protocol
Lecture 17 :
PCP Priority
Inversions
Lecture 18 :
Analysis of PCP
priority
inversions
5 units
Lecture 19 :
Some basic 8 units
issues in Real- 13 units
Time Operating
1 unit
Systems
Lecture 20 :
Unix as a Real- Score: 0
Time operating Accepted Answers:
System
5 units
Feedback for
Week 4 2) Assume that four periodic real-time tasks T1, T2, T3, and T4 share 1 point
Quiz : diagram. The time for which each task needs a resource is annotated on the
Assignment 4
arrow connecting the task to the resource. The tasks are arranged in
Week 4: Lecture decreasing order of their priorities. That is, T1 is the highest priority task and
Material T4 is the lowest priority task. The tasks are scheduled using a rate monotonic
Assignment-4 scheduler that incorporates the highest locker protocol for supporting
Solutions
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VIDEOS
resource sharing. What will be the ceiling priority of the resource R1?
Priority of T1
Priority of T2
Priority of T3
Priority of T4
Score: 0
Accepted Answers:
Priority of T1
3) Assume that four periodic real-time tasks T1, T2, T3, and T4 share 1 point
diagram. The time for which each task needs a resource is annotated on the
arrow connecting the task to the resource. The tasks are arranged in
decreasing order of their priorities. That is, T1 is the highest priority task and
T4 is the lowest priority task. The tasks are scheduled using a would undergo
direct blocking?
T1, T2, and T4

T1 and T2
T2 and T4
T2 only
Score: 0
Accepted Answers:
T1 and T2
4) Which one of the following represents the principal factor that makes 1 point
supporting sharing non-preemptable resources among real-time tasks under
dynamic priority task schedulers impractical?
It is not possible to design a resource sharing algorithm when task

priorities change dynamically
The basic inheritance scheme can only be used with rate monotonic
schedulers
Too much overhead in recomputing changed task and ceiling priorities
No feasible algorithms exist to support resource sharing in dynamic
priority situations
Score: 0
Accepted Answers:
Too much overhead in recomputing changed task and ceiling priorities
5) Which one of the following is false regarding the utilization-balancing 1 point
algorithm for task allocation in multiprocessors?
In the resultant allocation, the typical utilization of each processor is

different from the average utilization of the processors
It is a greedy algorithm
It is a non-optimal algorithm
It is typically used when the tasks assigned to the individual processors
are to be scheduled using rate monotonic schedulers
Score: 0
Accepted Answers:
It is typically used when the tasks assigned to the individual processors are to b
scheduled using rate monotonic schedulers
6) Which one of the following statements is true? 1 point
The priority ceiling protocol (PCP) can be considered to be a satisfactory

protocol to be deployed when a number of serially reusable preemptable
resources are to be shared among a set of real-time tasks.
When priority ceiling protocol (PCP) is used in a Unix-based real-time
operating system, the ceiling priority value of a critical resource would be
the maximum of the priority values of all the tasks using that resource.
Under PCP the duration for which a lower priority task can inheritance
block a higher priority task is also identical to the duration for which it can
avoidance block the higher priority task.
Under PCP even a task which does not require any resource may
undergo priority inversion for some duration on account of resource usage
by other tasks.
Score: 0
Accepted Answers:
Under PCP even a task which does not require any resource may undergo priorit
inversion for some duration on account of resource usage by other tasks.
7) Which one of the following statements is false? 0 points
POSIX 1003.4 (real-time standard) requires that real-time processes be

scheduled at priorities higher than kernel processes.
Under the Unix V operating system, computation intensive tasks
dynamically gravitate to higher priorities.
Unix V has a worst case interrupt latency time of about one second that
is primarily attributable to the non-preemptive kernel
Unix dynamically recomputes task priorities in an attempt to meet task
deadlines
Score: 0
Accepted Answers:
Unix dynamically recomputes task priorities in an attempt to meet task
deadlines
8) Which one of the following statements is false regarding a real-time 1 point
operating system that provides memory protection?
The cost of developing and testing a program on the operating system

would increase compared to when the operating system does not provide
memory protection.
The system calls for memory operations would be light weight.
Maintenance cost would increase for programs running on the operating

system compared to when the operating system does not provide memory
protection.
Memory overhead would be incurred to support memory protection.
Score: 0
Accepted Answers:
The system calls for memory operations would be light weight.
9) Assume that four periodic real-time tasks T1, T2, T3, and T4 share 1 point
diagram. The time for which each task needs a resource is annotated on the
arrow connecting the task with the corresponding resource. The tasks are
arranged in decreasing order of their priorities, with T1 being the highest
priority task and T4 the lowest priority task. The tasks are scheduled using a
rate monotonic scheduler incorporating the priority ceiling protocol (PCP) for
supporting resource sharing. What is the maximum duration for which the
task T3 would suffer avoidance related inversion?
5
8
10
0
Score: 0
Accepted Answers:
8
10)Assume that four periodic real-time tasks T1, T2, T3, and T4 share 1 point
diagram. The time for which a task needs a resource is annotated on the arrow
connecting the task to the resource. The tasks are arranged in decreasing
order of their priorities. That is, T1 is the highest priority task and T4 is the
lowest priority task. The tasks are scheduled using a rate monotonic scheduler
incorporating the priority ceiling protocol (PCP) for resource sharing. Which
task would not suffer any avoidance related inversions?
T1
T2
T3
T4
Score: 0
Accepted Answers:
T4
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Unit 1 - How to
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Assignment-00
The due date for submitting this assignment has passed.
How to access As per our records you have not submitted this Due on 2018-07-29, 23:59 IST.
the portal assignment.
How to access 1) How many full adders and half adders are required to construct an m-bit parallel adder? 1 point
the home
page?
m/2 full adders and m/2 half adders
How to access
the course m half adders
page?
m-1 full adders and 1 half adder
How to access
m+1 half adders
the MCQ, MSQ
and No, the answer is incorrect.
Programming
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assignments?
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Quiz :
m-1 full adders and 1 half adder
Assignment-00
2) How many types of flip-flops are generally used? 1 point
Introduction and
Modeling
2
Modeling and 3
Synthesis
issues 4
5
Architectural
Synthesis of No, the answer is incorrect.
Hardwares
Score: 0
System-level Accepted Answers:

Design 4
3) How many inputs and outputs does a D flip-flop has (excluding the clock) 1 point
Temporal Logic
2 inputs and 2 outputs

Model Checking
1 input and 2 outputs
BDD and

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System 4) A clock withPowered

frequency
by X (MHZ) is applied to a cascaded counter containing a modulus-4 1 point
Hardware counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is
Testing
________
Embedded
System X/4 MHz
Hardware X/8 MHz
Testing - II
X/32 MHz
Advances in
Embedded X/320 MHz
System
Hardware
Testing Score: 0
Accepted Answers:
Advances in X/320 MHz
Embedded
System 5) Which of the following describes most appropriately a “shift register”? 1 point
Hardware
Testing - II The register that can shift information bits to another register
Testing for The register that can shift information bits either to the right or to the left
Embedded
The register that can shift information bits to the right only
Software
Systems The register that can shift information bits to the left only

Score: 0
Accepted Answers:
The register that can shift information bits either to the right or to the left
6) Which among the following is the queue that keeps the processes that are residing in main 1 point
memory and are ready and waiting to be executed?
job queue
ready queue
execution queue
process queue

Score: 0
Accepted Answers:
ready queue
7) Which of the scheduling algorithms mentioned below works by allocating the CPU first to 1 point
the process that requests the CPU first?
first-come, first-served scheduling
shortest job scheduling
priority scheduling
none of the mentioned

Score: 0
Accepted Answers:
first-come, first-served scheduling
8) One of the following statements best describes the disadvantage of priority based 1 point
scheduling algorithm
Complex Scheduler in terms of computation

Schedule takes a lot of time
May lead to some low priority process waiting indefinitely for the CPU
none of the above

Score: 0
Accepted Answers:
May lead to some low priority process waiting indefinitely for the CPU
9) A Language for which a DFA can be constructed is a________ 1 point
Regular Language
Context free Language
Recursively enumerable language
None of the above

Score: 0
Accepted Answers:
Regular Language
10)In the formal definition of a deterministic finite state machine the number of tuples required 1 point
is

Score: 0
Accepted Answers:
5
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Unit 2 -
Introduction and Modeling
Course
outline
Assignment-1
Introduction and 1) An embedded system is a: 1 point

Modeling
Physical system enclosed within a computing system
Introduction
Physical system enclosed within a memory system
Modeling
Techniques – 1 Memory system enclosed within a physical system
Quiz : Computing system enclosed within a physical system
Assignment-1
Modeling and Score: 0
Synthesis
issues Accepted Answers:
Computing system enclosed within a physical system
Architectural
2) A real-time system must: 1 point
Synthesis of
Hardwares
Always produce correct outputs within a short time
System-level Sometimes produce correct outputs within a stipulated time
Design
Always produce correct outputs within a stipulated time
Temporal Logic
Sometimes produce correct outputs within a short time
Model Checking No, the answer is incorrect.

Score: 0
BDD and
Accepted Answers:
Symbolic Model
Checking Always produce correct outputs within a stipulated time
3) Which of the following systems could reasonably be considered to be safety-critical? 1 point

Introduction to
Digital Testing
Video-editing software
Embedded The software that controls traffic lights

System

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The softwarePowered
that controls
by the engines of an aircraft
Advances in
Embedded 4) Consider an embedded system with an aperiodic control task which arrives at time instant 2 1 point
System
(from system start) and requires 4 time units to complete execution. The processor starts executing this
Hardware
Testing job 2 time units subsequent to its arrival. What is the response time for this job?
Advances in 2
Embedded
4
System
Hardware 6
Testing - II
8
Testing for
Embedded
Software Score: 0
Systems Accepted Answers:
6
5) Design a mealy-type FSM to check whether a given integer is divisible by 3. What is the 1 point
minimum number of states required for this design?

Score: 0
Accepted Answers:
3
6) A mealy-type FSM associates outputs to: 1 point
States
Transitions
Both states and transitions
None of the above

Score: 0
Accepted Answers:
Transitions
7) The statechart language can be used to represent: 1 point
FSM
FSMD
HCFSM
PSM

Score: 0
Accepted Answers:
FSM
FSMD
HCFSM
8) In a HCFSM, AND-decomposition is used to model: 1 point

Concurrency
Precedence
Hierarchy
Abstraction

Score: 0
Accepted Answers:
Concurrency
9) Accurate estimates on execution times are difficult to obtain in embedded systems due to: 1 point
Micro-architectural intricacies such as pipeline stalls
Contention for shared caches
External inputs/outputs
Contention among programs running on a set of processors

Score: 0
Accepted Answers:
Micro-architectural intricacies such as pipeline stalls
Contention for shared caches
External inputs/outputs
Contention among programs running on a set of processors
10)A hard real-time safety-critical embedded system should: 1 point
Be verifiable and testable
Exhibit guaranteed worst-case performance
Exhibit high average-case performance
Be predictable and reliable

Score: 0
Accepted Answers:
Be verifiable and testable
Exhibit guaranteed worst-case performance
Be predictable and reliable
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Unit 3 -
Modeling and Synthesis issues
Course
outline
Assignment-2
Introduction and 1) Consider the transition diagram of DES G1 and G2 shown in the figure. 2 points
Modeling
Modeling and
Synthesis
issues
Compute the synchronous parallel composition of G1 and G2. The total number of (reachable
Modeling / accessible) states in the composite model G1||G2 is:
Techniques – 2
6
Hardware/Software
Partitioning - 1 9
Hardware/Software 5
Partitioning - 2
4
Introduction to
Hardware No, the answer is incorrect.
Design
Score: 0
Quiz : Accepted Answers:
Assignment-2
5
Architectural 2) 2 points
Synthesis of
Hardwares
System-level
Design
Temporal Logic
Model Checking Consider the task graph shown above in which all edges are of unit cost. An initial hardware-software
partition for the task graph is also shown through the cut line. With this as an input, a correct
BDD and enumeration of the vertices on each side of the partition after the second iteration of the inner repeat
Symbolic Model
loop in the Kernighan-Lin (KL) algorithm is:
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Testing Score: 0
Accepted Answers:
Embedded
System Partition-1: a, c, e, g; Partition-2: b, d, f, h
Hardware
3) For Question 2, the absolute gain (g) at the end of the third iteration is: 2 points
Testing - II
Advances in -2
Embedded
2
System
Hardware -1
Testing
1
Advances in
Embedded
System Score: 0
Hardware Accepted Answers:
Testing - II
-2
Testing for 4) RTL (Register Transfer Logic) design is obtained as an output of the_______phase 2 points
Embedded
Software
Architectural Synthesis
Systems
Logic Synthesis
Geometrical Synthesis
High-Level Synthesis

Score: 0
Accepted Answers:
Architectural Synthesis
High-Level Synthesis
5) Registers are connected to functional units via______and functional units are connected 2 points
to registers via______
MUXs, DMUXs
DMUXs, MUXs

Score: 0
Accepted Answers:
MUXs, DMUXs
Previous Page End


Unit 4 -
Architectural Synthesis of Hardwares
Course
outline
Assignment-3
Introduction and
Modeling
Modeling and
Synthesis
issues
Architectural
Synthesis of
Hardwares
Hardware
Architectural
Synthesis – 1
Hardware
Architectural
Synthesis – 2
Hardware
Architectural
Synthesis – 3
Hardware
Architectural
Synthesis – 4
Hardware
Architectural Consider the Operation Constraints Graph (OCG) shown in the figure above. Each addition
Synthesis – 5 operation takes unit time. The latency bound is 4. There are no resource constraints.
Hardware
Architectural 1) The correct ALAP schedule is: 1 point
Synthesis – 6
Hardware C-step 1: 1, 2. C-step 2: 3, 4. C-step 3: 5, 6. C-step 4: 7

Architectural
Synthesis – 7 C-step 1: 1, 2, 3. C-step 2: 4, 5. C-step 3: 6. C-step 4: 7
Quiz : © 2014C-step
NPTEL1:- 1, 2, 3, 4.
Privacy C-step- 2:
& Terms 5. C-step
Honor Code 3: 6. C-step
- FAQs - 4: 7
Assignment-3
A project of
C-step 1: 1. C-step 2: 2, 3, In
4. association
C-step 3: 5,with
6. C-step 4: 7
System-level No, the answer is incorrect.
Design
Score: 0
Funded by
Accepted Answers:

C-step 1: 1, 2. C-step by
Powered 2: 3, 4. C-step 3: 5, 6. C-step 4: 7
Temporal Logic
2) The mobility for each node (from 1 to 7) in OCG is: 1 point
Model Checking
0, 1, 0, 0, 0, 1, 0
BDD and
Symbolic Model 0, 1, 1, 0, 1, 0, 0
Checking
0, 0, 1, 0, 1, 0, 0
Introduction to 0, 0, 1, 0, 1, 1, 0
Digital Testing
Embedded Score: 0
System Accepted Answers:
Hardware
0, 0, 1, 0, 1, 0, 0
Testing
3) A valid list schedule for the OCG assuming only one adder resource is: 1 point
Embedded (Note: Assume the priority of a operation as (1 / (mobility + 1))).
System
Hardware
Testing - II 1, 2, 4, 6, 3, 5, 7
1, 2, 3, 4, 5, 6, 7
Advances in
Embedded 1, 2, 4, 3, 6, 5, 7
System
Hardware 1, 2, 3, 5, 4, 6, 7
Testing
Score: 0
Advances in
Embedded Accepted Answers:
System 1, 2, 4, 6, 3, 5, 7
Hardware
Testing - II 4) A new addition (+) operation having index-9 has been introduced to the OCG. This newly 1 point
included operation takes the output of operations 1 and 3 as input and floats its output on operation 7.
Testing for What will be minimum number of resources (i.e., adders) required to schedule this modified OCG with
Embedded a latency bound of 4.
Software
Systems
1

Score: 0
Accepted Answers:
3
5) Consider the modified OCG discussed in Q4. Let binary decision variables of type x(i,j) 3 points
denote the assignment of operation-i at time step-j. x(i,j) is 1 if operation-i is scheduled at time step-j.
x(i,j) is 0 otherwise. There are two adders and latency bound is 5. Determine the correct inequality
representing the resource constraint at time step 2.
x(3,2) + x(4,2) + x(5,2) + x(9,2) <= 2
x(1,2) + x(2,2) + x(3,2) + x(4,2) + x(5,2) <= 2
x(1,2) + x(2,2) + x(3,2) + x(4,2) + x(5,2) + x(9,2) <= 2
x(1,2) + x(2,2) + x(3,2) + x(4,2) + x(5,2) + x(9,2) + x(6,2) <= 2

Score: 0
Accepted Answers:
x(1,2) + x(2,2) + x(3,2) + x(4,2) + x(5,2) + x(9,2) <= 2

6) Consider the modified OCG discussed in Q4 and Q5. Determine the correct inequality 3 points
representing the dependency constraint between operations 9 and 3.
x(9,2) + x(9,3) - x(3,1) - x(3,2) >= 1
x(9,2) + x(9,3) + x(9,4) - x(3,1) - x(3,2) - 3x(3,3) - 1 >= 0
2x(9,2) + 3x(9,3) + 4x(9,4) - x(3,1) - 2x(3,2) - 3x(3,3) >= 0
2x(9,2) + 3x(9,3) + 4x(9,4) - x(3,1) - 2x(3,2) - 3x(3,3) >= 1

Score: 0
Accepted Answers:
2x(9,2) + 3x(9,3) + 4x(9,4) - x(3,1) - 2x(3,2) - 3x(3,3) >= 1
Previous Page End

Unit 5 -
System-level Design
Course
outline
Assignment-4
Introduction and 1) Consider a set of 6 tasks, T1 (1, 5), T2 (2, 10), T3 (3, 15), T4 (3, 15), T5 (2, 5), and T6 (1, 2 points
Modeling 5), to be executed on two unit capacity processors using either Pfair or ERfair scheduling schemes.
Modeling and Notation: Tk (e, p) denotes a task Tk with execution time “e” and period “p”.
Synthesis
issues
What is the pseudo-deadline of second subtask of task T5 when scheduled using ERfair?
Architectural
Synthesis of 5
Hardwares
8
System-level 10
Design
7
System Level
Analysis
Score: 0
Uniprocessor
Scheduling – 1
Accepted Answers:
5
Uniprocessor
Scheduling – 2 2) Consider a set of 7 tasks, T1 (3, 10), T2 (10, 20), T3 (10, 20), T4 (6, 10), T5 (5, 10), T6 (8, 2 points
20), and T7 (2, 10) to be executed on three unit capacity processors using DPfair scheduling scheme.
Multiprocessor
Scheduling – 1
Notation: Tk (e, p) denotes a task Tk with execution time “e” and period “p”.
Multiprocessor
Scheduling – 2
What is the workload of task T6 for the first time-slice?
Quiz :
Assignment-4 5
Temporal Logic 6
3
Model Checking
4
BDD and
Funded by

System processing using “Earliest

Powered byDeadline First” scheduling scheme.
Hardware
Testing
Embedded
System
Hardware
Testing - II
Advances in
Embedded
System
What is the response time of job J1, J2 and J3, respectively?
Hardware
Testing
Advances in 0, 4, 5
Embedded
System 10, 3, 10
Hardware 23, 3, 12
Testing - II
33, 28, 29
Testing for
Embedded No, the answer is incorrect.
Software Score: 0
Systems
Accepted Answers:
23, 3, 12
4) Time taken by a task instruction can depend on whether: 2 points

1. branch prediction was correct or wrong
2. interrupt occurs from a peripheral device
3. there is a hit or miss in the instruction cache
4. resource contention occur with other executing tasks
1 and 2
2 and 4
1 and 3
3 and 4

Score: 0
Accepted Answers:
1 and 3
5) Consider a uniprocessor system processing three (implicit-deadline) periodic tasks T1, T2, 2 points
and T3, respectively. The task parameters are listed in the following table.
This task set is _________ under Rate-Monotonic (RM), and ___________ under Earliest-Deadline
First (EDF) algorithms?
Schedulable, Unschedulable
Schedulable, Schedulable

Unschedulable, Unschedulable
Unschedulable, Schedulable

Score: 0
Accepted Answers:
Unschedulable, Unschedulable
Previous Page End

Unit 6 -
Temporal Logic
Course
outline
Assignment-5
Introduction and 1) Verification process checks: 1 point

Modeling
For the faults after manufacturing
Modeling and
Synthesis Whether the manufactured device matches the design
issues
Whether the manufactured device matches the specification
Architectural Whether the system design matches the specification

Synthesis of
Hardwares No, the answer is incorrect.
Score: 0
Design
Whether the system design matches the specification
Temporal Logic 2) Which are the inputs to a particular model checking / verification tool? 1 point
Introduction
Model and Error Trace
and Basic
Operators of Specification and Error Trace
Temporal Logic
Model and Specification
Syntax and
Semantics of Model, Error Trace, and Specification
CTL
Quiz : Score: 0
Assignment-5
Accepted Answers:
Model Checking Model and Specification
3) Given a model M and for a temporal formula φ, where (M, Sj) |= φ, which of the following 1 point
BDD and
Symbolic Model is FALSE?
Checking
φ does not strictly hold statically in a model M.
Introduction to
φ holds for the state Sj in the model M.
Funded by

System φ holds for all states in

Powered bythe model M.
Hardware
Testing - II 4) What does the temporal formula P -> GQ indicates? 1 point
Advances in If Q is TRUE in a state, then P is TRUE for all of its future states
Embedded
System Q is TRUE for all the future states
Hardware
Testing P and Q are TRUE for all the future state
If P is TRUE in a state, then Q is TRUE for all of its future states

Advances in
Embedded No, the answer is incorrect.
System Score: 0
Hardware
Testing - II Accepted Answers:
If P is TRUE in a state, then Q is TRUE for all of its future states
Testing for 5) If p is an atomic proposition, express the following in temporal logic. p is true in the next 1 point
Embedded
state but not in the next to next state.
Software
Systems
Xp V !XXp
Xp Λ XXp
Xp Λ !XXp
Xp V XXp

Score: 0
Accepted Answers:
Xp Λ !XXp
6) What does the temporal formula P->Previous(Q) mean? 1 point
If P holds in a state then its previous state holds Q
If Q holds in a state then its next state holds P
If P holds then Q holds eventually
If P holds then eventually in the past Q holds

Score: 0
Accepted Answers:
If P holds in a state then its previous state holds Q
7) Given a Model M. What does (M,Sj) |= Globallyinpast(φ) indicates? 1 point
For all k, k > j, (M , Sk) |= φ
For all k, k >= j, (M , Sk) |= φ
For all k, k < j, (M , Sk) |= φ
For all k, k <= j, (M , Sk) |= φ

Score: 0
Accepted Answers:
For all k, k <= j, (M , Sk) |= φ
8) What does the temporal formula (Previous(Q) Λ Q) V GQ mean? 1 point
Q holds in the previous, present, and the future states
Q holds either in the present and previous states or in all the future states
Q holds either in the previous or in the present state.

Q holds either in the previous or in all the future states.

Score: 0
Accepted Answers:
Q holds either in the present and previous states or in all the future states
9) Which of the following is FALSE? 1 point
P V XQ <=> Either P holds in a state or Q holds in the next state.
XP V XXP <=> P is TRUE in the next state or the next but one.
GFP <=> P is infinitely often TRUE.
(P Λ (Q U R)) <=> P holds in a state and R holds until Q holds

Score: 0
Accepted Answers:
(P Λ (Q U R)) <=> P holds in a state and R holds until Q holds
10)Which of the following statements is a strict condition for a CTL formula? 1 point
Every path quantifier of a CTL formula should be followed by a logic operator
Every path quantifier of a CTL formula should be preceded by a temporal operator
Every temporal operator of a CTL formula should be preceded by a path quantifier
Every temporal operator of a CTL formula should be followed by a path quantifier

Score: 0
Accepted Answers:
Every temporal operator of a CTL formula should be preceded by a path quantifier
11)Which of the following is FALSE? 1 point
AGp <=> p Holds Globally in all paths
EFp <=> There exists some path where p holds in future
AXp <=> In all paths, p holds in the next state
AFp <=> In all paths, p holds in all the future states

Score: 0
Accepted Answers:
AFp <=> In all paths, p holds in all the future states
12)Which of the following is not a CTL Formula? 1 point
AF EG p
A [p U A[q U r]]
EFGr
EGp V E(q U r)

Score: 0
Accepted Answers:
EFGr
13)Which of the following is a CTL Formula? 1 point

AEFr
F [ r U q]
AG ¬(p Λ q)
A [p U q U r]

Score: 0
Accepted Answers:
AG ¬(p Λ q)
14)A Kripke Structure consists of 1 point
A finite set of states S
A transition relation ->
A labelling function L, and a finite set of states S
A finite set of states S, a transition relation ->, and a labelling function L

Score: 0
Accepted Answers:
A finite set of states S, a transition relation ->, and a labelling function L
15)Which of the following is not a Kripke Structure? 1 point


Score: 0
Accepted Answers:
16)Which one of the following state transition diagrams represents the given Kripke structure 1 point
< S, ->, L > specified below?
S = {s1, s2, s3, s4, s5, s6}

-> = { {s1,,s2} , {s1,s3}, {s2,s3}, {s2,s4}, {s3,s4}, {s3,s5}, {s4,s5}, {s5,s6}, {s6,s4}}
L: L(s1) = {p,q}, L(s2) = {p}, L(s3) = {p,q,r}, L(s4) = {p,r}, L(s5) = {r}, L{s6} = {q}


Score: 0
Accepted Answers:
17) Which satisfaction relation(s) is/are true in the following Kripke 1 point
structure
[M, S0] |= A[p U q]
[M, S0] |= E[p U r]
[M, S0] |= E[p U q]
Both b and c

Score: 0
Accepted Answers:
Both b and c
18)For the following state transition diagram, which of the following options hold TRUE value 1 point
for the states {S0,S1,S2,S3}?

qVr
pΛq
pVr
pΛr

Score: 0
Accepted Answers:
pVr
19) For the below diagram, which of the states have TRUE value for A (p U q)? 0 points
{ S0 }
{ S1 }
{ S0,S1 }
{ S 1, S 3, S 4, S 6 }

Score: 0
Accepted Answers:
{ S 1, S 3, S 4, S 6 }
Previous Page End

Unit 7 - Model Checking
Course outline Assignment-6

How to access the The due date for submitting this assignment has passed. Due on 2018-09-12, 23:59 IST.
portal As per our records you have not submitted this assignment.
Introduction and 1) Which of the following equivalences is wrong for the temporal operators? 1 point
Modeling
AFφ = ¬EG¬φ
Modeling and
¬AFφ = EG¬φ
Synthesis issues
EFφ = ¬AF¬φ
Architectural
Synthesis of ¬EFφ= AG¬φ
Hardwares
Score: 0
System-level Design
Accepted Answers:
Temporal Logic EFφ = ¬AF¬φ
2) Which of the following sets is an adequate set of temporal operators? 1 point

Model Checking
Equivalence EX, AU
between CTL
formulas EX, AU, and EU
Model Checking AG, EG, and AF

Algorithm
AG and EG
Quiz : Assignment-6
BDD and Symbolic Score: 0
Model Checking Accepted Answers:
EX, AU, and EU
Introduction to
Digital Testing 3) Which of the following is FALSE about a temporal operators φ and p? 1 point
Embedded System AGφ, EGφ, AFφ, and EFφ can be written in terms of AUφ and EUφ
Hardware Testing
AXφ can be written with EGφ
Embedded System
EXφ, EGφ (AFφ) and E(φ U p) is an adequate set of operators
Hardware Testing - II
AXφ can be written with EXφ
Advances in
Embedded System No, the answer is incorrect.
Hardware Testing Score: 0
Accepted Answers:
Advances in
AXφ can be written with EGφ
Embedded System
Hardware Testing - II 4) If the future temporal operator (F) includes the present, then which of the following equivalences is true? 1 point
Testing for EFp = EX EFp

Embedded Software
Systems EFp = p Λ EX EFp
EFp = p V EX EFp

A project of In association with Funded by
Powered by

5) Let p and q are atomic propositions. Which of the following pairs of CTL formulae is not equivalent? 1 point
AFp V AFq and AF(p V q)
AG(p Λ q) and AGp Λ AGq
T and AGp -> EGp
EFp Λ EFq and EF(p V q)

Score: 0
Accepted Answers:
EFp Λ EFq and EF(p V q)
6) Which of the following pairs of CTL formulae is equivalent? 1 point
EFp Λ EFq and EF(p Λ q)
EFp V EFq and EF(p V q)
EFp and EGp
T and EGp -> AGp

Score: 0
Accepted Answers:
EFp V EFq and EF(p V q)
7) What does the CTL model checking algorithm do? 1 point
Iteratively determines states which satisfy a given CTL formula
A CTL formula is derived from the states of the model
Determines the equivalent states of the model
A model is created using specifications

Score: 0
Accepted Answers:
Iteratively determines states which satisfy a given CTL formula
8) What are the inputs and outputs for the labelling algorithm for model checking? 1 point
INPUTS = Set of states which satisfy φ and a CTL Formula φ. OUTPUT = A CTL Model M = (S, ->, L).
INPUTS = A CTL Model M = (S, ->, L) and a Set of states which satisfy φ. OUTPUT = CTL Formula φ.
INPUTS = A CTL Model M = (S, ->, L) and a CTL Formula φ. OUTPUT = Set of states which satisfy φ.
INPUTS = A CTL Model M = (S, ->, L). OUTPUT = A CTL Formula φ.
Score: 0
Accepted Answers:
INPUTS = A CTL Model M = (S, ->, L) and a CTL Formula φ. OUTPUT = Set of states which satisfy φ.
9) Which of the following is not a subformula of the CTL Formula AGp Λ AGq 1 point
AG p
pΛq

Score: 0
Accepted Answers:
pΛq
10)Which of the following SAT function is FALSE? 1 point
SAT{φ1 V φ2} => SAT{φ1} U SAT{φ2}
SAT{φ1 Λ φ2} => SAT{φ1} Ո SAT{φ2}
SAT{AX φ1} = SAT {¬EX ¬φ1}

SAT{EF φ1} = SAT{¬E{T U φ1}}

Score: 0
Accepted Answers:
SAT{EF φ1} = SAT{¬E{T U φ1}}
11)SATEX(p) is a function that determines the set of states satisfying EXp. In the given figure, SAT(p) = {S4, S6}. 1 point
What is SATEX(p)?
{S1, S2, S3}
{S1, S3}
{S1}
{S1, S3, S4, S6}

Score: 0
Accepted Answers:
{S1, S3}
12)SATAF(p) is a function that determines the set of states satisfying AFp. In the given figure, SAT(p) = {S4, S6}. 1 point
What is SATAF(p)?
{S0}
{S1, S3}
{S1, S3, S4, S6}
{S0, S1, S3}


Score: 0
Accepted Answers:
{S1, S3, S4, S6}
13)Let SATEU(p,q) be a function that determines the set of states satisfying E(p U q). In the given figure, SAT(p) = 1 point
{S1, S2} and SAT(q) = {S3}. Now, What is SATEU(p,q)?
{S3}
{S3, S4, S5}
{S1, S2, S3}
{S1, S2}

Score: 0
Accepted Answers:
{S1, S2, S3}
14)Let p be an atomic proposition. Choose the correct one? 1 point
AF ( p ) = E[ T U p ]
AF (p ) = p V AXAF (p)
EF ( p ) = p V AXAF (p)
AF (p ) = p Λ AXAF (p)

Score: 0
Accepted Answers:
AF (p ) = p V AXAF (p)
15)Consider the mutual exclusion example with 4 processes, P1, P2, P3, and P4. The atomic propositions for Pi 1 point
are ni, ti and ci , where 1 = i = 4. What is the CTL formula to represent Safety property?
AG ¬((c1 Λ c2) V c3 V c4 )
AG ¬((c1 Λ c3) V c2 V c4)
AG ¬ ((c2 Λ c3) V c1 Λ c3)
AG ¬ (c1 Λ c2 Λ c3 Λ c4)

Score: 0
Accepted Answers:
AG ¬ (c1 Λ c2 Λ c3 Λ c4)
16)Consider the model M shown in the figure. p is an atomic proposition. Determine the set of states satisfying AXp 1 point
using model checking algorithm, where

S4, S7, S1
S1, S3, S7
S1, S3, S5
S3, S4, S7

Score: 0
Accepted Answers:
S3, S4, S7
17)Consider the model M shown in the figure. p and q are atomic propositions. Determine the set of states 1 point
satisfying E(pUq) using model checking algorithm.
S1, S4, S5, S2

S3, S4, S5
S1, S4
S1, S4, S5, S6, S7

Score: 0
Accepted Answers:
S1, S4, S5, S6, S7
18)Consider the model M shown in the figure. p and q are atomic propositions. Determine the set of states 1 point
satisfying AF(¬p Λ q) using model checking algorithm.
S3
S3, S4, S1
S3, S4
S4

Score: 0
Accepted Answers:
S3
Previous Page End

Unit 8 - BDD
and Symbolic Model Checking
Course
outline
Assignment-7
Introduction and 1) Binary Decision Diagram (BDD) construction of a Boolean expression is based on 1 point
Modeling _____________.
Modeling and Shannon expansion

Synthesis
issues SOP representation
POS representation
Architectural
Synthesis of Both b & c
Hardwares
System-level Score: 0
Design
Accepted Answers:
Shannon expansion
Temporal Logic
2) How many nodes are required to create a Binary Decision Tree having 4 variables? 1 point
Model Checking
24
BDD and
Symbolic Model 25
Checking
25-1
Binary Decision
24-1
Diagram
Use of OBDDs
for State Score: 0
Transition Accepted Answers:
System
25-1
Symbolic Model
3) Find the number of terminal nodes of a Boolean function f(a,b,c)=a’b+abc+b’c’ in BDT and 1 point
Checking
BDD representation.
Quiz :
Assignment-7
BDT=5, BDD=5

Funded by

Accepted Answers:
Powered by
Embedded
BDT=8, BDD=2
System
Hardware
4) Which Boolean function is represented by the given ROBDD? 1 point
Testing - II
Advances in
Embedded
System
Hardware
Testing
Advances in
Embedded
System
Hardware
Testing - II
Testing for
Embedded
Software
Systems
f = b’+a’c’
f = a’+b’c’
f = a’b’+c’
f = a’+b’+c’

Score: 0
Accepted Answers:
f = b’+a’c’
5) Which one is the ROBDD for the given Boolean expression f=abc+a’c’? Assume variable 1 point
ordering is <a,b,c>



Score: 0
Accepted Answers:
6) Which among the following are false for the given BDD, where 0 points
path 1 : x-y-z-y-1
path 2 : x-y-z-y-0

Both path 1 and path 2 are inconsistent
Path 1 is consistent and path 2 is inconsistent
Path 1 is inconsistent and path 2 is consistent.
Both path 1 and path 2 are consistent.

Score: 0
Accepted Answers:
Path 1 is consistent and path 2 is inconsistent
7) What will be the optimal ordering of variables for the Boolean function f=ab+a’c+bc’d? 1 point
<a,b,c,d>
<a,c,d,b>
<a,b,d,c>
<a,c,b,d>

Score: 0
Accepted Answers:
<a,c,d,b>
8) Let BX and BY are two ROBDDs representing Boolean function f(a,b,c)=a'b+ac+bc' with 1 point
variable ordering <a, b, c> and <c, a, b> respectively. The number of nodes in B X and BY are :
BX=5, BY=5
BX=5, BY=6
BX=6, BY=5
BX=6, BY=6

Score: 0
Accepted Answers:

BX=6, BY=5
9) Consider the Boolean function of 2-bit comparator, f(a1,a2,b1,b2)= (a1 XNOR b1) . (a2 1 point
XNOR b2). Consider a ROBDD that represents f with variable ordering < a1, a2, b1, b2>. How many
nodes will this ROBDD have?
10
11
12
14

Score: 0
Accepted Answers:
11
10)Consider the Boolean function f(a,b,c,d)= ab'c + ab + c'd+ bcd. Construct ROBDD B f to 1 point
represent f. Assume order of variables is <a, b, c, d>. The number of nodes in B f is:

Score: 0
Accepted Answers:
8
11)Consider the boolean function in the question 10. Construct ROBDDs BX and BY to 1 point
represent restrict (0,c,Bf) and restrict(1,c,Bf), respectively. Assume order of variables is <a, b, c, d>.
The number of nodes in BX and BY are:
BX = 5, BY = 5
BX = 6, BY = 5
BX = 5, BY = 6
BX = 6, BY = 6

Score: 0
Accepted Answers:
BX = 5, BY = 5
12)Consider the ROBDDs constructed in question 11 using the Boolean function given in 1 point
question 10. Construct ROBDD Bz to represent exists(c,Bf) using Bx and By. Assume order of variables
is <a, b, c, d>. The number of nodes in Bz are:

Score: 0
Accepted Answers:

13)Let f(x, y) = x(y + x') be a Boolean function. What will be the restrictions of f with respect to 1 point
x, if x=0. and x=1 respectively?
0, xy
x', xy
0, y
x', x+y

Score: 0
Accepted Answers:
0, y
14)Which among the following is True? 1 point
Pre∀(X) = S- Pre∃(X)
Pre∀(X) = S- Pre∃(S-X)
Pre∃(X)= S-Pre∀(X-S)
Pre∃(X)= S-Pre∀(S-X)

Score: 0
Accepted Answers:
Pre∀(X) = S- Pre∃(S-X)
15)What is Pre∃(X) for the given state transition diagram where S={x1,x2,y1,y2,y3,y4} and 1 point
X={y2,y3}?
{x2,y1,y2,y3}
{x2,x1,y1,y3}
{x2,y1,y3}
{y1,y3,y4}

Score: 0
Accepted Answers:
{x2,y1,y3}

16)What is Pre∀(X) for the state transition diagram shown in Question 15? 1 point
{x2,y1}
{x2,y1,y3}
{x1,x2,y3}
{x1,x2,y1,y3}

Score: 0
Accepted Answers:
{x2,y1}
17)Which of the following symbolic model checking function returns Pre∃(Bφ), where Bφ is the 1 point
OBDD for set of states where φ is true?
EF(Bφ)
AF(Bφ)
AG(Bφ)
EX(Bφ)

Score: 0
Accepted Answers:
EX(Bφ)
Previous Page End

Unit 9 - Introduction to
Digital Testing
Course outline Assignment-8

How to access the The due date for submitting this assignment has passed. Due on 2018-09-26, 23:59 IST.
portal As per our records you have not submitted this assignment.
Introduction and 1) Murphy’s Law states that _______ 1 point

Modeling
If anything can go wrong, it will
Modeling and
If nothing goes wrong, it will
Synthesis issues
If anything can go wrong, it will not
Architectural
Synthesis of If nothing goes wrong, it will not
Hardwares
Score: 0
System-level Design
Accepted Answers:
Temporal Logic If anything can go wrong, it will
2) Figure below illustrates the process of Embedded Systems Design and Test flow. What is the block marked 1 point
Model Checking
“1” in the figure?
BDD and Symbolic
Model Checking
Introduction to
Digital Testing
Introduction to
Digital VLSI Testing
Automatic Test
Pattern Generation
(ATPG)
Quiz :
Assignment-8
Embedded System
Hardware Testing
Embedded System
Hardware Testing - II
Test Response storage
Advances in Integration
Embedded System
Hardware Testing Test Response compressor
Copy of Manufactured circuit under test

Advances in
Embedded System No, the answer is incorrect.
Hardware Testing - II Score: 0
Accepted Answers:

A project of In association with Funded by
Powered by

Data flow-based testing
None

Score: 0
Accepted Answers:
Design for testability
4) Figure below illustrates a process of ____ circuit testing. 1 point
Digital
Analog
Both of the above
None of the above

Score: 0
Accepted Answers:
Digital
5) For an n-input circuit, ____ test patterns are needed for functional testing. 1 point
2n
n2
2n

Score: 0
Accepted Answers:
2n
6) A circuit with n nets can have ___ possible stuck-at faults under single stuck-at fault model. 1 point
2n
n2
infinite
2n

Score: 0
Accepted Answers:
2n
7) How many test patterns are needed to test the circuit given in the figure below? Assume that structural 0 points
testing with single stuck at fault model is used.

25
60
192
160

Score: 0
Accepted Answers:
192
8) Functional and structural testing of the 32-Bit adder circuit shown below needs ____ and ____ test patterns, 1 point
respectively.
265, 23
2 * 65, 23
265, 2 * 3
65, 3

Score: 0
Accepted Answers:
265, 23
9) How many stuck-at faults are possible in the AND-gate shown below? 1 point

12
11
10

Score: 0
Accepted Answers:
12
10)A net having fan-out to k gates will have ___ stuck at fault locations 1 point
k+1
k-1
2k
None

Score: 0
Accepted Answers:
k+1
11)Which of the following statement is generally valid for a circuit? 1 point
All faults are “easy to test”
All faults are “difficult to test”
Few faults are “easy to test” and most others are “difficult to test”
Most faults are “easy to test” and few are “difficult to test”

Score: 0
Accepted Answers:
Most faults are “easy to test” and few are “difficult to test”
12)The test patterns for “easy to test faults” are derived by ____ 1 point
Fault simulation algorithms
Sensitization–propagation -justification approach
Boolean Difference approach
All the above

Score: 0
Accepted Answers:
13)The test patterns for “difficult to test faults” are derived by ____ 1 point
both (a) and (b)
other than the above


Score: 0
Accepted Answers:
14)Let us consider a 2-input AND gates shown in figure below where the inputs are marked using notations 1 point
from Roth’s 5-valued algebra. What is the output notation at the ? marked net i.e., output of gate G1?

Score: 0
Accepted Answers:
D
15)Consider figure of Question 14. What is the output notation at the ? marked net i.e., output of gate G2? 1 point
D̅
D

Score: 0
Accepted Answers:
D̅
16)Consider figure of Question 14. What is the output notation at the ? marked net i.e., output of gate G3? 1 point

Score: 0
Accepted Answers:
X
17)If one wants to take the path “e-f-g-h” in the figure below for propagating the fault effect to the output h. The 1 point
signals labelled as 1, 2, 3 in the nets of the path are assigned in terms of Roth’s 5 valued algebra. The signal value of the
net labelled with 1 is _____.


Score: 0
Accepted Answers:
D
Previous Page End

Unit 10 -
Embedded System Hardware Testing
Course
outline
Assignment-9
How to access As per our records you have not submitted this assignment.
the portal
1) To test the sequential circuits, the number of test patterns are required in time frame expansion 1 point
Introduction and method is:
Modeling
No. of primary inputs
Modeling and
Synthesis issues dseq+ 1
2No. of primary inputs

Architectural
Synthesis of 1
Hardwares
System-level Score: 0
Design Accepted Answers:
dseq+ 1
Temporal Logic
2) Which of the following is TRUE about the testing of sequential circuits? 1 point
Model Checking
Test pattern generation is complicated than of combinational circuits.
BDD and
Multiple number of test patterns are required.
Symbolic Model
Checking If the output of a flip-flop can be controlled by only primary inputs, its sequential depth is 1
Introduction to All of the above

Digital Testing
Score: 0
Embedded
System Hardware Accepted Answers:
Testing All of the above
Scan Chain 3) With set/reset flip-flops, how many patterns are required to test a fault in sequential circuits? 1 point
based
Sequential
1
Circuit Testing
(Contd. from dseq + 1
Previous
Module) 2
Software- dseq
Hardware

Funded by

Quiz : Powered by
A requirement of a package of thousands of I/O pins, which makes it impractical.
Assignment-9
A shift register is used and loads itself with the pattern required for setting the flip-flops
Embedded
System Hardware Only 3 extra I/O lines are required for testing a fault
Testing - II
Both b & c are TRUE
Advances in No, the answer is incorrect.

Embedded Score: 0
System Hardware
Testing Accepted Answers:
Both b & c are TRUE
Advances in
5) Which of the following is not among the three new I/Os added for ATPG Set and reset by shift 1 point
Embedded
System Hardware register?
Testing - II
S_clock
Testing for
Embedded S_in
Software Systems
test in
test out

Score: 0
Accepted Answers:
S_in
6) Which of the following is FALSE for Scan Chain based Testing? 1 point
The flip-flops in the circuit are converted under test itself to a shift register
Area overhead for testing is huge
In test mode, the flip-flops are decoupled from the circuit and they are connected in form of a shift
register
if there are nff flip-flops, then nff clock pulses are required to set/reset the flip-flops

Score: 0
Accepted Answers:
Area overhead for testing is huge
7) High level fault models for RTL must be: 1 point
Convenient representation of the effect of the physical defects or failures
Well-correlated with the physical defects of the circuit
Test schemes of higher description level to improve the scalability
All of the above

Score: 0
Accepted Answers:
All of the above
8) For High level fault models for RTL: 1 point
Number of test patterns required is higher than structural testing
Minimizes test pattern generation time
Higher accuracy than gate-level fault models are ensured
All of the above

Score: 0

Accepted Answers:
Minimizes test pattern generation time
9) For the sequential circuit shown below, Which of the following is TRUE? 1 point
The circuit has Scan chain and is in functional mode
The circuit does not have scan chain
The circuit has scan chain but is permanently disabled
The circuit has Scan chain and is in test mode

Score: 0
Accepted Answers:
The circuit has Scan chain and is in functional mode
Previous Page End

Unit 11 -
Embedded System Hardware Testing - II
Course
outline
Assignment-10
Introduction and 1) The components of Scalable Core Test Architecture are: 1 point
Modeling
Test Access Mechnism
Modeling and
Synthesis Wrapper
issues
Source and Sink for test stimuli and responses
Architectural All of the above

Synthesis of
Score: 0
Design
All of the above
Temporal Logic 2) Which of the following is FALSE about TAM? 1 point
Model Checking Transports test responses from the CUT to the test sink.
Wider TAM, more I/Os are required.

BDD and
Symbolic Model Loads and executes test instructions.
Checking
Delivers test stimuli from the test source to the CUT.
Introduction to
Digital Testing No, the answer is incorrect.
Score: 0
System Loads and executes test instructions.
Hardware
Testing 3) Which of the following are the valid operating modes of IEEE P 1500 standard? 1 point
Embedded INTEST
System
Hardware XTEST
Testing - II
BYPASS
Testing for © 2014 NPTEL - Privacy & Terms - Honor Code - FAQs -
All the above
embedded
cores
Memory Testing Score: 0
Quiz : Accepted Answers: Funded by

Assignment-10 All the above

4) Which of the following

Powered byis FALSE about the WIR circuitry of the P1500 Wrapper 1 point
Advances in architecture?
Embedded
System
Hardware Loads and executes test instructions
Testing
Configures the operation of the wrapper
Advances in Consists of boundary scan cells (BSCs)

Embedded
System Decodes loaded instructions
Hardware
Testing - II
Score: 0
Testing for Accepted Answers:

Embedded Consists of boundary scan cells (BSCs)
Software
Systems 5) The state transition diagram shown in the below figure corresponds to which fault in a 1 point
memory?
Stuck at one in a memory cell
Stuck at zero in a memory cell
Up transition fault in a memory cell
Down transition fault in a memory cell

Score: 0
Accepted Answers:
6) The state transition diagram shown in the below figure corresponds to which fault in a 1 point
memory?
Stuck at zero in a memory cell
Stuck at one in a memory cell

Score: 0

Accepted Answers:
7) From the context of memory testing, the types of faults considered in address decoder are: 1 point
No address can access a certain cell
With a particular address, multiple cells are simultaneously accessed
A particular cell can be accessed with multiple addresses
All of the above

Score: 0
Accepted Answers:
All of the above
8) March Test is most appropriate for? 1 point
Testing Combinational circuits
Testing memory
Testing Sequential circuits
All of the above

Score: 0
Accepted Answers:
Testing memory
9) The bridging faults <0,0|0,0>,<0,1|1,1>,<1,0|1,1>,<1,1|1,1> are? 1 point
AND Bridging faults
OR Bridging faults
Both b & c
None of the above

Score: 0
Accepted Answers:
OR Bridging faults
Previous Page End


Unit 12 -
Advances in Embedded System Hardware Testing
Course
outline
Assignment-11
Introduction and 1) Which of the following is TRUE about Delay faults? 1 point
Modeling
Stuck-at fault model generally do not verify the timing correctness
Modeling and
Synthesis Real time embedded systems require path delay fault models to test the delay faults
issues
For high speed circuits stuck-at fault model do not cover much delay faults.
Architectural All of the above

Synthesis of
Score: 0
Design
All of the above
Temporal Logic 2) When do delay faults occurs in a combinational circuit? 1 point
Model Checking Clock period > the propagation delay of all paths
Propagation delay of a combinational path > Clock Period

BDD and
Symbolic Model Clock Period > Propagation delay of a combinational path
Checking
None of the above
Introduction to
Score: 0
System Propagation delay of a combinational path > Clock Period
Hardware
Testing 3) Only for a few characteristic polynomials the LFSR is maximal length; such polynomials are 1 point
called:
Embedded
System
Non-primitive polynomials
Hardware
Testing - II Primitive polynomials
© 2014Exhaustive
NPTEL - Privacy & Terms - Honor Code - FAQs -
polynomials
Advances in
A project of
Embedded In association with
Implicit polynomials
System
Testing
Score: 0
Funded by
Testing for Accepted Answers:

Advanced Primitive polynomials

Powered by
Faults in Real
time Embedded 4) Consider a modular LFSR shown below. What is the characteristic function f(x) for the 1 point
Systems circuit?
BIST for
Embedded
Systems
Quiz :
Assignment-11
Advances in
Embedded
System
Hardware 1+x
Testing - II
1 + x + x4
Testing for
1 + x3 + x4
Embedded
Software 1 + x2 + x3
Systems
Score: 0
Accepted Answers:
1 + x3 + x4
5) Consider a circuit representation below of a 3-input Linear feedback shift register (LFSR). 1 point
What is the characteristic polynomial f(x) of the LFSR?
1+x
1 + x2 + x3
1 + x + x2
None of the above

Score: 0
Accepted Answers:
1 + x2 + x3
6) Inertial delay of a gate depends on: 1 point
input rise or fall times
input capacitance
device characteristics
All of the above

Score: 0

Accepted Answers:
All of the above
7) Which of the following is not a component for Built-in self-test(BIST)? 1 point
Hardware test pattern generator
Output response compactor
Set and Reset by Shift Register
Test Controller

Score: 0
Accepted Answers:
Set and Reset by Shift Register
8) In BIST, which of the following component does the lossy compression of the outputs of the 1 point
CUT?
Input Mux
Comparator
Test Controller

Score: 0
Accepted Answers:
9) ____of BIST generates the test patterns required to sensitize the faults and propagate the 1 point
effect to the outputs.
Hardware Test Patter Generator
Output Response Compactor
Comparator
Test Controller

Score: 0
Accepted Answers:
Hardware Test Patter Generator
Previous Page End


Unit 14 -
Testing for Embedded Software Systems
Course
outline
Assignment-12
Introduction and 1) Which of the following (X,Y) belongs to Unordered Codes? 1 point
Modeling
X = 10001, Y = 10000
Modeling and
Synthesis X = 11001, Y = 11000
issues
X = 11000, Y = 00000
Architectural X = 11000, Y = 10001

Synthesis of
Score: 0
Design
X = 11000, Y = 10001
Temporal Logic 2) Which of the following codes can detect unidirectional errors? 1 point
Model Checking X = 11000, Y = 00000
X = 11000, Y = 10001
BDD and
Symbolic Model X = 10001, Y = 10000
Checking
X = 11001, Y = 11000
Introduction to
Score: 0
System X = 11000, Y = 10001
Hardware
Testing 3) Which of the following is TRUE about online BIST? 1 point
Embedded Not an efficient technique for OLT because present day circuits have parallelism and
System
pipelining techniques for high utilization of its modules
Hardware
Testing - II Test length has to be minimum, so as to fit within the idle time available
Funded by

All of the above

Powered by
Advances in
Embedded 4) A ____ can be configured to realize any possible combinational output for a given number 1 point
System
of inputs.
Hardware
Testing - II
CLB
Testing for IOB
Embedded
Software LUT
Systems
None of the above
Testing for
Reprogrammable No, the answer is incorrect.
hardware Score: 0
Interaction Accepted Answers:

Testing LUT
between
Hardware and 5) Which of the following is TRUE about Virtual Machines? 1 point
Software
Developer can treat it as the real machine
Quiz :
Assignment-12 A software layer very close to the hardware that hides the hardware’s details and provides an
abstract view to the programmer
Operating systems are often viewed as virtual machines
All of the above

Score: 0
Accepted Answers:
All of the above
6) Which of the following is correct about the current software/hardware design process? 1 point
Hardware problems can be fixed with simple software modifications
Once operational, software rarely needs modification or maintenance
Valid and complete software requirements are easy to state and implement in code
Hardware and software cannot be acquired separately and independently, with their
successful and easy integration

Score: 0
Accepted Answers:
Hardware and software cannot be acquired separately and independently, with their successful and easy
integration
7) Which of the following is TRUE about the duplication schemes for online testing? 1 point
The circuit duplication is for crosschecking the output responses for Similarity
In identical duplication, circuits are structurally equivalent
In partial duplication, a minimized version of the circuit under test is replicated.
All of the above

Score: 0
Accepted Answers:
All of the above
8) Which of the following is TRUE about online testing techniques? 1 point
Self checking design using error detecting codes is non-intrusive

The hardware overhead for duplication schemes for On-line Testing does not exceed 100%
On-line BIST depends on the idle time of the modules
All of the above

Score: 0
Accepted Answers:
On-line BIST depends on the idle time of the modules
9) The components to be tested in FPGA testing are: 1 point
CLB
I/O Pins
Interconnect Networks
All of the above

Score: 0
Accepted Answers:
All of the above
Previous Page End

Operating Systems/Real-time OS and Micro controllers Multiple Choice Questions
Multiple Choice Questions

8.1 Identify which of these are real-time applications scenarios:
a. An on-line bus ticketing system
b. Printing of annual report of a company’s annual report
c. Reconciling a day’s transactions in an account book of a small company
d. An aircrafts’ yaw control system
8.2 Identify the category of the following real-time systems as “hard, soft or firm”
a. An on-line celebrity cricket bat auction SOFT
b. A patient monitoring system in an ICU FIRM
c. A library book reservation system SOFT
d. A bank’s credit card defaulters notice generation program HARD
8.3 Which of the following describes the RTOS design philiosophy best
a. Maximize the throughput of the system
b. Maximize the processor utilization
e. Minimizing the response time
c. Response within certain stipulated time period
8.4 Which of the following are commercially claimed RTOSs
a. Linux
b. Windows CE
c. Mindows NT
d. Vx works
e. Sun Solaris
8.5 Scheduling of tasks is a very important consideration in RTOS. Which of the
following best described the scheduling policy design:
a. The scheduler must follow a pre-emptive policy
b. The scheduler must not use pre-emptive policy option
c. The scheduler must not only use pre-emptive policy options with the
priority considerations.
d. The scheduler must not use pre-emptive policy option, but must employ
priority consideration.
8.6 Keeping a task’s schedulability in mind, which way a task may be scheduled:
P.C.P.Bhat/IISc Bangalore M8/V1/June 04/1
Operating Systems/Real-time OS and Micro controllers Multiple Choice Questions
a. The task has a predetermined time after which it may be scheduled.

b. The task has a predetermined time before which it may be scheduled
c. The task has a predetermined time interval during which it must be
scheduled any time.
d. The task start has a worst case delay estimate before which it must be
scheduled.
8.7 Describe which of these scheduling policies is most suited for controlling a set of
periodic tasks.
a. FCFS
b. Least laxity first
c. Earliest dead line first
d. Rate monotonic policy schedule
8.8 Which of the following strategy is employed for overcoming the priority
inversion problem?
a. Abandon the notion of priorities altogether
b. Have only two priority levels
c. Allow for temporarily raising the priority of lower level priority process
d. Use pre-emptive policies strictly based on priorities
8.9 Is it true that, in general, in an embedded system the application tasks have higher
priority than system tasks?
a. Yes
b. No
8.10 Where are the device drivers located in RTOSs with a microkernel:
a. In the kernel space
b. In the user space
c. In separately allocated space which is neither kernel space nor user space.
P.C.P.Bhat/IISc Bangalore M8/V1/June 04/2
UNIT 4 & UNIT 5 PART-A MCQ
1. What is the first stage of the compilation process?

a) pre-processing
b) post-processing
c) compilation
d) linking
2. Which of the following produces an assembler file in the compilation process?

a) pre-processor
b) assembler
c) compiler
d) post-processing
3. Which of the following processes the source code before it goes to the compiler?
a) compiler
b) simulator
c) pre-processor
d) emulator
4. Which file is converted to an object file?

a) hex file
b) decoded file
c) coded file
d) assembly file
5.. Which of the following allows the programmer to define constants?

a) pre-processor
b) compiler
c) emulator
d) debugger
6.. Time duration required for scheduling dispatcher to stop one process and start
another is known as ____________
a) process latency
b) dispatch latency
c) execution latency
d) interrupt latency
7. In real time operating system ____________

a) all processes have the same priority
b) a task must be serviced by its deadline period
c) process scheduling can be done only once
d) kernel is not required
8. For real time operating systems, interrupt latency should be ____________
a) minimal
b) maximum
c) zero
d) dependent on the scheduling
9. Time required to synchronous switch from the context of one thread to the context of
another thread is called?
a) threads fly-back time
b) jitter
c) context switch time
d) none of the mentioned
10. In a real time system the computer results ____________

a) must be produced within a specific deadline period
b) may be produced at any time
c) may be correct
d) all of the mentioned
UNIT 4 & UNIT 5 PART-B MCQ
1. What are the two major sections in a coprocessor?

a) control unit
b) numeric control unit
c) floating point unit
d) Integer unit
2. Name the processor which helps in floating point calculations.

a) microprocessor
b) microcontroller
c) coprocessor
d) controller
3. How are negative numbers stored in a coprocessor?

a) 1’s complement
b) 2’s complement
c) decimal
d) gray
4. What are the stages included in pipelining
a)fetch
b)throughput
c)decode
d)execute
5.Which one of the following is a real time operating system?
a) RTLinux
b) VxWorks
c) Windows CE
d) Android
6.Antilock brake systems, flight management systems, pacemakers are examples of

____________
a) safety critical system
b) hard real time system
c) soft real time system
d) none of the above
7. Some of the properties of real time systems include ____________

a) single purpose
b) inexpensively mass produced
c) small size
d) none of the above
8. Memory management units ____________

a) increase the cost of the system
b) increase the power consumption of the system
c) increase the time required to complete an operation
9. The switching of the CPU from one process or thread to another is called
____________
a) process switch
b) task switch
c) context switch
10. Which of the following statements are true?
I. Shortest remaining time first scheduling may cause starvation
II. Preemptive scheduling may cause starvation
III. Round robin is better than FCFS in terms of response time
a) I only
b) I and III only
c) II and III only
d) I, II and III
11.The Assemblers have the following major tasks
a) generate binary for symbolic instructions
b) translate labels into addresses
c) handle pseudo-ops
d) generate one to multiple translation
12. The basic compilation phases are
a) HLL
b) symbol Table , Optimization
c) Assembly
d) encryption
13. The classification of RTOS are
a) settling real -time
b) hard real - time
c) firm real – time
d) soft real –time

EXTRA
Unit-4 PART-A

a) microprocessor
b) microcontroller
c) coprocessor
d) controller

a) 1’s complement
b) 2’s complement
c) decimal
d) gray
3. What is 80/20 rule?

a) 80% instruction is generated and 20% instruction is executed
b) 80% instruction is executed and 20% instruction is generated
c) 80%instruction is executed and 20% instruction is not executed
d) 80% instruction is generated and 20% instructions are not generated
4. How is memory accessed in RISC architecture?

a) load and store instruction
b) opcode instruction
c) memory instruction
d) bus instruction
5. What type of error occurs in the refresh cycle of the DRAM?

a) errors in data
b) power loss
c) timing issues
d) not accessing data
UNIT-5 PART-A
1. Which of the following statements are true?
a) I only
b) I and III only
c) II and III only
d) I, II and III
2. VxWorks is centered around ____________
a) wind microkernel
b) linux kernel
c) unix kernel
d) ATMEL
3. If a process fails, most operating system write the error information to a ______
a) log file
b) another running process
c) new file
d) memory
4. Which facility dynamically adds probes to a running system, both in user processes
and in the kernel?
a) DTrace
b) DLocate
c) DMap
d) DAdd
5. Which system call can be used by a parent process to determine the termination of
child process?
a) wait
b) exit
c) fork
d) get
6. The address of the next instruction to be executed by the current process is provided
by the __________
a) CPU registers
b) Program counter
c) Process stack
d) Pipe
7. Which of the following do not belong to queues for processes?

a) Job Queue
b) PCB queue
c) Device Queue
d) Ready Queue
8. When the process issues an I/O request __________

a) It is placed in an I/O queue
b) It is placed in a waiting queue
c) It is placed in the ready queue
d) It is placed in the Job queue
UNIT-4 PART-B
1. What are the essential tight constraint/s related to the design metrics of an
embedded system?
a. Ability to fit on a single chip

b. Low power consumption
c. Fast data processing for real-time operations
d. high power consumption
2. Which characteristics of an embedded system exhibit the responsiveness to

the assortments or variations in system's environment by computing specific
results for real-time applications without any kind of postponement ?
a. Single-functioned Characteristic
b. Tightly-constraint Characteristics
c. Reactive time Characteristics
d.real time characteristics
3. Which of the following is the design in which both the hardware and software are
considered during the design?
a) platform based design
b) memory based design
c) software code design
d) hardware code design
4. Which design activity is in charge of mapping operations to hardware?

a) scheduling
b) high-level transformation
c) hardware partitioning
d) software partitioning
5. Which level simulates the algorithms that are not used within the embedded
systems?
a) gate level
b) circuit level
c) switch level
d) algorithmic level
UNIT-5 PART-B
1.In Operating Systems, which of the following is/are CPU scheduling algorithms?
a) Round Robin
b) Shortest Job First
c) Priority
d) CACHE
2. Which one of the following error will be handle by the operating system?
a) power failure
b) lack of paper in printer
c) connection failure in the network
d) booting
3. Process synchronization can be done on __________

a) hardware level
b) software level
c) special architecture
d) memory management
4. A monitor is a module that encapsulates __________

a) shared data structures
b) procedures that operate on shared data structure
c) synchronization between concurrent procedure invocation
d) compressed data
5. Messages sent by a process __________

a) have to be of a fixed size
b) have to be a variable size
c) can be fixed sized
d) can be variable sized
UNIT - IV
1. When comparing PIC16C7x with PIC16C6x, the enhanced capability is_________
a) digital-to-analog
b) analog-to-digital
c) encoding
d) decoding
2. The number of instruction set that the PIC microcontroller has is ________
a) 35 b) 34 c) 31 d) 45
3. The PIC microcontroller family uses which architecture?
a) Harward b) Von-Neumann c) Array d) Pipelining
4. In PIC microcontroller, group of locations of memory are termed as _________, which can be
accessed through various instruction.
a) Register find b) Register file c) Register Locate d) Register Identify
5. In the PIC microcontroller, the register bank which has 32 bytes of special purpose registers is
______
a) Bank 0 &1 b) Bank 1 & 2 c) Bank 0 & 2 d) Bank 0, 1 & 2
6. In PIC microcontroller, The W register serves the purpose similar to ________ of 8085
microprocessors.
a) Program counter b) Instruction register c) Accumulator d) ISR
7. In PIC microcontroller, the watchdog timer can be cleared using the instruction _________
a) clcwd b) clrwdt c) clrwd d) wdtclr
8. What is the length of PCLATH?
a) 13 b) 8 c) 5 d) 4
9. The RP0 bit in PIC microcontroller is in ________ register.
a) Flag b) Status c) FSR d) INDF
10. In PIC microcontroller, if there is any carry from lower nibble to higher nibble ________ bit of
STATUS register becomes set.
a) AC b) CY c) DC d) OV
11. Identify the instruction of PIC which increment f, putting result in F or W is ________
a) inrf f,F(W) b) incf f,F(W) c) inf f,F(W) d) inxf f,F(W)
12. The instruction addlw of PIC microcontroller affects the ______ status bits.
a) C, DC, Z b) C, Z c) C, AC, Z d) C, DC
13. The instruction of PIC16Cxx that tests the ‘b’ bit of ‘f’ register, where b = 0 to 7 and skip when it
clear is ________
a) btfss b) btfsc c) btccc d) btsss
14. Identify the correct instruction of PIC which AND literal value into W from the following
a) andlw b) andwf c)andff d)andwl
15. In PIC16Cxx, return from ISR; reenabling interrupts is being done by _______ instruction.
a) return b) retlw c) retfie d) retei
16. The PIC16C7x has ________ I/O Ports
a) 5 b) 6 c) 4 d) 0
17. Setting the TRISB of PIC16F877 microcontroller will make the respective port pin as ______ pin
a) output b) input c) toggle d) reset
18. The 28 pin and 40 pin PIC microcontrollers have ______ number of I/O ports respectively.
a) 3 & 5 b) 4 & 8 c) 6 & 12 d) 2 & 6
19. In PIC microcontroller, GIE stands for __________
a) Gain input enable b) Gain interrupt enable
c) Global interrupt enable d) Global input enable
20. The alternate use of PORT D I/O pins of PIC16C7x is ________
a) Serial ports; Timer I/O b) A/D converter inputs
c) Parallel slave port d) External interrupt
21. Which of the following PIC microcontroller has two CCP module in it?
a) PIC16C62A b) PIC16C64A c) PIC16C72 d) PIC16C74A
22. In CCP module of PIC microcontroller, P denotes ________
a) Parity b) PAL c) PWM d) Priority
23. The TMR1 cannot be stopped and changed when it is used for ___________ function.
a) compare b) capture
c) compare and capture d) PWM
24. In PIC, the time of occurrence of an input edge is determined by combination of ________
a) Timer 1 and CCP1 b) Timer 2 and CCP2
b) Timer 1, CCP1 and CCP2 d) Timer 1 and either of CCP1 or CCP2
25. In PIC Microcontroller, the period of PWM is controlled by _________
a) Timer1 prescaler and PR1 b) Timer2 prescaler and PR2
b) Timer0 prescaler and PR2 d) Timer0 prescaler and PR1
26. The PIC16C6x/7x has _________ program counter.
a) 8 bit b) 11 bit c) 12 bit d) 13 bit
27. In PIC Microcontroller, to enable the program memory from 2k to 4k, which of the following is
to be made?
a) PCLATH.3=1 b) PCLATH.1=1 c) PCLATH.2=1 d) PCLATH.4=1
28. In PIC Microcontroller, the NOT_TO and NOT_PD are bits available in _______ register.
a) FSR b) INDF c) STATUS d) PCLATH
29. The status of ________ bit can be used to identify and convert the result obtained into a BCD.
a) C b) DC c) Z d) AC
30. Which of the following is not the bit of STATUS register?
a) DC b) C d) RP0 d) FSR
31. Identify the correct simpler assembler process
a) code.asm converted to code.hex converted to MCU
b) code.hex converted to code.asm converted to MCU
c) code.oct converted to code.hex converted to MCU
d) code.hex converted to MCU
32. In PIC microcontroller, which of the following is not the file structure of IDE?
a) project_name.mcp b) project.name.mcw c) project.name.mcs d) project.name.mcc
33. In half drive mode of operation of stepper motor, how the phases are energized?
a) one and two phases simultaneously b) one and two phases alternatively
b) two and three phases simultaneously d) two and three phases alternatively
34. Which mode of stepper motor operation is suitable for better power consumption?
a) Full Drive b) Wave Drive c) Half Drive d) Quarter Drive
35. When two stator electromagnets are energized at a time, the mode is called _________
a) Full Drive b) Wave Drive c) Half Drive d) Quarter Drive
36. In wave drive operation of stepper motor, ________ is less when compared to full step drive.
a) current b) voltage c) torque d) speed
37. What are the special features available in PIC microcontroller for speed control of DC motor?
a) PWM generation and analog channel b) PWM generation and ADC
c) ADC and analog channel d) PWM generation and DAC
38. When we are using the PWM controller IC’s, the error% in frequency will be _______
a) 3-5% b) 1-2% c) 0-1% d) 3-4%
39. The pulse width modulator method that can be used for PIC controlled DC motor is __________
a) analog b) digital c) analog and digital d) programming
40. When interfacing the DC motor with PIC microcontroller, the back emf of the motor can avoided
by _________
a) H bridge b) Large inductance c) T bridge d) Small inductance
41. ________ uses the combination of PIC microcontroller and a DAC.
a) Waveform generator b) Sinusoidal generator
c) PWM generator d) Attenuator
42. The modification of frequency and amplitude of the generated waveform using PIC
microcontroller is achieved by ________
a) changing the programming b) changing carrier wave
b) changing the input parameters d) changing the controller
43. R/2R resistor ladder network which is used in waveform generator is a ________
a) decoder b) ADC c) DAC d) multiplier
44. The frequency counter design using PIC microcontroller needs ________
a) Timer 0 and Timer 1 b) Timer 0 alone c) Timer 1 alone d) ADC
45. In PIC microcontroller, for a 16 bit counter the maximum measurable frequency range is _______
a) 0-65k b) 0-24k c) 0-30k d) 0-70k
46. The frequency counter’s maximum range can be defined by ________
a) counter length b) setting it the program
b) tuning the analog circuit components d) setting the oscillator frequency
47. In PIC microcontroller, Real time clock design can be used for __________ application
a) Data logging b) Process monitoring
c) Interrupt handling d) Rebooting
48. Inter integrated circuit protocol used in __________ of PIC microcontroller.
a) RTC b) Waveform generator c) PWM d) Counter
49. Programmable gate pulse to the switches using PIC microcontroller has _________
a) a drawback that frequency cannot be varied
b) a wide range of control over frequency
c) limited frequency variation
d) a fixed frequency of operation
50. By using the feedback provided, control of abnormality of power switches is possible in ______
a) programmed gate pulse b) SPWM gate pulse
b) RPWM gate pulse d) floating gate pulse
51. In PIC microcontroller, the instruction fetched from successive addresses like n, n+1, n+2, n+3
and soon. When the goto address location is executed after n+1, the program counter content will
have _________
a) n+2 b) New Address c) Old Address d) n+3
52. In PIC microcontroller, under indirect addressing mode, the full 8 bit register file address is
written first into _______
a) INDF b) FSR c) PCLATH d)RP0
53. In PIC microcontroller, the program counter comprises of _____ bit PCL and ______ bit
PCLATH.
a) 4, 8 b) 8, 5 c) 5, 8 d) 8, 4
54. In PIC microcontroller, copy the content of f in either F or W and then rotate F or W right
through carry operation is executed by ______ instruction.
a) rrf b) rfr c)rff d) rfc
55. In PIC microcontroller, What is the operation of btfss STATUS,z instruction?
a) test Z bit of STATUS and will skip to next instruction if the bit is reset
b) test Z bit of STATUS and will skip to next instruction if the bit is set
c) test Z bit of STATUS and will go to next instruction if the bit is reset
d) test Z bit of STATUS and will go to next instruction if the bit is set
56. In PIC microcontroller, which of the following instruction complement f and putting the result in
F or W?
a) compf f,F(W) b) comf f,F(W) c) cmpf f,F(W) d) cpf f,F(W)
57. In PIC microcontroller, the W register can be using the instruction _______
a) clear w b) clrf w c) clrw d) clr w
58. In PIC microcontroller, which of the following instruction doesn’t take more than 1 cycle for
operation on any condition?
a) goto b) call c) btfss d) rlf
59. The instruction clrw of PIC microcontroller affects the ______ status bit(s).
a) C, DC, Z b) Z c) C, AC, Z d) C, DC
60. In PIC microcontroller, which instruction will wait for watchdog timer or external signal to begin
program execution again?
a) nop b) sleep c) resume d) clrwdt
61. In PIC microcontroller, the instruction used to set a particular bit of register is ________
a) bcf f,b b) bsf f,b c) bss f,b d) bff f,b
62. In PIC microcontroller, what is the 6th bit of STATUS register?
a) 0 b) Z c) DC d) C
63. In PIC microcontroller, the ________ accesses the location pointed by FSR.
a) PCLATH b) INDF c) PCL d) W
64. In PIC microcontroller, the instruction bcf STATUS,RP0 is used to ______
a) Select Bank 1 b) Select Bank 0 c) Reset Bank 1 d) Reset Bank 0
65. In PIC microcontroller, the number of levels of stack available is ________
a) 4 b) 8 c) 16 d) 32
UNIT – V
1. RISC processors were designed for _______
A. Main computer
B. Mini computer
C. Mobile system
D. supercomputer
ANSWER: C
2. ARM processor is a----- device
A. 8 bit
B. 16 bit
C. 4 bit
D. 32 bit
ANSWER: D
3. Expansion of RISC is _________
A. Restricted Instruction Sequencing Computer
B. Restricted Instruction Sequential Compiler
C. Reduced Instruction Set Computer
D. Reduced Induction sequential Computer
ANSWER: C
4. The program counter is implemented using ------------ in the ARM processor
A. Caches
B. Heaps
C. General purpose register
D. special purpose register
ANSWER: C
5. ARM machine instructions are encoded with ------word
A. 2 byte
B. 3 byte
C. 8 byte
D. 4 byte
ANSWER: D
6. The first ARM processor was developed at -------computers
A. Acorn
B. Intel
C. Microchip
D. Atmel
ANSWER: A
7. The ARM instruction set features
A. 5- address register instruction
B. load store architecture
C. load and store single register
D. shift and ALU operations a multiple instruction
ANSWER: B
8. Thumb instructions are used to access the ----.
A. Current program status register
B. stack pointer
C. program counter
D. addresss bus
ANSWER: A
9. ENTRY directive specifies the ------ of the execution.
A. Start
B. End
C. Main
D. Return
ANSWER: A
10. The -----------is used to switch fast and to perform better in ARM
processor.
A. Switching circuit
B. Barrel shifter circuit
C. Integrated circuit
D. Multiplexer circuit
ANSWER: A
11. Which instructions are used in ARM processor to load or store multiple operands?
A. Banked instructions
B. Lump transfer instructions
C. Block transfer instructions
D. DMA instructions
ANSWER: C
12. The main importance of ARM processor is to provide
A. low cost and low power consumption
B. High degree of multitasking
C. Efficient memory management
D. less error
ANSWER: A
13. What is the nature of instruction size in RISC processors?
A. register based
B. variable
C. time to refine
D. Unpredictable
ANSWER: A
14. How many address lines are there in ARM processor?
A. 24
B. 32
C. 16
D. 64
ANSWER: B
15. In pipelining, before decode, data is
A. fetched
B. execute
C. initialized
D. deleted
ANSWER: A
16. The Thumb instruction set is a subset of the most commonly used ----ARM instructions.
A. 32 bit
B. 24 bit
C. 16 bit
D. 64 bit
ANSWER: A
17. CPSR stands for-------
A. current program status Register
B. carry program sub-register
C. clock power status register
D. current program saved register
ANSWER: A
18. The ARM processor has --------operating modes
A. 2
B. 4
C. 6
D. 8
ANSWER: C
19. The ARM has ____sets of instructions which interact with main memory
A. 1
B. 2
C. 3
D. 4
ANSWER: C
20. A --------------define the current limits of the stack in ARM processor
A. stack pointer
B. data pointer
C. program counter
D. offset pointer
ANSWER: A
21. The thumb code requires------------of the space of the ARM code
A. 40%
B. 50%
C. 70%
D. 100%
ANSWER: C
22. In order to easily add system features like caches and memory timing characteristics ____ is
designed
A. ARMulator
B. AMBA Bus
C. System bus
D. ARM Memory interface
ANSWER: A
23. ARM processor with Cortex-M0 core has a clock generator with ____ clock sources
A. 4
B. 5
C. 3
D. 6
ANSWER: B
24. ____ is not a valid ARM Instruction
A. MUL
B. MLA
C. LDR
D. MVI
ANSWER: D
25. Identify which of the below is not the addressing mode of ARM processor?
A. Immediate addressing
B. Implied addressing
C. Register addressing
D. Base plus index addressing
ANSWER: B
26. Which of the below mentioned code is not the condition code flag of ARM processor?
A. N
B. C
C. Z
D. OV
ANSWER: D
27. In ARM processor, when two 32 bit integers are multiplied, the result obtained is ______
A. 24 bit
B. 26 bit
C. 27 bit
D. 28 bit
ANSWER: B
28. The register used to store the condition code bits in ARM processor is _________
A. APSR
B. CPSR
C. PC
D. r12
ANSWER: B
29. ARM Processor does not support _______ operations.
A. memory to register
B. register to register
C. memory to memory
D. register to memory
ANSWER: C
30. Which of the following category is not the ARM instructions comes under?
A. Data processing instructions
B. Memory handling instructions
C. Data transfer instructions
D. Control flow instructions
ANSWER: B
31. ARM means _____________
A. Advanced RISC Machines
B. Advanced Rate Machines
C. Advance Running Machines
D. Artificial Running Machines
ANSWER: A
32. With 32-bit memory, the ARM code is-------faster than thumb code
A. 40%
B. 45%
C. 30%
D. 20%
ANSWER: A
33. ARM processor supports ___________ address system
A. Little Endian
B. Big Endian
C. X-Little Endian
D. Both Little & Big Endian
ANSWER: D
34. Throughput means
A. One instruction per cycle
B. Three cycles per instruction
C. Two instructions per cycle
D. Average number of clock cycles per instruction
ANSWER: A
35. Identify the available stages in 3-stage pipeline
A. Decode, Write-back, and Fetch
B. Execute, Decode and Fetch
C. Fetch, execute and buffer
D. Decode, execute and buffer
ANSWER: B
36. The hardware system prototyping tools are NOT related to
A. Rapid silicon prototyping
B. AMBA
C. Providing a platform for system verification and software development
D. ARM integrator
ANSWER:
37. The ARM code can be evaluated and debugged without the processor chip using ARMulator
which is a _________
A. Hardware emulator
B. Software emulator
C. Firmware emulator
D. Interrupt emulator
ANSWER: B
38. Which instruction of ARM processor did not give any carry at the output of arithmetic operation?
A. BVS
B. BGT
C. BCC
D. BCS
ANSWER: C
39. In ARM Processor, the result of product of two register content can be added to another register
content is done by the instruction ________
A. MUL
B. MULA
C. MLA
D. MUA
ANSWER: C
40. NUC140 processor does not consist
A. More than two timers
B. Real time clock
C. Brown out reset
D. 16-bit ADC
ANSWER: D
41. Which of the following is NOT true related to the nuvoTon –NU-LB-NUC140 processor
A. An ARM based 32-bit microcontroller
B. It is using ARM9 cpu core
C. having SRAM
D. It uses Thumb instruction set
ANSWER: B
42. In nuvoTon –NU-LB-NUC140 architecture, ‘1’ and ‘4’ represent ____ and ___ repectively
A. CPU core and Function
B. CPU core and RAM size
C. Function and CPU core
D. RAM size and Function
ANSWER:
43. Which of the following ARM processor is fastest?
A. Cortex-A processors
B. Cortex-M processors
C. ARM9E series
D. ARM64FX.
ANSWER: D
44. How many registers are available in arm processor?
A. 54
B. 45
C. 47
D. 37
ANSWER: D
45. ARM7 is a --------------- ARM processor
A. 32- bit
B. 8-bit
C. 16-bit
D. 64-bit
ANSWER: A
46. Which of the following interrupt input is level sensitive and maskable?
A. FIQ
B. IPR
C. IR
D. IIS
ANSWER: A
47. Which modelling presents signals at the correct time within a cycle, allowing logic delays to be
accounted for?
A. Instruction accurate modelling
B. Cycle accurate modelling
C. Time accurate modelling
D. System accurate modelling
ANSWER: C
48. Which of the following is not the instruction of ARM processor?
A. ADC
B. ADD
C. ORR
D. ANL
ANSWER: D
49. Which of the following statements are false?
(1) ARM processor with 3-stage pipeline has A bus and B bus
(2) Barrel shifter is connected to B bus
a. (1) alone is false

b. (2) alone is false
c. Both (1) and (2) are false
d. Neither (1) nor (2)
ANSWER: D
50. Which of the following statements are true with respect to ALU bus in 3-stage pipeline of ARM
organization?
(1) It is connected between Register bank and address register
(2) It is connected between B bus and ALU
e. (1) alone is true

f. (2) alone is true
g. Both (1) and (2) are true
h. Neither (1) nor (2)
ANSWER: A
51. Executing ADD ro,r1,r2 instruction using ARM processor will
i. Add the contents of registers r0 and r2 , then stores result in r0
j. Add the contents of registers r1 and r0 , then stores result in r2
k. Add the contents of registers r1 and r2 , then stores result in r0
l. Add the contents of registers r1 and r2 , then stores result in r1
ANSWER: C
52. MVN and MOV instructions in ARM are
m. 8-bit instructions
n. Register movement instructions
o. Not used to transfer data between registers
p. 8-bit instructions
ANSWER: B
53. LSL and MLA instructions are used to ____ and _____
q. Load store logic, Multiply and accumulate
r. Logical shift left, Multiply with accumulator
s. Logical store logic, Multiply and accumulate
t. Logical shift left, Multiply and accumulate
ANSWER: D
54. Identify the instruction based on the figure shown.
A. LSR
B. LSL
C. ASL
D. ASR
ANSWER: B
55. In ARM Processor, What is the operation of the instruction ADR r1, TABLE1?
A. Copies the r1 content to Table1
B. Causes r1 to contain address of data that follows Table1
C. Copies the r1 with content of Table1
D. Causes r1 to contain address of Table1
ANSWER: B
56. Identify the instruction which transfers data to multiple registers at a time in ARM processor.
A. LDIMR r2, { r1, r3, r5 }
B. LDA r2, { r1, r3, r5 }
C. LDMIA r1, { r0, r2, r5 }
D. LDM r1, { r0, r2, r5 }
ANSWER: C
57. The ARM processor has how many general purpose registers?
A. r0 to r14
B. r0 to r15
C. r0 to r7
D. r0 to r31
ANSWER: A
58. How many write and read ports does the PC of ARM processor has?
A. 1 and 3 respectively
B. 2 and 3 respectively
C. 1 and 2 respectively
D. 2 and 4 respectively
ANSWER: B
59. Which of the following has the highest exception priority?
A. FIQ
B. IRQ
C. Reset
D. Prefetch abort
ANSWER: C
60. The S and H bits of binary encoding in ARM processor defines ________
A. type of source
B. type of destination
C. type of operand
D. type of error
ANSWER: C
1. How many clock pulses are confined by each machine cycle of Peripheral-Interface Controllers?
a. 4
b. 8
c. 12
d. 16
ANSWER: (a) 4
2) Which flags are more likely to get affected in status registers by Arithmetic and Logical Unit (ALU) of
PIC 16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
ANSWER: (d) All of the above
3) What is the execution speed of instructions in PIC especially while operating at the maximum value of
clock rate?
a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs
ANSWER: (b) 0.2 μs
4) Which operational feature of PIC allows it to reset especially when the power supply drops the
voltage below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above
ANSWER: (b)Brown-out reset
5) Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program memory
d. All of the above
6) Which among the below specified major functionalities is/are associated with the programmable
timers of PIC?
a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs
a. Only C
b. C & D
c. A, B & D
d. A, B & C
ANSWER: (d) A, B & C
7) Which timer/s possess an ability to prevent an endless loop hanging condition of PIC along with its
own on-chip RC oscillator by contributing to its reliable operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
ANSWER: (c) Watchdog Timer (WDT)
8) Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
ANSWER: (b) Program Counter Latch (PCLATH) Register
9) Which register/s is/are mandatory to get loaded at the beginning before loading or transferring the
contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
ANSWER: (a) W
10) How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
ANSWER: (a) 1
11) The RPO status register bit has the potential to determine the effective address of______
a. Direct Addressing Mode
b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
ANSWER: (a) Direct Addressing Mode
12) Which status bits exhibit carry from lower 4 bits during 8-bit addition and are especially beneficial
for BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
ANSWER: (b) Digits Carry bit (DC)
13) Which statement is precise in relation to FSR, INDF and indirect addressing mode?
a. Address byte must be written in FSR before executing INDF instruction in indirect addressing mode
b. Address byte must be written in FSR after executing INDF instruction in indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF instruction in indirect
addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in indirect addressing
mode
a. Only A
b. Only B
c. Only A & B
d. A & D
ANSWER: (a) Only A
14) Which among the below stated registers specify the address reachability within 7 bits of address
independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
15) Where do the contents of PCLATH get transferred in the higher location of program counter while
writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
ANSWER: (c) 13th bit
16) Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
ANSWER:(b) Low
17) Generation of Power-on-reset pulse can occur only after __________
a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
ANSWER: (a) the detection of increment in VDD from 1.5 V to 2.1 V
18) What is the rate of power up delay provided by an oscillator start-up timer while operating at XT,
LP and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
ANSWER: (b) 1024 cycles
19) Which kind of mode is favourable for MCLR pin for indulging in reset operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
ANSWER: (b) Sleep mode
20) What is the purpose of using the start-up timers in an oscillator circuit of PIC?
a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
ANSWER: (a) For ensuring the inception and stabilization of an oscillator in a proper manner
21) Which program location is allocated to the program counter by the reset function in Power-on-Reset
(POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
ANSWER: (a) Initial address
22) When does it become very essential to use the external RC components for the reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
ANSWER: (b) Only if VDD power-up slope is insufficient at a requisite level
23) Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a. A & B
b. C & D
c. A & C
d. B & D
ANSWER: (b) C & D
24) Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely unique
and distinct from other microcontrollers?
a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
ANSWER: (a) It can reset the PIC automatically in running condition
25) What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in
PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
ANSWER: (a) CPU resets PIC once again in BOR mode
26) What output is generated by OSC2 pin in PIC oscillator comprising RC components for
sychronizing the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
ANSWER:(c) (1/8) x frequency of OSC1
27) Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock
sources for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
ANSWER: (b) LP (Low-Power Clocking)
28) Which significant feature/s of crystal source contribute/s to its maximum predilection and utility as
compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
ANSWER: (a) All of the above
29) What is the executable frequency range of High speed (HS) clocking method by using cystal/
ceramic/ resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
ANSWER: (d) 4-20 MHz
30) How many bits are required for addressing 2K & 4K program memories of PIC 16C61 respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
ANSWER: (c) 11 & 12 bits
31) What location is attributed to ‘goto Mainline’ instruction in the program memory of PIC 16C61?
a. 000H
b. 004H
c. 001H
d. 011H
ANSWER: (a) 000H
32) When do the special address 004H get automatically loaded into the program counter?
a. After the execution of RESET action in program counter
b. After the execution of ‘goto Mainline ‘ instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
ANSWER: (c) At the occurrence of interrupt into the program counter
33) How many bits are utilized by the instruction of direct addressing mode in order to address the
register files in PIC?
a. 2
b. 5
c. 7
d. 8
ANSWER:(c) 7
34) Which registers are adopted by CPU and peripheral modules so as to control and handle the
operation of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
ANSWER: (c) Special Function Registers
35) Which among the below specified registors are addressable only from bank1 of RFS?
a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)
ANSWER: (a) PORTA (05H)
36) Which register acts as an input-output control as well as data direction register for PORTA in bank
2 of RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)
ANSWER: (c) TRISA (85H)
37) Which bank of RFS has a provision of addressing the status register?
a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2
ANSWER: (c) Either Bank 1 or Bank 2
38) Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the
external interrupt INT?
a. RBPU
b. INTEDG
c. PSA
d. RTS
ANSWER: (b) INTEDG
39) Where are the prescalar assignments applied with a usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
ANSWER: (c) Either RTCC or Watchdog timer
40) Where is the exact specified location of an interrupt flag associated with analog-to-digital converter?
a. INTCON
b. ADCON0
c. ADRES
d. PCLATH
ANSWER: (b) ADCON0
41) Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register?
a. GIE
b. ADIE
c. RBIE
d. TOIE
ANSWER: (a) GIE
42) When does it become possible for a bit to get accessed from bank ‘0’ in the direct addressing mode of
PICs?
a. Only when RPO bit is set ‘zero’
b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict
ANSWER: (a) Only when RPO bit is set ‘zero’
43) When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of ‘interrupt
on change’?
a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs
ANSWER: (a) By configuring all the pins (RB4-RB7) as inputs
44) Which digital operations are performed over the detected mismatch outputs with an intention to
generate a single output RB port change output?
a. OR
b. AND
c. EX-OR
d. NAND
ANSWER: (a) OR
45) What is the purpose of acquiring two different bits from INTCON register for performing any
interrupt operation in PIC 16C61 / 71?
a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
ANSWER: (b) One for enabling the interrupt & one for its occurrence detection
46) Which among the below specified combination of interrupts belong to the category of the PIC 16C61
/ 71?
a. External, Timer/Counter & serial Port Interrupts
b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts
ANSWER: (c) External, Timer 0 & Port B Interrupts
47) Which condition results in setting the GIE bit of INTCON automatically?
a. Execution of retfie instruction at the beginning of ISR
b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit
ANSWER: (b) Execution of retfie instruction at the end of ISR
48) What kind of external edge-sensitive interrupt is generated due to transition effect at pin RBO/INT?
a. INT
b. RBO
c. INTF
d. All of the above
ANSWER:(a) INT
49) Which bit-register pair plays a significant role in configuring the rising or falling edge triggering
levels in external interrupts of PIC 16C61/71?
a. INTF bit – INTCON register
b. INTEDG bit – OPTION register
c. INT bit -INTCON register
d. INTE bit – OPTION register
ANSWER: (b) INTEDG bit – OPTION register
50) Consider the following statements. Which of them is /are incorrect?
a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
c. During the occurrence of interrupt, GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.
a. A & B
b. C & D
c. Only A
d. Only C
ANSWER: (b) C & D
51) What is the purpose of setting TOIE bit in INTCON along with GIE bit?
a. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
ANSWER: (a) For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
52) Where do the conversion interrupt flag (ADIF) end after an accomplishment of analog-to-digital
(ADC) conversion process?
a. INTCON
b. ADCON0
c. OPTION
ANSWER: (b) ADCON0
53) How much time is required for conversion per channel if PIC 16C71 possesses four analog channels,
each comprising of 8-bits?
a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs
ANSWER: (c) 20 μs
54) How much delay is required to synchronize the external clock at TOCKI in Timer ‘0’ of PIC 16C61?
a. 2-cycles
b. 4-cycles
c. 6-cycles
d. 8-cycles
ANSWER: (a) 2-cycles
55) Which command enables the PIC to enter into the power down mode during the operation of
watchdog timer (WDT)?
a. SLEEP
b. RESET
c. STATUS
d. CLR
ANSWER: (a) SLEEP
56) Which channel would be selected if the values of channel bits CHS0 & CHS1 are ‘1’ & ‘0’
respectively in ADC Status Register?
a. AIN0
b. AIN1
c. AIN2
d. AIN3
ANSWER: (c) AIN2
57) Which bit is mandatory to get initiated or set for executing the process of analog to digital
conversion in ADCON0?
a. ADIF
b. ADON
c. Go/!Done
d. ADSC1
ANSWER: (c) Go/!Done
58) What would be the value of ADC clock source, if both the ADC clock bits are selected to be ‘1’?
a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC
ANSWER: (d) FRC
59) The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated by __________
a. PCFG1 & PCG0
b. VREF
c. ADON
d. All of the above
ANSWER: (a) PCFG1 & PCG0
60) Which among the below mentioned aspect issues are supported by capture/compare/PWM modules
corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
61) Which register is suitable for the corresponding count, if the measurement of pulse width is less than
65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
ANSWER: (c) 16-bit register
UNIT-5 -MCQ
Identify which of the below is not the addressing mode of ARM
processor? A. Immediate addressing
B. Implied addressing
C. Register addressing
D. Base plus index addressing
ANSWER: B
Which of the below mentioned code is not the condition code flag of ARM
processor? A. N
B. C
C. Z
D. OV
ANSWER: D
Identify the instruction based on the figure shown.

A. LSR
B. LSL
C. ASL
D. ASR
ANSWER: B
In ARM processor, when two 32 bit integers are multiplied, the result obtained is
______ A. 24 bit
B. 25 bit
C. 27 bit
D. 28 bit
ANSWER: B
In ARM Processor, What is the operation of the instruction ADR r1,

TABLE1? A. Copies the r1 content to Table1
B. Causes r1 to contain address of data that follows Table1
C. Copies the r1 with content of Table1
D. Causes r1 to contain address of Table1
ANSWER: B
Identify the instruction which transfers data to multiple registers at a time in ARM
processor. A. LDIMR r2, { r1, r3, r5 }
B. LDA r2, { r1, r3, r5 }
C. LDMIA r1, { r0, r2, r5 }
D. LDM r1, { r0, r2, r5 }
ANSWER: C
Which instruction of ARM processor did not give any carry at the output of arithmetic
operation?
A. BVS
B. BGT
C. BCC
D. BCS
ANSWER: C
The ARM processor has how many general purpose registers?

A. r0 to r14
B. r0 to r15
C. r0 to r7
D. r0 to r31
ANSWER: A
The register used to store the condition code bits in ARM processor is _________
A. APSR
B. CPSR
C. PC
D. r12
ANSWER: B
In ARM Processor, the result of product of two register content can be added to another register
content is done by the instruction ________
A. MUL
B. MULA
C. MLA
D. MUA
ANSWER: C
ARM stands for _____________.
A. Advanced RISC Microprocessors

B. Advanced RISC Management
C. Advanced RISC Machines
D. Advanced RISC Main frame
ANSWER: C
Instruction in ARM machines is encoded into __________ Word.
A. Two byte
B. Four Byte
C. Eight Byte
D. Six Byte
ANSWER: B
The address space in ARM is ___________
A. 2^8
B. 2^16
C. 2^32
D. 2^64
ANSWER : C
Which of the following is False?
A. The ability to store data in the form of consecutive bytes.

B. These ARM processors are designed for handheld devices.
C. ARM is a type of system architecture.
D. Both A and B
ANSWE : A
__________ is the address that the computer acquires from the current instruction
being executed.
A. Simple Address
B. Complex Address
C. Non-Effective address
D. Effective address
ANSWER: D
The duplicate registers are used in situations of _________.

A. Banked switching
B. Extential switching
C. context switching
D. Internal switching
ANSWER: C
The instructions which are used to load or store multiple operands are called as __________ A.
Banked instructions
B. Lump transfer instructions
C. Block transfer instructions
D. DMA instructions
ANSWER :C
What are the profiles for ARM architecture?
A. A, R
B. A, M
C. A, R, M
D. R ,M
ANSWER: C
The Thumb instruction set is a--------of the ARM instruction set and the instruction operate on
restricted view of the ARM register
A.Subset
B.Null set
C.Set
D.Semi set
ANSWER: A
The ARMulator has a role in ----------- system design.
A.Hardware
B.Software
C.Embedded
D.AMBA
ANSWER: C
ARM processor supports ___________ address system

A. Little Endian
B. Big Endian
C. X-Little Endian
D. Both Little & Big Endian
ANSWER: D
Which instruction is used to list the registers used for execution?
A. ASSIGN
B. RN
C. PSLOAD
D. ADR
ANSWER : B
Which instruction is basically used to check the branch enable bit?
A. BEQ
B. ASSIGN
C. PSLOAD
D. ADR
ANSWER : A
Which of the following is true?
A. instructions are generally used to perform memory transfer
operations. B. The LDM instruction is used to load data into multiple
locations.
C. The MLA instruction is used perform addition and multiplication
together. D. All of the above
ANSWER: D
The offset used in the conditional branching is __________ bit.
A. 8
B. 16
C. 24
D. 32
ANSWER : C
The Thumb instruction set is a subset of the most commonly used ----ARM instructions.
A.32 bit
B.24 bit
C.16 bit
D. 4 bit
ANSWER: A
CPSR stands for-------

A. current program status Register
B. carry program sub-register
C. clock power status register
D. current program saved register
ANSWER: A
The ARM processor has --------operating modes

A. 2
B. 4
C. 6
D. 8
ANSWER: C
The thumb code requires------------of the space of the ARM code

A. 40%
B. 50%
C. 70%
D. 100%
ANSWER: C
In order to easily add system features like caches and memory timing characteristics ____ is
designed
A. ARMulator
B. AMBA Bus
C. System bus
D. ARM Memory interface
ANSWER: A
In ARM processor, when two 32 bit integers are multiplied, the result obtained is ______
A. 24 bit
B. 25 bit
C. 27 bit
D. 28 bit
ANSWER: B
The Advanced Peripheral Bus offers a simpler interface for------- performance peripherals.
A. Low
B. High
C. Unity
D. Zero
ANSWER :A
All Thumb instructions are ---------long

A. 16 bit
B. 8 bit
C. 64 bit
D. 32 bit
ANSWER :A
With 32-bit memory, the ARM code is -------faster than the Thumb code
A.40%
B.45%
C.55%
D.80%
ANSWER :A
Many Thumb data processing instructions use a--------- address format

A. 1
B. 2
C. 3
D. 4
ANSWER : B
Identify the available stages in 5-stage pipeline:
A. Decode, Write-back, and Fetch
B. Fetch, Decode, Execute , buffer and Write-back
C. Fetch, execute, buffer, and decode
D. Decode, execute , buffer and Write-back
ANSWER: B
The hardware system prototyping tools are related to

A. Rapid silicon prototyping
B. ASB
C. Providing a platform for system verification and software development
D. ARM integrator
ANSWER: A
ARM7 is a --------------- ARM processor

A. 32- bit
B. 8-bit
C. 16-bit
D. 64-bit
ANSWER: A
Which of the following is not the instruction of ARM processor?
A. ADC
B. ADD
C. ORR
D. ANL
ANSWER: D
Which of the following register in ARM7 is used to point to the location of currently executing
instruction in a program?
A.R1
B. R5
C. R15
D. R8
ANSWER : C
Which of the following statements are true with respect to pipelining. I. Pipelining is an
implementation technique whereby multiple instructions are overlapped in execution. It is
not visible to the programmer
II. II. Each step is called a pipe stage or pipe segment
III. III. Pipeline machine cycle is the time required to move an instruction one step down the
pipeline
A. All are true
B.I and III are true
C. II and III are true
D. None of them are true
ANSWER : A
The fastest data access is provided using _______.
A. Caches
B.DRAM’s
C. SRAM’s
D. Registers
ANSWER : D
UNIT 4-MCQ
How many clock pulses are confined by each machine cycle of Peripheral-Interface Controllers?
a. 4
b. 8
c. 12
d. 16
ANSWER: (a) 4
Which flags are more likely to get affected in status registers by Arithmetic and Logical Unit (ALU)
of PIC 16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
What is the execution speed of instructions in PIC especially while operating at the maximum value
of clock rate?
a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs
ANSWER: (b) 0.2 μs
Which operational feature of PIC allows it to reset especially when the power supply drops the
voltage below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
ANSWER: (b)Brown-out reset
Which among the below stated reasons is/are responsible for the selection of PIC
implementation/design on the basis of Harvard architecture instead of Von-Newman architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program
memory d. All of the above
Which among the below specified major functionalities is/are associated with the programmable
timers of PIC?
a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runsa. Only C
b. C & D
c. A, B & D
d. A, B & C
ANSWER: (d) A, B & C

Which timer/s possess an ability to prevent an endless loop hanging condition of PIC along with its
own on-chip RC oscillator by contributing to its reliable operation?
a.Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
ANSWER: (c) Watchdog Timer (WDT)
Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
ANSWER: (b) Program Counter Latch (PCLATH) Register
Which register/s is/are mandatory to get loaded at the beginning before loading or transferring the
contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
ANSWER: (a) W
How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
ANSWER: (a) 1
The RPO status register bit has the potential to determine the effective address of______
a. Direct Addressing Mode

b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
ANSWER: (a) Direct Addressing Mode
Which status bits exhibit carry from lower 4 bits during 8-bit addition and are especially beneficial for
BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
ANSWER: (b) Digits Carry bit (DC)
In PIC microcontroller, which instruction will wait for watchdog timer or external signal to begin
program execution again?
a.nop
b. sleep
c. resume
d. clrwdt
ANSWER: (b) Sleep
Which statement is precise in relation to FSR, INDF and indirect addressing mode? a. Address
byte must be written in FSR before executing INDF instruction in indirect addressing mode
b. Address byte must be written in FSR after executing INDF instruction in indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF instruction in
indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in indirect
addressing mode
a. Only A
b. Only B
c. Only A & B
d. A & D
ANSWER: (a) Only A
Which among the below stated registers specify the address reachability within 7 bits of address
independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
Where do the contents of PCLATH get transferred in the higher location of program counter while
writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
ANSWER: (c) 13th bit
Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
ANSWER:(b) Low
Generation of Power-on-reset pulse can occur only after __________

a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
ANSWER: (a) the detection of increment in VDD from 1.5 V to 2.1 V
What is the rate of power up delay provided by an oscillator start-up timer while operating at XT, LP
and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
ANSWER: (b) 1024 cycles
Which kind of mode is favourable for MCLR pin for indulging in reset operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
ANSWER: (b) Sleep mode
What is the purpose of using the start-up timers in an oscillator circuit of PIC? a.
For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
ANSWER: (a) For ensuring the inception and stabilization of an oscillator in a proper manner
Which program location is allocated to the program counter by the reset function in Power-on-Reset
(POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
ANSWER: (a) Initial address
When does it become very essential to use the external RC components for the reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
ANSWER: (b) Only if VDD power-up slope is insufficient at a requisite level
Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a. A & B
b. C & D
c. A & C
d. B & D
ANSWER: (b) C & D
Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely unique
and distinct from other microcontrollers?a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
ANSWER: (a) It can reset the PIC automatically in running condition
What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in
PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
ANSWER: (a) CPU resets PIC once again in BOR mode
What output is generated by OSC2 pin in PIC oscillator comprising RC components for sychronizing
the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
ANSWER:(c) (1/8) x frequency of OSC1
Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock
sources for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
ANSWER: (b) LP (Low-Power Clocking)
Which significant feature/s of crystal source contribute/s to its maximum predilection and utility as
compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
ANSWER: (a) All of the above
What is the executable frequency range of High speed (HS) clocking method by using cystal/ ceramic/
resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
ANSWER: (d) 4-20 MHz
How many bits are required for addressing 2K & 4K program memories of PIC 16C61
respectively? a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
ANSWER: (c) 11 & 12 bits
What location is attributed to ‘goto Mainline’ instruction in the program memory of PIC 16C61?
a. 000H
b. 004H
c. 001H
d. 011H
ANSWER: (a) 000H
When do the special address 004H get automatically loaded into the program counter?
a. After the execution of RESET action in program counter
b. After the execution of ‘goto Mainline ‘ instruction in the program
memory c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
ANSWER: (c) At the occurrence of interrupt into the program counter
How many bits are utilized by the instruction of direct addressing mode in order to address the
register files in PIC?
a. 2
b. 5
c. 7
d. 8
ANSWER:(c) 7
Which registers are adopted by CPU and peripheral modules so as to control and handle the operation
of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
ANSWER: (c) Special Function Registers
Which among the below specified registors are addressable only from bank1 of RFS?
a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)
ANSWER: (a) PORTA (05H)
Which register acts as an input-output control as well as data direction register for PORTA in bank 2
of RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)
ANSWER: (c) TRISA (85H)
Which bank of RFS has a provision of addressing the status register?

a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2
ANSWER: (c) Either Bank 1 or Bank 2
Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the
external interrupt INT?
a. RBPU
b. INTEDG
c. PSA
d. RTS
ANSWER: (b) INTEDG
Where are the prescalar assignments applied with a usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
ANSWER: (c) Either RTCC or Watchdog timer
Where is the exact specified location of an interrupt flag associated with analog-to-digital converter?
a. INTCON
b. ADCON0
c. ADRES
d. PCLATH
ANSWER: (b) ADCON0
Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register?
a. GIE
b. ADIE
c. RBIE
d. TOIE
ANSWER: (a) GIE
When does it become possible for a bit to get accessed from bank ‘0’ in the direct addressing mode of
PICs?
a. Only when RPO bit is set ‘zero’
b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict
ANSWER: (a) Only when RPO bit is set ‘zero’
The number of instruction set that the PIC microcontroller has is ________
a.35
b. 34
c. 31
d. 45
ANSWER: (a) 35
The PIC microcontroller family uses which architecture?

a. Harward
b. Von-Neumann
c. Array
d. Pipelining
ANSWER:(a) Harward
In PIC microcontroller, group of locations of memory are termed as _________, which can be
accessed through various instruction.
a. Register find
b. Register file
c. Register Locate
d .Register Identify
ANSWER :(b) Register file
In the PIC microcontroller, the register bank which has 32 bytes of special purpose registers is
______ a. Bank 0 &1
b. Bank 1 & 2
c. Bank 0 & 2
d. Bank 0, 1 & 2
ANSWER: (a) Bank 0&1
In PIC microcontroller, The W register serves the purpose similar to ________ of 8085
microprocessors.
a.Program counter
b. Instruction register
c. Accumulator
d. ISR
ANSWER:(a) Accumulator
In PIC microcontroller, the watchdog timer can be cleared using the instruction _________
a. clcwd
b. clrwdt
c. clrwd
d .wdtclr
ANSWER :(a) clrwdt
What is the length of PCLATH?

a.13
b. 8
c. 5
d. 4
ANSWER: (c) 5
The RP0 bit in PIC microcontroller is in ________ register.
a. Flag
b. Status
c. FSR
d. INDF
ANSWER :(a) status
In PIC microcontroller, if there is any carry from lower nibble to higher nibble ________ bit of
STATUS register becomes set.
a.AC
b. CY
c. DC
d. OV
ANSWER:(c) DC
Identify the instruction of PIC which increment f, putting result in F or W is

________ a.inrf f, F(W)
b. incf f, F(W)
c. inf f,F(W)
d. inxf f,F(W)
ANSWER :(b) incf, F(W)
The instruction addlw of PIC microcontroller affects the ______ status

bits. a.C, DC, Z
b. C, Z
c. C, AC, Z
d. C, DC
ANSWER: (a) C ,DC, Z
The instruction of PIC16Cxx that tests the ‘b’ bit of ‘f’ register, where b = 0 to 7 and skip when it
clear is ________
a.btfss
b. btfsc
c. btccc
d. btsss
ANSWER: (b) btfsc
Identify the correct instruction of PIC which AND literal value into W from the following
a.andlw
b. andwf
c. andff
d. andwl
ANSWER : (a) andlw
In PIC microcontroller, the ________ accesses the location pointed by FSR.

a.PCLATH
b. INDF
c.PCL
d. W
ANSWER: (b) INDF
When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of ‘interrupt
on change’?
a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs
ANSWER: (a) By configuring all the pins (RB4-RB7) as inputs
Which digital operations are performed over the detected mismatch outputs with an intention to
generate a single output RB port change output?
a. OR
b. AND
c. EX-OR
d. NAND
ANSWER: (a) OR
What is the purpose of acquiring two different bits from INTCON register for performing any
interrupt operation in PIC 16C61 / 71?
a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
ANSWER: (b) One for enabling the interrupt & one for its occurrence detection
Which among the below specified combination of interrupts belong to the category of the PIC 16C61
/ 71?
a. External, Timer/Counter & serial Port Interrupts
b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts
ANSWER: (c) External, Timer 0 & Port B Interrupts
Which condition results in setting the GIE bit of INTCON automatically?
a. Execution of retfie instruction at the beginning of ISR
b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit
ANSWER: (b) Execution of retfie instruction at the end of ISR
What kind of external edge-sensitive interrupt is generated due to transition effect at pin RBO/INT?
a. INT
b. RBO
c. INTF
d. All of the above
ANSWER:(a) INT
Which bit-register pair plays a significant role in configuring the rising or falling edge triggering
levels in external interrupts of PIC 16C61/71?
a. INTF bit – INTCON register
b. INTEDG bit – OPTION register
c. INT bit -INTCON register
d. INTE bit – OPTION register
ANSWER: (b) INTEDG bit – OPTION register
Consider the following statements. Which of them is /are incorrect?

a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep
mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin. c.
During the occurrence of interrupt, GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.
a. A & B
b. C & D
c. Only A
d. Only C
ANSWER: (b) C & D
What is the purpose of setting TOIE bit in INTCON along with GIE bit?
a. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
ANSWER: (a) For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
Where do the conversion interrupt flag (ADIF) end after an accomplishment of analog-to-digital
(ADC) conversion process?
a. INTCON
b. ADCON0
c. OPTION
ANSWER: (b) ADCON0
How much time is required for conversion per channel if PIC 16C71 possesses four analog channels,
each comprising of 8-bits?
a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs
ANSWER: (c) 20 μs
Which mode of stepper motor operation is suitable for better power

consumption? a. Full Drive
b. Wave Drive
c. Half Drive
d. Quarter Drive
ANSWER : (b) Wave Drive
When two stator electromagnets are energized at a time, the mode is called
_________ a.Full Drive
b. Wave Drive
c. Half Drive
d.Quarter Drive
ANSWER : (a) Full Drive
In wave drive operation of stepper motor, ________ is less when compared to full step
drive. a.current
b. voltage
c. torque
d. speed
ANSWER: (c) torque
What are the special features available in PIC microcontroller for speed control of DC
motor? a.PWM generation and analog channel
b. PWM generation and ADC
c. ADC and analog channel
d. PWM generation and DAC
ANSWER : (a) PWM generation and analog signal
Which command enables the PIC to enter into the power down mode during the operation of
watchdog timer (WDT)?
a. SLEEP
b. RESET
c. STATUS
d. CLR
ANSWER: (a) SLEEP
Which channel would be selected if the values of channel bits CHS0 & CHS1 are ‘1’ & ‘0’
respectively in ADC Status Register?
a. AIN0
b. AIN1
c. AIN2
d. AIN3
ANSWER: (c) AIN2
Which bit is mandatory to get initiated or set for executing the process of analog to digital conversion
in ADCON0?
a. ADIF
b. ADON
c. Go/!Done
d. ADSC1
ANSWER: (c) Go/!Done
What would be the value of ADC clock source, if both the ADC clock bits are selected to be ‘1’?
a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC
ANSWER: (d) FRC
The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated by __________
a. PCFG1 & PCG0
b. VREF
c. ADON
d. All of the above
ANSWER: (a) PCFG1 & PCG0
Which among the below mentioned aspect issues are supported by capture/compare/PWM modules
corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
Which register is suitable for the corresponding count, if the measurement of pulse width is less than
65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
ANSWER: (c) 16-bit register
In PIC microcontroller, the program counter comprises of _____ bit PCL and ______ bit PCLATH.
a.4, 8
b. 8, 5
c. 5, 8
d.8, 4
ANSWER: (b) 8,5
1. In real time operating system ____________
a) all processes have the same priority
b) a task must be serviced by its deadline period
c) process scheduling can be done only once
d) kernel is not required
View Answer
Answer: b
Explanation: None.
2. Hard real time operating system has ______________ jitter than a soft real time
operating system.
a) less
b) more
c) equal
View Answer
Answer: a
Explanation: Jitter is the undesired deviation from the true periodicity.
3. For real time operating systems, interrupt latency should be ____________
a) minimal
b) maximum
c) zero
d) dependent on the scheduling
View Answer
Answer: a
Explanation: Interrupt latency is the time duration between the generation of interrupt
and execution of its service.
4. In rate monotonic scheduling ____________
a) shorter duration job has higher priority
b) longer duration job has higher priority
c) priority does not depend on the duration of the job
View Answer
Answer: a
Explanation: None.
5. In which scheduling certain amount of CPU time is allocated to each process?
a) earliest deadline first scheduling
b) proportional share scheduling
c) equal share scheduling
View Answer
Answer: b
Explanation: None.
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6. The problem of priority inversion can be solved by ____________

a) priority inheritance protocol
b) priority inversion protocol
c) both priority inheritance and inversion protocol
View Answer
Answer: a
Explanation: None.
7. Time duration required for scheduling dispatcher to stop one process and start
another is known as ____________
a) process latency
b) dispatch latency
c) execution latency
d) interrupt latency
View Answer
Answer: b
Explanation: None.
8. Time required to synchronous switch from the context of one thread to the context of
another thread is called?
a) threads fly-back time
b) jitter
c) context switch time
View Answer
Answer: c
Explanation: None.
9. Which one of the following is a real time operating system?
a) RTLinux
b) VxWorks
c) Windows CE
d) All of the mentioned
View Answer
Answer: d
Explanation: None.
10. VxWorks is centered around ____________
a) wind microkernel
b) linux kernel
c) unix kernel
View Answer
Answer: a
Explanation: None.
1. What is the disadvantage of real addressing mode?
a) there is a lot of cost involved
b) time consumption overhead
c) absence of memory protection between processes
d) restricted access to memory locations by processes
View Answer
Answer: c
Explanation: None.
2. Preemptive, priority based scheduling guarantees ____________
a) hard real time functionality
b) soft real time functionality
c) protection of memory
View Answer
Answer: b
Explanation: None.
3. Real time systems must have ____________
a) preemptive kernels
b) non preemptive kernels
c) preemptive kernels or non preemptive kernels
d) neither preemptive nor non preemptive kernels
View Answer
Answer: a
Explanation: None.
4. What is Event latency?
a) the amount of time an event takes to occur from when the system started
b) the amount of time from the event occurrence till the system stops
c) the amount of time from event occurrence till the event crashes
d) the amount of time that elapses from when an event occurs to when it is serviced.
View Answer
Answer: d
Explanation: None.
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5. Interrupt latency refers to the period of time ____________

a) from the occurrence of an event to the arrival of an interrupt
b) from the occurrence of an event to the servicing of an interrupt
c) from arrival of an interrupt to the start of the interrupt service routine
View Answer
Answer: c
Explanation: None.
6. Real time systems need to __________ the interrupt latency.
a) minimize
b) maximize
c) not bother about
View Answer
Answer: a
Explanation: None.
7. The amount of time required for the scheduling dispatcher to stop one process and
start another is known as ______________
a) event latency
b) interrupt latency
c) dispatch latency
d) context switch
View Answer
Answer: c
Explanation: None.
8. The most effective technique to keep dispatch latency low is to ____________
a) provide non preemptive kernels
b) provide preemptive kernels
c) make it user programmed
d) run less number of processes at a time
View Answer
Answer: b
Explanation: None.
9. Priority inversion is solved by use of _____________
a) priority inheritance protocol
b) two phase lock protocol
c) time protocol
View Answer
Answer: a
Explanation: None.
1. In a real time system the computer results ____________
a) must be produced within a specific deadline period
b) may be produced at any time
c) may be correct
View Answer
Answer: a
Explanation: None.
2. In a safety critical system, incorrect operation ____________
a) does not affect much
b) causes minor problems
c) causes major and serious problems
View Answer
Answer: c
Explanation: None.
3. Antilock brake systems, flight management systems, pacemakers are examples of
____________
a) safety critical system
b) hard real time system
c) soft real time system
d) safety critical system and hard real time system
View Answer
Answer: d
Explanation: None.
4. In a ______ real time system, it is guaranteed that critical real time tasks will be
completed within their deadlines.
a) soft
b) hard
c) critical
View Answer
Answer: b
Explanation: None.
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5. Some of the properties of real time systems include ____________

a) single purpose
b) inexpensively mass produced
c) small size
View Answer
Answer: d
Explanation: None.
6. The amount of memory in a real time system is generally ____________
a) less compared to PCs
b) high compared to PCs
c) same as in PCs
d) they do not have any memory
View Answer
Answer: a
Explanation: None.
7. What is the priority of a real time task?
a) must degrade over time
b) must not degrade over time
c) may degrade over time
View Answer
Answer: b
Explanation: None.
8. Memory management units ____________
a) increase the cost of the system
b) increase the power consumption of the system
c) increase the time required to complete an operation
View Answer
Answer: d
Explanation: None.
9. The technique in which the CPU generates physical addresses directly is known as
____________
a) relocation register method
b) real addressing
c) virtual addressing
View Answer
Answer: b
Explanation: None.
1. Earliest deadline first algorithm assigns priorities according to ____________
a) periods
b) deadlines
c) burst times
View Answer
Answer: b
Explanation: None.
2. A process P1 has a period of 50 and a CPU burst of t1 = 25, P2 has a period of 80
and a CPU burst of 35. The total CPU utilization is ____________
a) 0.90
b) 0.74
c) 0.94
d) 0.80
View Answer
Answer: c
Explanation: None.
and a CPU burst of 35., the priorities of P1 and P2 are?
a) remain the same throughout
b) keep varying from time to time
c) may or may not be change
View Answer
Answer: b
Explanation: None.
and a CPU burst of 35., can the two processes be scheduled using the EDF algorithm
without missing their respective deadlines?
a) Yes
b) No
c) Maybe
d) None of the mentioned
View Answer
Answer: a
Explanation: None.
5. Using EDF algorithm practically, it is impossible to achieve 100 percent utilization due
to __________
a) the cost of context switching
b) interrupt handling
c) power consumption
View Answer
Answer: a
Explanation: None.
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6. T shares of time are allocated among all processes out of N shares in __________
scheduling algorithm.
a) rate monotonic
b) proportional share
c) earliest deadline first
View Answer
Answer: b
Explanation: None.
7. If there are a total of T = 100 shares to be divided among three processes, A, B and
C. A is assigned 50 shares, B is assigned 15 shares and C is assigned 20 shares.
A will have ______ percent of the total processor time.
a) 20
b) 15
c) 50
View Answer
Answer: c
Explanation: None.
B will have ______ percent of the total processor time.
a) 20
b) 15
c) 50
View Answer
Answer: b
Explanation: None.
C will have ______ percent of the total processor time.
a) 20
b) 15
c) 50
View Answer
Answer: a
Explanation: None.
If a new process D requested 30 shares, the admission controller would __________
a) allocate 30 shares to it
b) deny entry to D in the system
c) all of the mentioned
View Answer
Answer: b
Explanation: None.
1. To schedule the processes, they are considered _________
a) infinitely long
b) periodic
c) heavy weight
d) light weight
View Answer
Answer: b
Explanation: None.
2. If the period of a process is ‘p’, then what is the rate of the task?
a) p2
b) 2*p
c) 1/p
d) p
View Answer
Answer: c
Explanation: None.
3. The scheduler admits a process using __________
a) two phase locking protocol
b) admission control algorithm
c) busy wait polling
View Answer
Answer: c
Explanation: None.
4. The ____________ scheduling algorithm schedules periodic tasks using a static
priority policy with preemption.
a) earliest deadline first
b) rate monotonic
c) first cum first served
d) priority
View Answer
Answer: b
Explanation: None.
5. Rate monotonic scheduling assumes that the __________
a) processing time of a periodic process is same for each CPU burst
b) processing time of a periodic process is different for each CPU burst
c) periods of all processes is the same
View Answer
Answer: a
Explanation: None.
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6. In rate monotonic scheduling, a process with a shorter period is assigned

__________
a) a higher priority
b) a lower priority
c) higher & lower priority
View Answer
Answer: a
Explanation: None.
7. There are two processes P1 and P2, whose periods are 50 and 100 respectively. P1
is assigned higher priority than P2. The processing times are t1 = 20 for P1 and t2 = 35
for P2. Is it possible to schedule these tasks so that each meets its deadline using Rate
monotonic scheduling?
a) yes
b) no
c) maybe
View Answer
Answer: a
Explanation: None.
8. If a set of processes cannot be scheduled by rate monotonic scheduling algorithm,
then __________
a) they can be scheduled by EDF algorithm
b) they cannot be scheduled by EDF algorithm
c) they cannot be scheduled by any other algorithm
View Answer
Answer: c
Explanation: None.
and a CPU burst of 35. The total CPU utilization is?
a) 0.90
b) 0.74
c) 0.94
d) 0.80
View Answer
Answer: c
Explanation: None.
and a CPU burst of 35. Can the processes be scheduled without missing the deadlines?
a) Yes
b) No
c) Maybe
View Answer
Answer: b
Explanation: None.
1. An un-interruptible unit is known as ____________
a) single
b) atomic
c) static
View Answer
Answer: b
Explanation: None.
2. TestAndSet instruction is executed ____________
a) after a particular process
b) periodically
c) atomically
View Answer
Answer: c
Explanation: None.
3. Semaphore is a/an _______ to solve the critical section problem.
a) hardware for a system
b) special program for a system
c) integer variable
View Answer
Answer: c
Explanation: None.
4. What are the two atomic operations permissible on semaphores?
a) wait
b) stop
c) hold
View Answer
Answer: a
Explanation: None.
5. What are Spinlocks?
a) CPU cycles wasting locks over critical sections of programs
b) Locks that avoid time wastage in context switches
c) Locks that work better on multiprocessor systems
View Answer
Answer: d
Explanation: None.
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6. What is the main disadvantage of spinlocks?

a) they are not sufficient for many process
b) they require busy waiting
c) they are unreliable sometimes
d) they are too complex for programmers
View Answer
Answer: b
Explanation: None.
7. The wait operation of the semaphore basically works on the basic _______ system
call.
a) stop()
b) block()
c) hold()
d) wait()
View Answer
Answer: b
Explanation: None.
8. The signal operation of the semaphore basically works on the basic _______ system
call.
a) continue()
b) wakeup()
c) getup()
d) start()
View Answer
Answer: b
Explanation: None.
9. If the semaphore value is negative ____________
a) its magnitude is the number of processes waiting on that semaphore
b) it is invalid
c) no operation can be further performed on it until the signal operation is performed on
it
View Answer
Answer: a
Explanation: None.
10. The code that changes the value of the semaphore is ____________
a) remainder section code
b) non – critical section code
c) critical section code
View Answer
Answer: c
Explanation: None.
11. The following program consists of 3 concurrent processes and 3 binary semaphores.
The semaphores are initialized as S0 = 1, S1 = 0, S2 = 0.
Process P0
while(true)
{
wait(S0);
print '0';
release(S1);
release(S2);
}
Process P1
wait(S1);
release(S0);
Process P2
wait(S2);
release(S0);
How many times will P0 print ‘0’?

a) At least twice
b) Exactly twice
c) Exactly thrice
d) Exactly once
View Answer
Answer: a
Explanation: None.
12. Each process Pi, i = 0,1,2,3,……,9 is coded as follows.
repeat
P(mutex)
{Critical Section}
V(mutex)
forever
The code for P10 is identical except that it uses V(mutex) instead of P(mutex). What is
the largest number of processes that can be inside the critical section at any moment
(the mutex being initialized to 1)?
a) 1
b) 2
c) 3
View Answer
Answer: c
Explanation: Any one of the 9 processes can get into critical section after executing
P(mutex) which decrements the mutex value to 0. At this time P10 can enter critical
section by incrementing the value to 1. Now any of the 9 processes can enter the critical
section by again decrementing the mutex value to 0. None of the remaining processes
can get into their critical sections.
13. Two processes, P1 and P2, need to access a critical section of code. Consider the
following synchronization construct used by the processes.
Process P1 :
while(true)
{
w1 = true;
while(w2 == true);
Critical section
w1 = false;
}
Remainder Section
Process P2 :
while(true)
{
w2 = true;
while(w1 == true);
Critical section
w2 = false;
}
Remainder Section
Here, w1 and w2 have shared variables, which are initialized to false. Which one of the
following statements is TRUE about the above construct?
a) It does not ensure mutual exclusion
b) It does not ensure bounded waiting
c) It requires that processes enter the critical section in strict alternation
d) It does not prevent deadlocks but ensures mutual exclusion
View Answer
Answer: d
Explanation: None
1. What will happen if a non-recursive mutex is locked more than once?
a) Starvation
b) Deadlock
c) Aging
d) Signaling
View Answer
Answer: b
Explanation: If a thread which had already locked a mutex, tries to lock the mutex again,
it will enter into the waiting list of that mutex, which results in a deadlock. It is because
no other thread can unlock the mutex.
2. What is a semaphore?
a) is a binary mutex
b) must be accessed from only one process
c) can be accessed from multiple processes
View Answer
Answer: c
Explanation: None.
3. What are the two kinds of semaphores?
a) mutex & counting
b) binary & counting
c) counting & decimal
d) decimal & binary
View Answer
Answer: b
Explanation: None.
4. What is a mutex?
a) is a binary mutex
b) must be accessed from only one process
c) can be accessed from multiple processes
View Answer
Answer: b
Explanation: None.
5. At a particular time of computation the value of a counting semaphore is 7.Then 20 P
operations and 15 V operations were completed on this semaphore. The resulting value
of the semaphore is? (GATE 1987)
a) 42
b) 2
c) 7
d) 12
View Answer
Answer: b
Explanation: P represents Wait and V represents Signal. P operation will decrease the
value by 1 every time and V operation will increase the value by 1 every time.
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6. A binary semaphore is a semaphore with integer values ____________

a) 1
b) -1
c) 0.8
d) 0.5
View Answer
Answer: a
Explanation: None.
7. The following pair of processes share a common variable X.
Process A
int Y;
A1: Y = X*2;
A2: X = Y;
Process B
int Z;
B1: Z = X+1;
B2: X = Z;
X is set to 5 before either process begins execution. As usual, statements within a

process are executed sequentially, but statements in process A may execute in any
order with respect to statements in process B.
How many different values of X are possible after both processes finish executing?
a) two
b) three
c) four
d) eight
View Answer
Answer: c
Explanation: Here are the possible ways in which statements from A and B can be
interleaved.
A1 A2 B1 B2: X = 11
A1 B1 A2 B2: X = 6
A1 B1 B2 A2: X = 10
B1 A1 B2 A2: X = 10
B1 A1 A2 B2: X = 6
B1 B2 A1 A2: X = 12.
8. The program follows to use a shared binary semaphore T.
Process A
int Y;
A1: Y = X*2;
A2: X = Y;
signal(T);
Process B
int Z;
B1: wait(T);
B2: Z = X+1;
X = Z;
T is set to 0 before either process begins execution and, as before, X is set to 5.

Now, how many different values of X are possible after both processes finish executing?
a) one
b) two
c) three
d) four
View Answer
9. Semaphores are mostly used to implement ____________
a) System calls
b) IPC mechanisms
c) System protection
View Answer
Answer: b
Explanation: None.
10. Spinlocks are intended to provide __________ only.
a) Mutual Exclusion
b) Bounded Waiting
c) Aging
d) Progress
View Answer
Answer: b
Explanation: None.
1. The bounded buffer problem is also known as ____________
a) Readers – Writers problem
b) Dining – Philosophers problem
c) Producer – Consumer problem
View Answer
Answer: c
Explanation: None.
2. In the bounded buffer problem, there are the empty and full semaphores that
____________
a) count the number of empty and full buffers
b) count the number of empty and full memory spaces
c) count the number of empty and full queues
View Answer
Answer: a
Explanation: None.
3. In the bounded buffer problem ____________
a) there is only one buffer
b) there are n buffers ( n being greater than one but finite)
c) there are infinite buffers
d) the buffer size is bounded
View Answer
Answer: b
Explanation: None.
4. To ensure difficulties do not arise in the readers – writers problem _______ are given
exclusive access to the shared object.
a) readers
b) writers
c) readers and writers
View Answer
Answer: b
Explanation: None.
5. The dining – philosophers problem will occur in case of ____________
a) 5 philosophers and 5 chopsticks
b) 4 philosophers and 5 chopsticks
c) 3 philosophers and 5 chopsticks
d) 6 philosophers and 5 chopsticks
View Answer
Answer: a
Explanation: None.
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6. A deadlock free solution to the dining philosophers problem ____________
a) necessarily eliminates the possibility of starvation
b) does not necessarily eliminate the possibility of starvation
c) eliminates any possibility of any kind of problem further
View Answer
Answer: b
Explanation: None.
7. All processes share a semaphore variable mutex, initialized to 1. Each process must
execute wait(mutex) before entering the critical section and signal(mutex) afterward.
Suppose a process executes in the following manner.
signal(mutex);
.....
critical section
.....
wait(mutex);
In this situation :
a) a deadlock will occur
b) processes will starve to enter critical section
c) several processes maybe executing in their critical section
View Answer
Answer: c
Explanation: None.
8. All processes share a semaphore variable mutex, initialized to 1. Each process must
execute wait(mutex) before entering the critical section and signal(mutex) afterward.
Suppose a process executes in the following manner.
wait(mutex);
.....
critical section
.....
wait(mutex);
a) a deadlock will occur

b) processes will starve to enter critical section
c) several processes maybe executing in their critical section
View Answer
Answer: a
Explanation: None.
9. Consider the methods used by processes P1 and P2 for accessing their critical
sections whenever needed, as given below. The initial values of shared boolean
variables S1 and S2 are randomly assigned. (GATE 2010)
Method used by P1 :
while(S1==S2);
Critical section
S1 = S2;
Method used by P2 :
while(S1!=S2);
Critical section
S2 = not(S1);
Which of the following statements describes properties achieved?

a) Mutual exclusion but not progress
b) Progress but not mutual exclusion
c) Neither mutual exclusion nor progress
d) Both mutual exclusion and progress
View Answer
Answer: d
Explanation: None.
1. A monitor is a type of ____________
a) semaphore
b) low level synchronization construct
c) high level synchronization construct
View Answer
Answer: c
Explanation: None.
2. A monitor is characterized by ____________
a) a set of programmer defined operators
b) an identifier
c) the number of variables in it
View Answer
Answer: a
Explanation: None.
3. A procedure defined within a ________ can access only those variables declared
locally within the _______ and its formal parameters.
a) process, semaphore
b) process, monitor
c) semaphore, semaphore
d) monitor, monitor
View Answer
Answer: d
Explanation: None.
4. The monitor construct ensures that ____________
a) only one process can be active at a time within the monitor
b) n number of processes can be active at a time within the monitor (n being greater
than 1)
c) the queue has only one process in it at a time
View Answer
Answer: a
Explanation: None.
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5. What are the operations that can be invoked on a condition variable?

a) wait & signal
b) hold & wait
c) signal & hold
d) continue & signal
View Answer
Answer: a
Explanation: None.
6. Which is the process of invoking the wait operation?
a) suspended until another process invokes the signal operation
b) waiting for another process to complete before it can itself call the signal operation
c) stopped until the next process in the queue finishes execution
View Answer
Answer: a
Explanation: None.
7. If no process is suspended, the signal operation ____________
a) puts the system into a deadlock state
b) suspends some default process execution
c) nothing happens
d) the output is unpredictable
View Answer
Answer: c
Explanation: None.
1. What is the Real-time systems?
A. Used for monitoring events as they occur
B. Primarily used on mainframe computers
C. Used for real-time interactive users
D. Used for program development
Answer - Click Here:
A
2. The __________ Operating System pays more attention to the meeting of
the time limits.
A. Network
B. Distributed
C. Online
D. Real-time
D
3. In real time operating system is__________
A. kernel is not required
B. process scheduling can be done only once task
C. must be serviced by its deadline period
D. all processes have the same priority
C
4. The interrupt latency should be _________ for real time operating systems.
A. maximum
B. minimal
C. dependent on the scheduling
D. zero
B
5. Which scheduling amount of CPU time is allocated to each process?
A. equal share scheduling
B. none of the mentioned
C. earliest deadline first scheduling
D. proportional share scheduling
D
6. What is the Use of the robot by car manufacturing companies the example
of…
A. applicant controlled computers
B. user-controlled computers
C. machine controlled computers
D. network controlled computers
C
7. When the System processes data instructions without any delay is called as
A. online system
B. real-time system
C. instruction system
D. offline system
B
8. Which single task of a particular application is process is a type of processor…
A. applicant processor
B. one task processor
C. real time processor
D. dedicated processor
D
9. The Designing of system take into considerations of_________.
A. operating system
B. communication system
C. hardware
D. all of the above
E. none of these
D
10. The Time duration required for scheduling dispatcher to stop one process
and start another is called…
A. dispatch latency
B. process latency
C. interrupt latency
D. execution latency
A
11. Which of the following is correct in real time?
A. non-preemptive kernels
B. preemptive kernels
C. neither preemptive nor non-preemptive kernels
D. preemptive kernels or non preemptive kernels
B
12. Which of the following is Preemptive, priority-based scheduling
guarantees?
A. protection of memory
B. hard real-time functionality
C. soft real-time functionality
D. all of the above
E. none of these
C
If we want to schedule the processes, they are considered as?
(A). infinitely long
(B). periodic
(C). heavyweight
(D). lightweight
(E). None of these
MCQ Answer: B
Suppose the period of a process is ‘p’, then the rate of the task is?
(A). p2
(B). 2*p
(C). 1/p
(D). p
(E). None of these
MCQ Answer: C
Suppose that we have a process P1 has a period of 50 and we have a

CENTRAL PROCESSING UNIT burst of t1 = 25, P2 has a period of 80, and a
CENTRAL PROCESSING UNIT burst of 35. The total CENTRAL PROCESSING
UNIT utilization is :
(A). 0.90
(B). 0.74
(C). 0.94
(D). 0.80
(E). None of these
MCQ Answer: C
T shares of time are allocated among all processes out of N shares in which of
the following scheduling algorithm?
(A). rate monotonic
(B). proportional share
(C). the earliest deadline first
(D). None of these
(E). None of these
MCQ Answer: B
Which of the following scheduling algorithm schedules periodic tasks using a

static priority policy by considering the priorities?
(A). the earliest deadline first
(B). rate monotonic
(C). first cum first served
(D). priority
(E). None of these
MCQ Answer: B
The scheduler permits a process using which of the following?

(A). two-phase locking protocol
(B). admission control algorithm
(C). busy-wait polling
(D). None of these
(E). None of these
MCQ Answer: C
In the case of rate monotonic scheduling, a process with a shorter period is

assigned which of the following priority?
(A). a higher
(B). a lower
(C). higher & lower
(D). None of these
(E). None of these
MCQ Answer: A
There are two processes processes1 and processes2, whose periods are 50
and 100 respectively. P1 is allotted higher priority than P2. The processing
times are t1 = 20 for P1 and t2 = 35 for P2. Is it feasible to schedule these tasks
so that these tasks fulfill their deadline using Rate monotonic scheduling?
(A). yes
(B). no
(C). maybe
(D). None of these
(E). None of these
MCQ Answer: A
Practically, if we want to use the EDF algorithm, it is impossible to achieve

100% utilization and its possible due to Which of the following?
(A). the cost of context switching
(B). interrupt handling
(C). power consumption
(D). all of the mentioned
(E). None of these
MCQ Answer: A
1. _______ OS pays more attention on the meeting of the time limits.
a. Distributed
b. Network
c. Real time
d. Online
View Answer Report Discuss Too Difficult!
Answer: (c).Real time

2. Real time systems are ________.
a. Primarily used on mainframe computers
b. Used for monitoring events as they occur
c. Used for program development
d. Used for real time interactive users
Answer: (b).Used for monitoring events as they occur
3. In ______ OS, the response time is very critical.
a. Multitasking
b. Batch
c. Online
d. Real-time
Answer: (d). Real-time
4. Which scheduling policy is most suitable for a time-shared operating system
a. Shortest-job First.
b. Elevator.
c. Round-Robin.
d. First-Come-First-Serve.
5. The basic types of OS are ...................
a. batch and time sharing

b. sequential and real time
c. direct and interactive
d. batch and interactive
Answer: (d).batch and interactive
6. In real time operating system
a. all processes have the same priority
b. a task must be serviced by its deadline period
c. process scheduling can be done only once
d. kernel is not required
Answer: (b).a task must be serviced by its deadline period
7. Hard real time operating system has ___ jitter than a soft real time operating system.
a. less
b. more
c. equal
d. none of the mentioned
Answer: (a).less
8. For real time operating systems, interrupt latency should be
a. minimal
b. maximum
c. zero
d. dependent on the scheduling
Answer: (a).minimal
9. In rate monotonic scheduling
a. shorter duration job has higher priority
b. longer duration job has higher priority
c. priority does not depend on the duration of the job
Answer: (a).shorter duration job has higher priority
10. In which scheduling certain amount of CPU time is allocated to each process?
a. earliest deadline first scheduling
b. proportional share scheduling
c. equal share scheduling
Answer: (b).proportional share scheduling
1. When there is an embedded component in a real time system, it is

known as a ?
A. firm time embedded system
B. simple time embedded system
C. real time embedded system
D. complex time embedded system
View Answer
Ans : C
Explanation: When there is an embedded component in a real time system, it is known

as a real time embedded system.
2. How many types of real time embedded systems?
A. 1
B. 2
C. 3
D. 4
View Answer
Ans : B
Explanation: There are primarily two types of real time embedded systems i.e. hard and
soft.
3. Which system makes sure that all critical processes are completed
within the given time frame?
A. hard
B. soft
C. simple
D. complex
View Answer
Ans : A
Explanation: Hard Real Time Embedded System : This type of system makes sure that
all critical processes are completed within the given time frame.
4. Which of the following are Applications of Real Time Embedded

Systems?
A. Vehicle control systems
B. satellite communications
C. Medical systems for radiation therapy
D. All of the above
View Answer
Ans : D
Explanation: All of the above are Applications of Real Time Embedded Systems.
5. In which area, Soft real time systems are used ?

A. multimedia
B. scientific projects
C. missiles
D. Both A and B
View Answer
Ans : D
Explanation: Soft real time systems are used in various areas such as multimedia,
scientific projects etc.
6. Every real-time system has a set of timing constraints, timing

constraints can be broken down into ______ categories.
A. 1
B. 2
C. 3
D. 4
View Answer
Ans : B
Explanation: Timing constraints can be broken down into two categories: event response
and task scheduling.
7. Hard real time operating system has ______________ jitter than a soft
real time operating system
A. less
B. more
C. equal
D. Can not say
View Answer
Ans : A
Explanation: Jitter is the undesired deviation from the true periodicity.
8. For real time, interrupt latency should be ____________

A. Zero
B. Maximum
C. Minimum
D. Can not say
View Answer
Ans : C
Explanation: Interrupt latency is the time duration between the generation of interrupt
and execution of its service.
9. Latency is defined as the?
A. response time plus the detection time
B. detection time minus response time
C. detection time plus response time
D. response time minus the detection time
View Answer
Ans : D
Explanation: Latency is defined as the response time minus the detection time.
10. If a system doesn't have timing constraints, it is not real-time.

A. TRUE
B. FALSE
C. Can be true or false
D. Can not say
View Answer
Ans : A
Explanation: True, Every real-time system has a set of timing constraints that it has been
designed to meet. If a system doesn't have timing constraints, it is not real-time.
. Which module gives control of the CPU to the process selected by the short-term
scheduler?
a) dispatcher
b) interrupt
c) scheduler
View Answer
Answer: a
Explanation: None.
2. The processes that are residing in main memory and are ready and waiting to execute
are kept on a list called _____________
a) job queue
b) ready queue
c) execution queue
d) process queue
View Answer
Answer: b
Explanation: None.
3. The interval from the time of submission of a process to the time of completion is
termed as ____________
a) waiting time
b) turnaround time
c) response time
d) throughput
View Answer
Answer: b
Explanation: None.
4. Which scheduling algorithm allocates the CPU first to the process that requests the
CPU first?
a) first-come, first-served scheduling
b) shortest job scheduling
c) priority scheduling
View Answer
Answer: a
Explanation: None.
5. In priority scheduling algorithm ____________
a) CPU is allocated to the process with highest priority
b) CPU is allocated to the process with lowest priority
c) Equal priority processes can not be scheduled
View Answer
Answer: a
Explanation: None.
6. In priority scheduling algorithm, when a process arrives at the ready queue, its priority
is compared with the priority of ____________
a) all process
b) currently running process
c) parent process
d) init process
View Answer
Answer: b
Explanation: None.
7. Which algorithm is defined in Time quantum?
a) shortest job scheduling algorithm
b) round robin scheduling algorithm
c) priority scheduling algorithm
d) multilevel queue scheduling algorithm
View Answer
Answer: b
Explanation: None.
8. Process are classified into different groups in ____________
a) shortest job scheduling algorithm
b) round robin scheduling algorithm
c) priority scheduling algorithm
d) multilevel queue scheduling algorithm
View Answer
Answer: d
Explanation: None.
9. In multilevel feedback scheduling algorithm ____________
a) a process can move to a different classified ready queue
b) classification of ready queue is permanent
c) processes are not classified into groups
View Answer
Answer: a
Explanation: None.
10. Which one of the following can not be scheduled by the kernel?
a) kernel level thread
b) user level thread
c) process
View Answer
Answer: b
Explanation: User level threads are managed by thread library and the kernel is unaware
of them.
1. CPU scheduling is the basis of ___________
a) multiprocessor systems
b) multiprogramming operating systems
c) larger memory sized systems
View Answer
Answer: b
Explanation: None.
2. With multiprogramming ______ is used productively.
a) time
b) space
c) money
View Answer
Answer: a
Explanation: None.
3. What are the two steps of a process execution?
a) I/O & OS Burst
b) CPU & I/O Burst
c) Memory & I/O Burst
d) OS & Memory Burst
View Answer
Answer: b
Explanation: None.
4. An I/O bound program will typically have ____________
a) a few very short CPU bursts
b) many very short I/O bursts
c) many very short CPU bursts
d) a few very short I/O bursts
View Answer
Answer: c
Explanation: None.
5. A process is selected from the ______ queue by the ________ scheduler, to be
executed.
a) blocked, short term
b) wait, long term
c) ready, short term
d) ready, long term
View Answer
Answer: c
Explanation: None.
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6. In the following cases non – preemptive scheduling occurs?

a) When a process switches from the running state to the ready state
b) When a process goes from the running state to the waiting state
c) When a process switches from the waiting state to the ready state
View Answer
Answer: b
Explanation: There is no other choice.
7. The switching of the CPU from one process or thread to another is called
____________
a) process switch
b) task switch
c) context switch
View Answer
Answer: d
Explanation: None.
8. What is Dispatch latency?
a) the speed of dispatching a process from running to the ready state
b) the time of dispatching a process from running to ready state and keeping the CPU
idle
c) the time to stop one process and start running another one
View Answer
Answer: c
Explanation: None.
9. Scheduling is done so as to ____________
a) increase CPU utilization
b) decrease CPU utilization
c) keep the CPU more idle
View Answer
Answer: a
Explanation: None.
a) increase the throughput
b) decrease the throughput
c) increase the duration of a specific amount of work
View Answer
Answer: a
Explanation: None.
11. What is Turnaround time?
a) the total waiting time for a process to finish execution
b) the total time spent in the ready queue
c) the total time spent in the running queue
d) the total time from the completion till the submission of a process
View Answer
Answer: d
Explanation: None.
a) increase the turnaround time
b) decrease the turnaround time
c) keep the turnaround time same
d) there is no relation between scheduling and turnaround time
View Answer
Answer: b
Explanation: None.
13. What is Waiting time?
a) the total time in the blocked and waiting queues
b) the total time spent in the ready queue
c) the total time spent in the running queue
d) the total time from the completion till the submission of a process
View Answer
Answer: b
Explanation: None.
a) increase the waiting time
b) keep the waiting time the same
c) decrease the waiting time
View Answer
Answer: c
Explanation: None.
15. What is Response time?
a) the total time taken from the submission time till the completion time
b) the total time taken from the submission time till the first response is produced
c) the total time taken from submission time till the response is output
View Answer
Answer: b
Explanation: None.
1. Round robin scheduling falls under the category of ____________

a) Non-preemptive scheduling
b) Preemptive scheduling
c) All of the mentioned
View Answer
Answer: b
Explanation: None.
2. With round robin scheduling algorithm in a time shared system ____________
a) using very large time slices converts it into First come First served scheduling
algorithm
b) using very small time slices converts it into First come First served scheduling
algorithm
c) using extremely small time slices increases performance
d) using very small time slices converts it into Shortest Job First algorithm
View Answer
Answer: a
Explanation: All the processes will be able to get completed.
3. The portion of the process scheduler in an operating system that dispatches
processes is concerned with ____________
a) assigning ready processes to CPU
b) assigning ready processes to waiting queue
c) assigning running processes to blocked queue
View Answer
Answer: a
Explanation: None.
4. Complex scheduling algorithms ____________
a) are very appropriate for very large computers
b) use minimal resources
c) use many resources
View Answer
Answer: a
Explanation: Large computers are overloaded with a greater number of processes.
5. What is FIFO algorithm?
a) first executes the job that came in last in the queue
b) first executes the job that came in first in the queue
c) first executes the job that needs minimal processor
d) first executes the job that has maximum processor needs
View Answer
Answer: b
Explanation: None.
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6. The strategy of making processes that are logically runnable to be temporarily

suspended is called ____________
a) Non preemptive scheduling
b) Preemptive scheduling
c) Shortest job first
d) First come First served
View Answer
Answer: b
Explanation: None.
7. What is Scheduling?
a) allowing a job to use the processor
b) making proper use of processor
c) all of the mentioned
View Answer
Answer: a
Explanation: None.
8. There are 10 different processes running on a workstation. Idle processes are waiting
for an input event in the input queue. Busy processes are scheduled with the Round-
Robin time sharing method. Which out of the following quantum times is the best value
for small response times, if the processes have a short runtime, e.g. less than 10ms?
a) tQ = 15ms
b) tQ = 40ms
c) tQ = 45ms
d) tQ = 50ms
View Answer
Answer: a
Explanation: None.
9. Orders are processed in the sequence they arrive if _______ rule sequences the jobs.
a) earliest due date
b) slack time remaining
c) first come, first served
d) critical ratio
View Answer
Answer: c
Explanation: None.
10. Which of the following algorithms tends to minimize the process flow time?
a) First come First served
b) Shortest Job First
c) Earliest Deadline First
d) Longest Job First
View Answer
Answer: b
Explanation: None.
11. Under multiprogramming, turnaround time for short jobs is usually ________ and
that for long jobs is slightly ___________
a) Lengthened; Shortened
b) Shortened; Lengthened
c) Shortened; Shortened
d) Shortened; Unchanged
View Answer
Answer: b
Explanation: None.
12. Which of the following statements are true? (GATE 2010)
a) I only
b) I and III only
c) II and III only
d) I, II and III
View Answer
Answer: d
Explanation: I) Shortest remaining time first scheduling is a preemptive version of
shortest job scheduling. It may cause starvation as shorter processes may keep coming
and a long CPU burst process never gets CPU.
II) Preemption may cause starvation. If priority based scheduling with preemption is
used, then a low priority process may never get CPU.
III) Round Robin Scheduling improves response time as all processes get CPU after a
specified time.
1. Which is the most optimal scheduling algorithm?
a) FCFS – First come First served
b) SJF – Shortest Job First
c) RR – Round Robin
View Answer
Answer: b
Explanation: None.
2. The real difficulty with SJF in short term scheduling is ____________
a) it is too good an algorithm
b) knowing the length of the next CPU request
c) it is too complex to understand
View Answer
Answer: b
Explanation: None.
3. The FCFS algorithm is particularly troublesome for ____________
a) time sharing systems
b) multiprogramming systems
c) multiprocessor systems
d) operating systems
View Answer
Answer: b
Explanation: In a time sharing system, each user needs to get a share of the CPU at
regular intervals.
4. Consider the following set of processes, the length of the CPU burst time given in
milliseconds.
Process Burst time
P1 6
P2 8
P3 7
P4 3
Assuming the above process being scheduled with the SJF scheduling algorithm.
a) The waiting time for process P1 is 3ms
b) The waiting time for process P1 is 0ms
c) The waiting time for process P1 is 16ms
d) The waiting time for process P1 is 9ms
View Answer
Answer: a
Explanation: None.
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5. Preemptive Shortest Job First scheduling is sometimes called ____________

a) Fast SJF scheduling
b) EDF scheduling – Earliest Deadline First
c) HRRN scheduling – Highest Response Ratio Next
d) SRTN scheduling – Shortest Remaining Time Next
View Answer
Answer: d
Explanation: None.
6. An SJF algorithm is simply a priority algorithm where the priority is ____________
a) the predicted next CPU burst
b) the inverse of the predicted next CPU burst
c) the current CPU burst
d) anything the user wants
View Answer
Answer: a
Explanation: The larger the CPU burst, the lower the priority.
7. Choose one of the disadvantages of the priority scheduling algorithm?
a) it schedules in a very complex manner
b) its scheduling takes up a lot of time
c) it can lead to some low priority process waiting indefinitely for the CPU
View Answer
Answer: c
Explanation: None.
8. What is ‘Aging’?
a) keeping track of cache contents
b) keeping track of what pages are currently residing in memory
c) keeping track of how many times a given page is referenced
d) increasing the priority of jobs to ensure termination in a finite time
View Answer
Answer: d
Explanation: None.
9. A solution to the problem of indefinite blockage of low – priority processes is
____________
a) Starvation
b) Wait queue
c) Ready queue
d) Aging
View Answer
Answer: d
Explanation: None.
10. Which of the following statements are true? (GATE 2010)
i) Shortest remaining time first scheduling may cause starvation
ii) Preemptive scheduling may cause starvation
iii) Round robin is better than FCFS in terms of response time
a) i only
b) i and iii only
c) ii and iii only
d) i, ii and iii
View Answer
Answer: d
Explanation: None.
11. Which of the following scheduling algorithms gives minimum average waiting time?
a) FCFS
b) SJF
c) Round – robin
d) Priority
View Answer
Answer: b
Explanation: None
https://examradar.com/operating-system-scheduling-algorithms-mcqs-type-questions-
answers/
Round-robin scheduling
A. allows interactive tasks quicker access to the processor
B. is quite complex to implement
C. gives each task the same chance at the processor
D. allows processor-bound tasks more time in the processor
E. None of the above
Answer: Option C
1. which of the following can not be scheduled by the kernel?
A. process
B. user-level thread
C. kernel-level thread
D. none of the mentioned
B
2. if _______ rule sequences the jobs Orders are processed in the sequence they
arrive
A. first come, first served
B. critical ratios
C. earliest due date
D. lack time remaining
A
3. scheduling algorithm In multilevel feedback
A. processes are not classified into groups
B. a process can move to a different classified ready queue…
C. classification of the ready queue is permanent
B
4. Select one which algorithms tend to minimize the process flow time?
A. First come First served
B. Earliest Deadline First
C. Shortest Job First
D. Longest Job First
C
5. The process can be classified into many groups in
A. shortest job scheduling algorithm
B. multilevel queue scheduling algorithm
C. round-robin scheduling algorithm
D. priority scheduling algorithm
B
6. The turnaround time for short jobs during multiprogramming is usually Shortened
and that for long jobs is slightly ___________
A. Shortened
B. Unchanged
C. Lengthened
D. Shortened
C
7. Time quantum can be said
A. multilevel queue scheduling algorithm
B. round-robin scheduling algorithm
C. shortest job scheduling algorithm
D. priority scheduling algorithm
B
8. Selects the statements which are true according to GATE 2010.
i. starvation may be caused by Shortest remaining time first scheduling
ii. starvation may be caused by Preemptive scheduling
iii. in terms of response time, Round robin is better than FCFS
A. all the given option
B. i only
C. ii and iii only
D. i and iii only
A
9. At the ready queue when a process arrives In priority scheduling algorithm, the
priority of this process is compared with the priority of?
A. currently running process
B. parent process
C. all process
D. init process
A
10. The FIFO algorithm said :
A. executes the job first that needs a minimal processor
B. the job first executes that comes last in the queue
C. the job first executes that has maximum processor needs
D. the job first executes that came in first in the queue
D
11. A program that is bound by CPU might have
A. Cpu bursts many short
B. Cpu bursts a few short
C. Cpu bursts a few longer
D. None of the above
C
12. scheduling algorithms that work on complex :
A. uses few resources
B. uses most resources
C. are suitable for large computers
D. all of the mentioned
C
13. scheduling algorithm which allocates the CPU first to the process which requests
the CPU first?
A. FCFS scheduling
B. priority scheduling
C. shortest job scheduling
A
14. In an operating system, the portion of the process scheduler that forward
processes is concerned with :
A. running processes are assigning to blocked queue
B. ready processes are assigning to CPU
C. ready processes are assigning to the waiting queue
D. all of the mentioned
B
15. From the time of submission of a process to the time of completion, The interval
is termed as
A. waiting time
B. turnaround time
C. response time
D. throughput
B
15. From the time of submission of a process to the time of completion, The interval
is termed as
A. waiting time
B. turnaround time
C. response time
D. throughput
B
16. under the category of_______ Round-robin scheduling falls :
A. Preemptive scheduling
B. Nonpreemptive scheduling
C. All of the mentioned
D. None of the mentioned
A
17. The processes that are inhabited in main memory and are ready and waiting to
execute and remained on a list called
A. process queue
B. execution queue
C. job queue
D. ready queue
18. control of the CPU to the process selected by the short-term scheduler is
assigned by the module ________.
A. interrupt
B. scheduler
C. dispatcher
C
71. Round robin scheduling falls under the category of :
a. Non preemptive scheduling
b. Preemptive scheduling
c. Both of the above
Answer: (b).Preemptive scheduling
72. With round robin scheduling algorithm in a time shared system,
a. using very large time slices converts it into First come First served scheduling algorithm
b. using very small time slices converts it into First come First served scheduling algorithm
c. using extremely small time slices increases performance
d. using very small time slices converts it into Shortest Job First algorithm
Answer: (a).using very large time slices converts it into First come First served scheduling algorithm
73. The portion of the process scheduler in an operating system that dispatches processes is concerned with
a. assigning ready processes to CPU
b. assigning ready processes to waiting queue
c. assigning running processes to blocked queue

d. All of these
Answer: (a).assigning ready processes to CPU
74. Complex scheduling algorithms :
a. are very appropriate for very large computers
b. use minimal resources
c. use many resources
d. All of these
Answer: (a).are very appropriate for very large computers
75. The FIFO algorithm :
a. first executes the job that came in last in the queue
b. first executes the job that came in first in the queue
c. first executes the job that needs minimal processor
d. first executes the job that has maximum processor needs
Answer: (b).first executes the job that came in first in the queue
76. The strategy of making processes that are logically runnable to be temporarily suspended is called :
a. Non preemptive scheduling
b. Preemptive scheduling
c. Shortest job first
d. First come First served

Answer: (b).Preemptive scheduling
77. CPU Scheduling is :
a. allowing a job to use the processor
b. making proper use of processor
c. Both a and b
d. None of these
Answer: (c).Both a and b
78. There are 10 different processes running on a workstation. Idle processes are waiting for an input event in
scheduled with the Round-Robin timesharing method. Which out of the following quantum times is the bes
processes have a short runtime, e.g. less than 10ms ?
a. tQ = 15ms
b. tQ = 40ms
c. tQ = 45ms
d. tQ = 50ms
Answer: (a).tQ = 15ms
79. Which of the following algorithms tends to minimize the process flow time ?
a. First come First served
b. Shortest Job First
c. Earliest Deadline First
d. Longest Job First
Answer: (b).Shortest Job First

80. Which of the following statements are true ?
a. I only
b. I and III only
c. II and III only
d. I, II and III
Answer: (d).I, II and III

1. Round robin scheduling is essentially the preemptive version of ________ ?
A.
FIFO
B. Shortest job first
C. Shortest remaining
D. Longest time first
- Answer&Explanation
Answer:Option A
Explanation :
No answer description available for this question.
Hide Answer
2. A page fault occurs ?
A.
when the page is not in the memory
B. when the page is in the memory
C. when the process enters the blocked state
D. when the process is in the ready state
Answer:Option A
Explanation :
Hide Answer
3. Which of the following will determine your choice of systems software

for your computer?
A. Is the applications software you want to use compatible with it ?
B. Is it expensive ?
C. Is it compatible with your hardware ?
D.
Both 1 and 3
Answer:Option D
Explanation :
Hide Answer
4. What is a shell ?
A. is a hardware component
B.
It is a command interpreter
C. It is a part in compiler
D. It is a tool in CPU scheduling
Answer:Option B
Explanation :
Hide Answer
5. Routine is not loaded until it is called. All routines are kept on disk in
a relocatable load format. The main program is loaded into memory &
is executed. This type of loading is called... ?
A. Static loading
B. Dynamic loading
C.
Dynamic linking
D. Overlays
Answer:Option C
Explanation :
Hide Answer
6. In the blocked state ?
A.
the processes waiting for I/O are found
B. the process which is running is found
C. the processes waiting for the processor are found
D. none of the above
Answer:Option A
Explanation :
Hide Answer
7. What is the memory from 1K - 640K called ?

A. Extended Memory
B. Normal Memory
C. Low Memory
D.
Conventional Memory
Answer:Option D
Explanation :
Hide Answer
8. Virtual memory is ..... ?

A. An extremely large main memory
B. An extremely large secondary memory
C.
An illusion of extremely large main memory
D. A type of memory used in super computers
Answer:Option C
Explanation :
Hide Answer
9. Which is not the state of the process ?

A. Blocked
B. Running
C. Ready
D.
Privileged
Answer:Option D
Explanation :
Hide Answer
10. The number of processes completed per unit time is known as.... ?
A. Output
B.
Throughput
C. Efficiency
D. Capacity
Answer:Option B
Explanation :
Hide Answer
11. What is Page stealing ?
A.
It takes page frames from other working sets
B. To increase the capacity of main memory
C. To speed up main memory read operation
D. None of above
Answer:Option A
Explanation :
Hide Answer
12. What is convoy effect ?
A.
All process waiting for the long process to complete
B. All process waiting for the small process to complete
C. Process in not present in main memory
D. None of above
Answer:Option A
Explanation :

Hide Answer
13. Aging is a technique ?

Used to increase the priority of processed that are waiting for long
A.
times
B. Used to decrease the priority that are waiting for long time
Used to increase the priority of processed that are currently
C.
running
D. Used to decrease the priority processes that are currently running
Answer:Option A
Explanation :
Hide Answer
14. Which of the following algorithm suffers from the Belady's anomly ?
A.
FIFO
B. LIFO
C. Optimal Algorithm
D. None of above
Answer:Option A
Explanation :
Hide Answer
15. Concurrent process are ?

A. Processes that do not overlap in time
B.
Process that overlap in time
C. Processes that are executed by the processor at the same time
D. None of above
Answer:Option B
Explanation :
Hide Answer
16. Which of the following disk scheduling strategies is likely to give the
best throughput ?
A.
Farthest cylinder next
B. Nearest Cylinder next
C. FCFS
D. Elevator algorithm
Answer:Option A
Explanation :
Hide Answer
17. Size of the virtual memory depends upon ?

A. Data Bus
B. Address Bus
C. Size of main memory
D. Memory buffer register
Answer:Option h
Explanation :
Hide Answer
18. Race around condition occurs when ?

Two processed unknowingly wait for resources that are help by
A.
each other
B.
Two process wait for same resources
C. All resources are shared
D. Two processes share the same shared resource
Answer:Option B
Explanation :
Hide Answer
19. The part of machine level instruction, which tells the central
processor what has to be done, is
A.
Operation code
B. address
C. Locator
D. Flip flop
Answer:Option A
Explanation :
Hide Answer
20. Correcting errors in a program is referred to as
A.
Debugging
B. bugging
C. Rectifying
D. modifying
Answer:Option A
Explanation :
Hide Answer
21. An assembler is used to translate a program written in

A. A Low Language
B. A high Language
C. Middle Language
D.
Assembly Language
Answer:Option D
Explanation :
Hide Answer
22. Round robin scheduling is essentially the preemptive version of

________.
A.
FIFO
B. Shortest job first
C. Shortes remaining
D. Longest time first
Answer:Option A
Explanation :
Hide Answer
23. Virtual memory is __________.

A. An extremely large main memory
B. An extremely large secondary memory
C.
An illusion of extremely large main memory
D. A type of memory used in super computers.
Answer:Option C
Explanation :
Hide Answer
24. Which is not the state of the process ?
A.
Privileged
B. Ready
C. Running
D. Blocked
Answer:Option A
Explanation :
Hide Answer
25. The number of processes completed per unit time is known as

__________.
A. output
B.
throughput
C. Efficiency
D. Capacity
Answer:Option B
Explanation :
Hide Answer
26. The mechanism that bring a page into memory only when it is
needed is called _____________
A. Sagmentation
B. Fragmentation
C.
Demand Paging
D. Page and Replacement
Answer:Option C
Explanation :
Hide Answer
27. PCB =
A. Program Control Block
B.
Process Control Block
C. Process Communication Block
D. None
Answer:Option B
Explanation :
Hide Answer
28. FIFO scheduling is ________.
A.
Non Preemptive Scheduling
B. Deadline Scheduling
C. Preemptive Scheduling
D. Fair share scheduling
Answer:Option A
Explanation :
Hide Answer
29. Which directory implementation is used in most Operating System?

A. Single level directory structure
B. Two level directory structure
C.
Tree directory structure
D. Acyclic directory structure
Answer:Option C
Explanation :
Hide Answer
30. The BankerÂ¿s algorithm is used
A.
to prevent deadlock in operating systems
B. to detect deadlock in operating systems
C. to rectify a deadlocked state
D. None
Answer:Option A
Explanation :

1. Which of the following helps in the generation of waveforms?
a) timer
b) inputs
c) outputs
d) memory
View Answer
Answer: a
Explanation: The embedded systems have a timing component called timer or counter
which helps in the timing reference for control sequence, provides system tick for the
operating system and also helps in the generation of waveforms for the serial port baud
rate generation.
2. Which bit size determines the slowest frequency?
a) counter size
b) pre-scalar value
c) counter
d) timer
View Answer
Answer: b
Explanation: The pre-scalar value determines the slowest frequency that can be
generated from a given clock input. Actually the bit size are determined by the pre-scalar
value and the conuter size.
3. Which bit size determines the maximum value of the counter-derived period?
a) counter size
b) pre-scalar value
c) bit size
d) byte size
View Answer
Answer: a
Explanation: The bit size are basically determined by its fundamental properties, that is,
the pre-scalar value and the counter size. The counter size determines the maximum
value of the counter derived period.
4. Which of the following timer is suitable for IBM PC?
a) IA-32
b) Intel 8253
c) Intel 64
d) 8051 timer
View Answer
Answer: b
Explanation: The Intel 8253 timer is suitable for the IBM PC. IA-32 and Intel 64 are the
offload timers used only for Intel. The 8051 timer is used for the timing program in 8051.
5. Which of the following is mode 0 in 8253?
a) interrupt on start count
b) interrupt for wait statement
c) interrupt on terminal count
d) no interrupt
View Answer
Answer: c
Explanation: The interrupt on the terminal count is known as mode 0 for the 8253. An
initial value is loaded into the count register and then starts to count down at the
frequency which is determined by the clock input. When the count reaches zero, an
interrupt is generated.
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6. Which determines the mode 1 in the Intel 8253?

a) interrupt on terminal count
b) programmable one-shot
c) rate generator
d) square wave rate generator
View Answer
Answer: b
Explanation: Programmable one-shot is also known as mode 1 in the Intel 8253. In
mode 1, a single pulse with a programmable duration is created first and then the pulse
length is loaded into the counter and when the external gate signal is high, the rising
edge starts the counter to count down to zero and the counter output signal goes high to
start the external pulse. When the counter reaches to zero, the counter output goes low
and thus the ending of the pulse.
7. Which mode of 8253 can provide pulse width modulation?
a) programmable one-shot
b) square wave rate generator
c) software triggered strobe
d) hardware triggered strobe
View Answer
Answer: a
Explanation: Mode 1 of the Intel 8253 can provide pulse width modulation for the power
control where the gate is connected to a zero crossing detector or a clock source.
8. Which of the following is the mode 3 in the Intel timer 8253?
a) rate generator
b) hardware triggered strobe
c) square wave rate generator
d) software triggered strobe
View Answer
Answer: a
Explanation: The rate generator is the mode 3 in Intel 8253 timer. The square wave
generator is the mode 4 and the hardware triggered strobe is the mode 5 in the Intel
8253 timer.
9. Which of the following determines the rate generation?
a) divide by N
b) multiply by N
c) addition by N
d) subtraction by N
View Answer
Answer: a
Explanation: The rate generator mode is determined by the mode 3 with the Intel 8253.
It is a simple divide by N mode where N is the initial value loaded into the counter.
10. Which mode of the Intel 8253 timer can generate a square wave?
a) mode 1
b) mode 2
c) mode 3
d) mode 4
View Answer
Answer: d
Explanation: The mode 4 is the square wave generator. This mode is similar to mode 3
except that the waveform is a square wave
1. Which mode of the Intel timer 8253 provides a software watchdog timer?
a) rate generator
b) hardware triggered strobe
c) square wave rate generator
d) software triggered strobe
View Answer
Answer: d
Explanation: The software triggered strobe can be used as a software-based watchdog
timer in which the output is connected to a non maskable interrupt.
2. Which of the following mode is similar to the mode 4 of the 8253 timer?
a) mode 5
b) mode 6
c) mode 0
d) mode 1
View Answer
Answer: a
Explanation: The mode 5 or the hardware triggered strobe is similar to the mode 4 or the
square wave rate generator expect that the retriggering is done by the external gate pin.
3. Which pin of 8253 is used for the generation of an external interrupt signal?
a) OUT pin
b) IN pin
c) Interrupt pin
d) Ready pin
View Answer
Answer: a
Explanation: The Intel 8253 timer has no interrupt pins. Therefore, the timer OUT pin is
used to generate an external interrupt signal.
4. Which timer architecture can provide a higher resolution than Intel 8253?
a) Intel 8253
b) Intel 8254
c) 8051 timer
d) MC68230
View Answer
Answer: d
Explanation: The Intel 8253 and 8254 have same pin configuration and functions. 8051
timer is a programmable timer in the 8051 microcontroller. The MC68230 timer
developed by Motorola can provide a powerful timer architecture which can provide
higher resolution than the Intel 8253.
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Factory Design Pattern
5. How many bit architecture does MC68230 have?

a) 16
b) 24
c) 32
d) 40
View Answer
Answer: b
Explanation: The MC68230 timer have a 24-bit architecture which is split into three 8-bit
components because of the 8-bit bus in the MC68000 CPU.
6. How many bit bus does MC68230 have?
a) 2
b) 4
c) 8
d) 16
View Answer
Answer: c
Explanation: The MC68230 timer have a 24-bit architecture which is split into three 8-bit
components because of the 8-bit bus which is used for the communication with the host
processor like MC68000 CPU which have an 8-bit architecture.
7. Which of the following is a timer processor?
a) Intel 8253
b) MC146818
c) MC68332
d) Intel 8259
View Answer
Answer: c
Explanation: Intel 8253 and 8259 are timers or counters which supports the processors.
MC146818 is a real-time clock. MC68332 which is developed by Motorola is a 32 bit
timer processor which can support MC68020.
8. What is the running frequency of MC68332?
a) 12 MHz
b) 14 MHz
c) 16 MHz
d) 18 MHz
View Answer
Answer: c
Explanation: The running frequency of the MC68332 is 16 MHz.
9. Which of the following is a real time clock?
a) MC146818
b) 8253
c) 8259
d) 8254
View Answer
Answer: a
Explanation: The 8253, 8254 and 8259 are timers or counters developed by Intel
whereas MC146818 is a real-time clock.
1. Real time systems can be classified into ...

a) Soft
b) Hard
c) Firm
d) All of the above
2. A hard real-time system is one in which ...
a) Failure to meet a single deadline may lead to complete and catastrophic system
failure.
b) Missing more than a few may lead to complete and catastrophic system failure.
c) Performance is degraded but not destroyed by failure to meet response-time
constraints.
d) None of the above
3. Which of the following is/are synchronous aperiodic event ...
a) Garbage collection
b) Externally generated exception
c) Cyclic code
d) Branch instruction
4. Which of the following is/are asynchronous periodic event ...
a) Typical branch instruction
b) Regular, but not fixed-period interrupt
c) Clock-generated interrupt
d) Traps
5. Which of the following pair of CPU utilization % and Zone type is/are correct ...
a) 83–99, questionable
b) 70–82, dangerous
c) 26–50, very safe
6. Disciplines that impact on real-time systems engineering is/are...
a) Control Theory
b) Operations Research
c) Both a and c
7. Which of following regarding RTOS is correct/ not misconception...
a) The study of real-time systems is mostly about scheduling theory.
b) There are no universal, widely accepted methodologies for real-time systems
specification
and design.
c) Rate-monotonic analysis has solved “the real-time problem.
8. Overall system utilization U= ...
a) i
b) i/pi
c) Both a and c
9. A system is said to be time-overloaded if...
a) U ≥ 100%
b) U ≤100%
c) U < 100%
d) U> 100%
10. Which of the following statement is true?
a) Any occurrence that causes the program counter to change non-sequentially is
considered
a change of flow-of-control
b) The release time is the time at which an instance of a scheduled task is ready to run,
and is
generally associated with an interrupt
c) Both a and c
11. Which of the following represent a possible change in flow-of-control?
a) Invocation of procedures in C
b) Instantiation of an object
c) If-then, goto, and case statements
d) All of the above
12. The (CPU) utilization or time-loading factor, U, is a ...
a) Measure of the percentage of idle processing
b) Measure of the percentage of non-idle processing
c) Both a and b
13. Which of the following is example of RTOS?
a) Inertial measurement system for an aircraft
b) System used to control a set of traffic lights at a four-way traffic intersection
c) System that controls all aspects of the bottling of jars of pasta sauce
d) All of the above
14. Many real-time systems utilize time-stamping and global clocks for...
a) Synchronization
b) Task initiation
c) Data marking
d) All of the above
15. Real-time systems are often ...
a) Reactive systems
b) Embedded systems
c) Data marking
d) a and b
16. Which of the following is/are system wide bus?
a) Power
b) Address
c) Data
d) All of the above
17. In signaling between devices is it is important to have a mechanism for “recording”
the appearance of that signal for later processing. This process is called ...
a) Latching
b) Tristate logic
c) Triggering
18. FireWire technology was originally developed by...
a) Microsoft
b) Apple
c) Google
19. Using EDF algorithm practically, it is impossible to achieve 100 percent utilization
due to
__________.
a) the cost of context switching
b) interrupt handling
c) power consumption
20. There are generally …… kinds of instructions.
a) 5
b) 4
c) 7
d) 6
21. In rate monotonic scheduling, a process with a shorter period is assigned
__________
a) a higher priority
b) a lower priority
c) higher & lower priority
22. A single 1394 port can be used to connect up …….. External devices.
a) 58
b) 64
c) 62
d) 63
23. The CISC is based on which of the following principle.
a) Complexity handled by the compiler and software
b) Instructions executed directly by hardware
c) There are multiple instructions and addressing modes
d) Highly pipelined design
24. Which of the following require special data-movement instructions
a) Memory-Mapped Input/Output
b) Programmed Input/Output
c) Direct Memory Access
25. Upon receipt of the interrupt signal, the contents of the program counter are saved
to a designated memory location called the…
a) Status register
b) Interrupt-handler location
c) Interrupt return location
26. The interrupt vector contains the…
a) Bit map of all pending interrupts
b) Value of the lowest interrupt that will currently be honored
c) Identity of the highest-priority interrupt request
27. Intel 82093AA I/O Advanced Programmable Interrupt Controller supports ……
programmable interrupts
a) 24
b) 32
c) 16
28. Interrupt register contains...
a) Identity of the highest-priority interrupt request
b) Bit map of all pending (latched) interrupts
c) Value of the lowest interrupt that will currently be honored
29. Watchdog timers are used to ensure that...
a) CPU continues to function
b) Task initiation
c) Certain devices are serviced at regular intervals
d) Both a and c
30. The entry of all the PCBs of the current processes is in __________
a) Process Register
b) Program Counter
c) Process Table
d) Process Unit
31. Which of the following provides time period for the context switch?
a. timer
b. counter
c. time slice
d. time machine
Answer: (c).time slice

32. Which of the following can periodically trigger the context switch?
a. software interrupt
b. hardware interrupt
c. peripheral
d. memory
Answer: (b).hardware interrupt
33. Which interrupt provides system clock in the context switching?
a. software interrupt
b. hardware interrupt
c. peripheral
d. memory
Answer: (b).hardware interrupt
34. The special tale in the multitasking operating system is also known as
a. task control block
b. task access block
c. task address block
d. task allocating block
Answer: (a).task control block
35. Which of the following stores all the task information that the system requires?
a. task access block

b. register
c. accumulator
d. task control block
Answer: (d).task control block
36. Which of the following contains all the task and their status?
a. register
b. ready list
c. access list
d. task list
Answer: (b).ready list
37. Which determines the sequence and the associated task’s priority?
a. scheduling algorithm
b. ready list
c. task control block
d. application register
Answer: (a).scheduling algorithm
38. Which can control the memory usage?
a. operating system
b. applications
c. hardware
d. kernel
Answer: (d).kernel
39. Which can control the memory sharing between the tasks?
a. kernel
b. application
c. software
d. OS
Answer: (a).kernel
40. Which of the following can implement the message passing and control?
a. application software
b. operating system
c. software
d. kernel
Answer: (a).application software
MULTIPLE CHOICE QUESTIONS ON EMBEDDED SYSTEMS
1. Which of the following is a coprocessor of 80386?
a) 80387
b) 8087
c) 8089
d) 8088
View Answer
Answer: a
Explanation: 80386 have 80387 as a floating point arithmetic coprocessor which can perform
various floating point calculations.
a) microprocessor
b) microcontroller
c) coprocessor
d) controller
View Answer
Answer: c
Explanation: The coprocessor can perform signal processing, floating point arithmetics,
encryption etc.
3. Which is the coprocessor of 8086?
a) 8087
b) 8088
c) 8086
d) 8080
View Answer
Answer: a
Explanation: 8087 is the coprocessor for both 8086 and 8088. 8089 is also a coprocessor of 8086
and 80888.
4. Which of the following is a coprocessor of Motorola 68000 family?
a) 68001
b) 68011
c) 68881
d) 68010
View Answer
Answer: c
Explanation: The 68881 coprocessor of Motorola provides floating point arithmetics.
5. Which of the following processors can perform exponential, logarithmic and trigonometric
functions?
a) 8086
b) 8087
c) 8080
d) 8088
View Answer
Answer: b
Explanation: 8087 is a coprocessor which can perform all the mathematical functions including
addition, subtraction, multiplication, division, exponential, logarithmic, trigonometric etc. 8086,
8080 and 8088 are microprocessors which require the help of a coprocessor for floating point
arithmetic.
6. How many stack register does an 8087 have?
a) 4
b) 8
c) 16
d) 32
View Answer
Answer: b
Explanation: The 8087 coprocessor does not have a main register set but they have an 8-level
deep stack register from st0 to st7.
7. Which of the following processor can handle infinity values?
a) 8080
b) 8086
c) 8087
d) 8088
View Answer
Answer: c
Explanation: 8087 is a coprocessor which can handle infinity values with two types of closure
known as affine closure and projective closure.
8. Which coprocessor supports affine closure?
a) 80187
b) 80287
c) 80387
d) 8088
View Answer
Answer: b
Explanation: 80287 uses an affine closure for infinity values whereas 80387 and 80187 support
projective closure for infinity values.
9. Which one is the floating point coprocessor of 80286?
a) 8087
b) 80187
c) 80287
d) 80387
View Answer
Answer: c
Explanation: 80286 supports 80287 as its floating point coprocessor which helps in floating point
calculations.
10. How many pins does 8087 have?
a) 40 pin DIP
b) 20 pin DIP
c) 40 pins
d) 20 pins
View Answer
Answer: a
Explanation: All 8087 models have a 40 pin DIP which is operated in 5V.
11. What is the clock frequency of 8087?
a) 10 MHz
b) 5 MHz
c) 6 MHz
d) 4 MHz
View Answer

a) 1’s complement
b) 2’s complement
c) decimal
d) gray
View Answer
Answer: b
Explanation: In a coprocessor, negative numbers are stored in 2’s complement with its leftmost
sign bit of 1 whereas positive numbers are stored in the form of true value with its leftmost sign
bit of 0.
13. How many bits are used for storing signed integers?
a) 2
b) 4
c) 8
d) 16
View Answer
Answer: d
Explanation: Signed integers in a coprocessor are stored as 16-bit word, 32-bit double word or
64-bit quadword.
14. Which of the processor has an internal coprocessor?
a) 8087
b) 80287
c) 80387
d) 80486DX
View Answer
Answer: d
Explanation: 8087 is an external IC designed to operate with the 8088/8086 processor but
80486DX is an on-chip coprocessor that is, it does not require an extra integrated chip for
floating point arithmetics.
15. What are the two major sections in a coprocessor?
a) control unit and numeric control unit
b) integer unit and control unit

c) floating point unit and coprocessor unit
d) coprocessor unit and numeric control unit
View Answer
Answer: a
Explanation: Control unit interfaces the coprocessor with its main microprocessor whereas
numeric control unit can execute the coprocessor instructions
15. Which are the processors based on RISC?
a) SPARC
b) 80386
c) MC68030
d) MC68020
View Answer
Answer: a
Explanation: SPARC and MIPS processors are the first generation processors of RISC
architecture.
16. What is 80/20 rule?
a) 80% instruction is generated and 20% instruction is executed
b) 80% instruction is executed and 20% instruction is generated
c) 80%instruction is executed and 20% instruction is not executed
d) 80% instruction is generated and 20% instructions are not generated
View Answer
Answer: a
Explanation: 80% of instructions are generated and only 20% of the instruction set is executed
that is, by simplifying the instructions, the performance of the processor can be increased which
lead to the formation of RISC that is reduced instruction set computing.
17. Which of the architecture is more complex?
a) SPARC
b) MC68030
c) MC68030
d) 8086
View Answer
Answer: a
Explanation: SPARC have RISC architecture which has a simple instruction set but MC68020,
MC68030, 8086 have CISC architecture which is more complex than CISC.
18. Which is the first company who defined RISC architecture?
a) Intel
b) IBM
c) Motorola
d) MIPS
View Answer
Answer: b
Explanation: In 1970s IBM identified RISC architecture.
19. Which of the following processors execute its instruction in a single cycle?
a) 8086
b) 8088
c) 8087
d) MIPS R2000
View Answer
Answer: d
Explanation: MIPS R2000 possess RISC architecture in which the processor executes its
instruction in a single clock cycle and also synthesize complex operations from the same reduced
instruction set.
20. How is memory accessed in RISC architecture?
a) load and store instruction
b) opcode instruction
c) memory instruction
d) bus instruction
View Answer
Answer: a
Explanation: The data of memory address is loaded into a register and manipulated, its contents
are written out to the main memory.
21. Which of the following has a Harvard architecture?

a) EDSAC
b) SSEM
c) PIC
d) CSIRAC
View Answer
Answer: c
Explanation: PIC follows Harvard architecture in which the external bus architecture consist of
separate buses for instruction and data whereas SSEM, EDSAC, CSIRAC are stored program
architecture.
22. Which of the following statements are true for von Neumann architecture?
a) shared bus between the program memory and data memory
b) separate bus between the program memory and data memory
c) external bus for program memory and data memory
d) external bus for data memory only
View Answer
Answer: a
Explanation: von Neumann architecture shares bus between program memory and data memory
whereas Harvard architecture have a separate bus for program memory and data memory.
23. What is CAM stands for?
a) content-addressable memory
b) complex addressable memory
c) computing addressable memory
d) concurrently addressable memory
View Answer
Answer: a
Explanation: Non-von Neumann architecture is based on content-addressable memory.
24. Which of the following processors uses Harvard architecture?
a) TEXAS TMS320
b) 80386
c) 80286
d) 8086
View Answer
Answer: a
Explanation: It is a digital signal processor which have small and highly optimized audio or
video processing signals. It possesses multiple parallel data bus.
25. Which company further developed the study of RISC architecture?
a) Intel
b) Motorola
c) university of Berkeley
d) MIPS
View Answer
Answer: c
Explanation: The University of Berkeley and Stanford university provides the basic architecture
model of RISC.
26. Princeton architecture is also known as
a) von Neumann architecture
b) Harvard
c) RISC
d) CISC
View Answer
Answer: a
Explanation: The von Neumann architecture is also known as von Neumann model or Princeton
architecture.
27. Who coined the term RISC?
a) David Patterson
b) von Neumann
c) Michael J Flynn
d) Harvard
View Answer
Answer: a
Explanation: David Patterson of Berkeley university coined the term RISC whereas Michael J
Flynn who first views RISC.

28. Which of the following is an 8-bit RISC Harvard architecture?
a) AVR
b) Zilog80
c) 8051
d) Motorola 6800
View Answer
Answer: a
Explanation: AVR is an 8-bit RISC architecture developed by Atmel. Zilog80, 8051, Motorola
6800 are having CISC architectures.
29. Which of the following processors has CISC architecture?
a) AVR
b) Atmel
c) Blackfin
d) Zilog Z80
View Answer
Answer: d
Explanation: Zilog80 have CISC architecture whereas AVR, Atmel and blackfin possess RISC
architecture
30. Which is the most basic non-volatile memory?
a) Flash memory
b) PROM
c) EPROM
d) ROM
View Answer
Answer: d
Explanation: The basic non-volatile memory is ROM or mask ROM, and the content of ROM is
fixed in the chip which is useful in firmware programs for booting up the system.
31. Who has invented flash memory?
a) Dr.FujioMasuoka
b) John Ellis
c) Josh Fisher
d) John Ruttenberg
View Answer
Answer: a
Explanation: Flash memory is invented by Dr. FujioMasuoka at Toshiba in the 1980s which are a
non-volatile memory.
32. Which of the following is serial access memory?
a) RAM
b) Flash memory
c) Shifters
d) ROM
View Answer
Answer: c
Explanation: The memory arrays are basically divided into three which are random access
memory, serial access memory, and content address memory. Serial access memory is divided
into two, theses are shifters and queues.
33. Which is the early form of non-volatile memory?
a) magnetic core memory
b) ferrimagnetic memory
c) anti-magnetic memory
d) anti-ferromagnetic
View Answer
Answer: a
Explanation: The early form of non-volatile memory is known as magnetic core memory in
which the ferromagnetic ring was magnetised to store data.
34. Which of the following memories has more speed in accessing data?
a) SRAM
b) DRAM
c) EPROM
d) EEPROM
View Answer
Answer: a
Explanation: SRAM have more speed than DRAM because it has 4 to 6 transistors arranged as
flip-flop logic gates, that is it can be flipped from one binary state to another but DRAM has a
small capacitor as its storage element.
35. In which memory, the signals are multiplexed?
a) DRAM
b) SRAM
c) EPROM
d) EEPROM
View Answer
Answer: a
Explanation: The signals in address bus are multiplexed with DRAM non-multiplexed with
SRAM.
36. How many main signals are used with memory chips?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: b
Explanation: The main signals associated with memory chips are four. These are the signals
associated with address bus, data bus, chip select signals, and control signals for read and write
operations.
37. What is the purpose of address bus?
a) to provide data to and from the chip
b) to select a specified chip
c) to select a location within the memory chip
d) to select a read/write cycle
View Answer
Answer: c
Explanation: Address bus is used to choose a particular location in the memory chip. Data bus is
used to provide data to and from the chip. Chip select signals are used to select a particular chip
within the memory.
38. Which are the two main types of processor connection to the motherboard?
a) sockets and slots
b) sockets and pins
c) slots and pins
d) pins and ports
View Answer
Answer: a
Explanation: The type of processor which connects to a socket on the bottom surface of the chip
that connects to the motherboard by Zero Insertion Force Socket. Intel 486 is an example of this
type of connection. The processor slot is one which is soldered into a card, which connects to a
motherboard by a slot. Example for slot connection is Pentium 3.
39. Which of the following has programmable hardware?
a) microcontroller
b) microprocessor
c) coprocessor
d) FPGA
View Answer
Answer: d
Explanation: Field programmable gate arrays is a type of multi-core architecture whose hardware
function can be programmed by using hardware design tools.
40. Who invented TriMedia processor?
a) Intel
b) IBM
c) Apple
d) NXP Semiconductor
View Answer
Answer: d
Explanation: TriMedia is a VLIW processor from NXP Semiconductor in Netherlands. It
possesses a Harvard architecture CPU for video and audio applications
41. Which of the following have a 16 Mbytes addressed range?

a) PowerPC
b) M68000
c) DSP56000
d) TMS 320
View Answer
Answer: b
Explanation: The M68000 family has a 16 Mbyte addressing range. The PowerPC family has a
larger 4 Gbyte range and the DSP56000 has a 128-kilo word address space.
42. Which of the following can destroy the accuracy in the algorithms?
a) delays
b) error signal
c) interrupt
d) mmu
View Answer
Answer: a
Explanation: The delays occurring in the memory management unit can destroy the accuracy in
the algorithms and in order to avoid this, the linear addressing range should be increased.
43. How many numbers of ways are possible for allocating the memory to the modular blocks?
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: c
Explanation: Most of the systems have a multitasking operating system in which the software
consist of modular blocks of codes which run under the control of the operating system. There
are three ways for allocating memory to these blocks. The first way distributes the block in a
predefined way. The second way for allocating memory includes relocation or position
independency in the software and the other way of allocating memory to the block is the address
translation in which the logical address is translated to the physical address.
44. Which of the following is replaced with the absolute addressing mode?
a) relative addressing mode
b) protective addressing mode
c) virtual addressing mode
d) temporary addressing mode
View Answer
Answer: a
Explanation: The memory allocation of the modular blocks can be done by the writing the
software program in relocatable or position independent manner which can execute anywhere in
the memory map, but relocatable code must have the same address between its data and code
segments. This is used to avoid the use of absolute addressing modes which is replaced by the
relative addressing modes.
45. What is the main purpose of the memory management unit?
a) address translation
b) large storage
c) reduce the size
d) provides address space
View Answer
Answer: a
Explanation: The memory management unit handles with physical addresses. Therefore, the
virtual or the logical address is first translated to the physical address.
46. Which of the following provides stability to the multitasking system?
a) memory
b) DRAM
c) SRAM
d) Memory partitioning
View Answer
Answer: d
Explanation: The memory partitioning provides stability to the multitasking system so that the
errors within one task will not corrupt the other tasks.
47. Which of the following is used by the M68000 family?
a) M68000
b) 80386
c) 8086
d) 80286
View Answer
Answer: a
Explanation: The M68000 uses memory partitioning by the use of function code or by the
combination of superscalar signals and the Harvard architecture.
48. What can be done for the fine grain protection of the processor?
a) add extra description bit
b) add error signal
c) add wait stage
d) remains unchanged
View Answer
Answer: a
Explanation: The finer grain protection of memory management is achieved by the addition of
extra description bit to an address to declare its status. The memory management unit can detect
an error if the task attempts to access memory that has not been allocated to it or a certain kind of
mismatch occurs.
49. Which of the following technique is used by the UNIX operating system?
a) logical address memory
b) physical address memory
c) virtual memory technique
d) translational address
View Answer
Answer: c
Explanation: In the workstation and in the UNIX operating system virtual memory technique is
frequently used in which the main memory is divided into different segments and pages. These
pages will have a virtual address which can increase the address spacing.
50. Which of the following consist two lines of legs on both sides of a plastic or ceramic body?
a) SIMM
b) DIMM
c) Zig-zag
d) Dual in-line
View Answer
Answer: d
Explanation: The dual-in-line package consists of two lines of legs on both sides of the plastic or
ceramic. Most commonly used is BIOS EPROMs, DRAM and SRAM.
51. Which of the following can transfer multiple bits of data simultaneously?
a) serial port
b) sequential port
c) concurrent unit
d) parallel port
View Answer
Answer: d
Explanation: The parallel port can transfer multiple bits of data simultaneously. It provides the
input or output binary data with a single bit allocated to each pin within the port.
52. Which of the following are interfaced as inputs to the parallel ports?
a) LEDs
b) switch
c) alphanumeric display
d) seven segmented display
View Answer
Answer: b
Explanation: The LEDs, alphanumeric displays, seven segment displays are interfaced for the
output whereas the switch is an input port.
53. Which of the following are interfaced as the outputs to the parallel ports?
a) keyboards
b) switches
c) LEDs
d) knobs
View Answer
Answer: c
Explanation: The keyboards, switches, and knobs are used as output whereas the LEDs are used
as the input port.
54. How many registers are there to control the parallel port in the basic form?
a) 1
b) 3
c) 2
d) 5
View Answer
Answer: c
Explanation: The basic operation of the parallel port dealt with two types of registers which are
called data direction register and the data register.
55. Which of the following is also known as tri-state?
a) output port
b) input port
c) parallel port
d) output-input port
View Answer
Answer: a
Explanation: The progression in the parallel ports provides a third register or an individual
control bit which can make the pin in a high impedance state. An output port which can do this is
also known as tri-state, that is, logic high, logic low and a high impedance state.
56. How buffers are enabled in the parallel ports?
a) by the data register
b) by data direction register
c) by individual control register
d) by data and individual control register
View Answer
Answer: b
Explanation: The implementation of parallel port uses a couple of buffers which are enabled by
the data direction register by setting the corresponding bit of the register.
57. Which of the following registers offers high impedance?

a) data register
b) data direction register
c) individual control bit
d) data register and data direction register
View Answer
Answer: c
Explanation: The register which offers high impedance is the individual control bit or the third
register which can be implemented by switching off both the buffers and putting their
connections to the pin which offers high impedance.
58. Which of the following can be used as a chip select?
a) multifunction I/O port
b) parallel port
c) DMA port
d) memory port
View Answer
Answer: a
Explanation: The multifunction I/O port can also be used a chip select for the memory design.
The function that the pin performs is set up internally through the use of a function register
which internally configures how the external pins are connected internally.
59. Which of the following is necessary for the parallel input-output port?
a) inductor
b) pull-up resistor
c) push-up resistor
d) capacitor
View Answer
Answer: b
Explanation: The I/O port needs an external pull-up resistor. In some devices, it offers internally.
If it is not provided, it can cause incorrect data on reading the port and it prevents the port from
turning off an external device.
60. Which of the following can be described as general-purpose?
a) multifunction I/O port

b) input port
c) DMA port
d) output port
View Answer
Answer: a
Explanation: The multifunction I/O ports can be described as the general-purpose and it can be
shared with other peripherals
61. What does UART stand for?
a) universal asynchronous receiver transmitter
b) unique asynchronous receiver transmitter
c) universal address receiver transmitter
d) unique address receiver transmitter
View Answer
Answer: a
Explanation: The UART or universal asynchronous receiver transmitter is used for the data
transmission at a predefined speed or baud rate.
62. How is data detected in a UART?
a) counter
b) timer
c) clock
d) first bit
View Answer
Answer: c
Explanation: The data can be detected by the local clock reference which is generated from the
baud rate generator.
63. Which of the signal is set to one, if no data is transmitted?
a) READY
b) START
c) STOP
d) TXD
View Answer
Answer: d
Explanation: The TXD signal goes to logic one, when no data is transmitted. When data
transmits, it sets to logic zero.
64. What rate can define the timing in the UART?
a) bit rate
b) baud rate
c) speed rate
d) voltage rate
View Answer
Answer: b
Explanation: The timing is defined by the baud rate in which both the transmitter and receiver
are used. The baud rate is supplied by the counter or an external timer called baud rate generator
which generate a clock signal.
65. How is baud rate supplied?
a) baud rate voltage
b) external timer
c) peripheral
d) internal timer
View Answer
Answer: b
Explanation: The baud rate is supplied by the counter or an external timer called baud rate
generator which generate a clock signal.
66. Which is the most commonly used UART?
a) 8253
b) 8254
c) 8259
d) 8250
View Answer
Answer: d
Explanation: The Intel 8253, 8254 and 8259 are timers whereas Intel 8250 is a UART which is
commonly used.
67. Which company developed 16450?
a) Philips
b) Intel
c) National semiconductor
d) IBM
View Answer
Answer: c
Explanation: The Intel 8250 is replaced by the 16450 and 16550 which are developed by the
National Semiconductors. 16450 is a chip which can combines all the PC’s input output devices
into a single piece of silicon.
68. What does ADS indicate in 8250 UART?
a) address signal
b) address terminal signal
c) address strobe signal
d) address generating signal
View Answer
Answer: b
Explanation: The ADS is address strobe signal and is working as active low in 8250 UART. The
ADS signal is used to latch the address and chip select signals while a processor access.
69. Which of the following signals are active low in the 8250 UART?
a) BAUDOUT
b) DDIS
c) INTR
d) MR
View Answer
Answer: a
Explanation: The BAUDOUT signal is active low whereas DDIS, INTR and MR are active high
in the 8250 UART. BAUDOUT is the clock signal from the transmitter part of the UART. DDIS
signal goes low when the CPU is reading data from the UART. INTR is the interrupt pin. MR is
the master reset pin.
70. Which of the signal can control bus arbitration logic in 8250?
a) MR
b) DDIS
c) INTR
d) RCLK
View Answer
Answer: b
Explanation: DDIS signal goes low when the CPU is reading data from the UART and it also
controls the bus arbitration logic
71. Which of the following can be used for long distance communication?
a) I2C
b) Parallel port
c) SPI
d) RS232
View Answer
Answer: d
Explanation: A slightly different serial port called RS232 is used for long distance
communication, otherwise the clock may get skewed. The low voltage signal also affect the long
distance communication.
72. Which of the following can affect the long distance communication?
a) clock
b) resistor
c) inductor
d) capacitor
View Answer
Answer: a
Explanation: For small distance communication, the clock signal which allows a synchronous
transmission of data is more than enough, and the low voltage signal of TTL or CMOS is
sufficient for the operation. But for long distance communication, the clock signal may get
skewed and the low voltage can be affected by the cable capacitance. So for long distance
communication RS232 can be used.
73. Which are the serial ports of the IBM PC?

a) COM1
b) COM4 and COM1
c) COM1 and COM2
d) COM3
View Answer
Answer: c
Explanation: The IBM PC has one or two serial ports called the COM1 and the COM2, which
are used for the data transmission between the PC and many other peripheral units like printer,
modem etc.
74. Which of the following can provide hardware handshaking?
a) RS232
b) Parallel port
c) Counter
d) Timer
View Answer
Answer: a
Explanation: In RS232, several lines are used for transmitting and receiving data and these also
provide a control for the hardware handshaking.
75. Which of the following have an asynchronous data transmission?
a) SPI
b) RS232
c) Parallel port
d) I2C
View Answer
Answer: b
Explanation: The data is transmitted asynchronously in RS232 which enhance long distance
communication, whereas SPI, I2C offers short distance communication, and therefore, they are
using synchronous data transmission.
76. How many areas does the serial interface have?
a) 1
b) 3
c) 2
d) 4
View Answer
Answer: c
Explanation: The serial interface is divided into two, physical interface and the electrical
interface.
77. The RS232 is also known as
a) UART
b) SPI
c) Physical interface
d) Electrical interface
View Answer
Answer: d
Explanation: The RS232 is also known as the physical interface and it is also known as EIA232.
78. How much voltage does the MC1489 can take ?
a) 12V
b) 5V
c) 3.3V
d) 2.2V
View Answer
Answer: b
Explanation: The MC1489 is a interface chip which can take a 5V and generate internally the
other voltages which are needed to meet the interface specification.
79. Which of the following is not a serial protocol?
a) SPI
b) I2C
c) Serial port
d) RS232
View Answer
Answer: d
Explanation: The RS232 is a physical interface. It does not follow the serial protocol.
80. Which of the following is an ideal interface for LCD controllers?
a) SPI
b) parallel port
c) Serial port
d) M-Bus
View Answer
Answer: d
Explanation: M-Bus or Motorola Bus is an ideal interface for LCD controllers, A/D converters,
EEPROMs and many other components which can benefit faster transmission.
81. Which of the following works by dividing the processor’s time?
a) single task operating system
b) multitask operating system
c) kernel
d) applications
View Answer
Answer: b
Explanation: The multitasking operating system works by dividing the processor’s time into
different discrete time slots, that is, each application requires a defined number of time slots to
complete its execution.
82. Which of the following decides which task can have the next time slot?
a) single task operating system
b) applications
c) kernel
d) software
View Answer
Answer: c
Explanation: The operating system kernel decides which task can have the next time slot. So
instead of the task executing continuously until completion, the execution of the processor is
interleaved with the other tasks.
83. Which of the following controls the time slicing mechanism in a multitasking operating
system?
a) kernel
b) single tasking kernel
c) multitasking kernel
d) application manager
View Answer
Answer: c
Explanation: The multitasking operating systems are associated with the multitasking kernel
which controls the time slicing mechanism.
84. Which of the following provides time period for the context switch?
a) timer
b) counter
c) time slice
d) time machine
View Answer
Answer: c
Explanation: The time period required for each task for execution before it is stopped and
replaced during a context switch is known as the time slice.
85. Which of the following can periodically trigger the context switch?
a) software interrupt
b) hardware interrupt
c) peripheral
d) memory
View Answer
Answer: b
Explanation: The time period required for each task for execution before it is stopped and
replaced during a context switch is known as the time slice. These are periodically triggered by a
hardware interrupt from the system timer.
86. Which interrupt provides system clock in the context switching?
a) software interrupt
b) hardware interrupt
c) peripheral
d) memory
View Answer
Answer: b
Explanation: The multitasking operating systems deals with the multitasking kernel which
controls the time slicing mechanism and the time period required for each task for execution
before it is stopped and replaced during a context switch is known as the time slice which are
periodically triggered by a hardware interrupt from the system timer. This hardware interrupt
provides the system clock in which several interrupts are executed and counted before a context
switch is performed.
87. The special tale in the multitasking operating system is also known as
a) task control block
b) task access block
c) task address block
d) task allocating block
View Answer
Answer: a
Explanation: When a context switch is performed, the current program or task is interrupted, so
the processor’s registers are saved in a special table which is known as task control block.
88. Which of the following stores all the task information that the system requires?
a) task access block
b) register
c) accumulator
d) task control block
View Answer
Answer: d
Explanation: The task control block stores all the task information that the system requires and
this is done when the context switch is performed so that the currently running program is
interrupted.
89. Which of the following contains all the task and their status?
a) register
b) ready list
c) access list
d) task list
View Answer
Answer: b
Explanation: The ‘ready’ list possesses all the information regarding a task, that is, all the task
and its corresponding status which is used by the scheduler to decide which task should execute
in the next time slice.
90. Which determines the sequence and the associated task’s priority?
a) scheduling algorithm
b) ready list
c) task control block
d) application register
View Answer
Answer: a
Explanation: The scheduling algorithm determines the sequence and an associated task’s priority.
It also determines the present status of the task
91. Which of the following can be used to refer to entities within the RTOS?
a) threads
b) kernels
c) system
d) applications
View Answer
Answer: a
Explanation: The threads and processes can be used to refer to entities within the RTOS. They
provide an interchangeable replacement for the task. They have a slight difference in their
function.
92. Which of the following defines the set of instructions loaded into the memory?
a) process
b) task
c) thread
d) system hardware
View Answer
Answer: b
Explanation: The task can be defined by the set of instructions which is loaded into the memory
and it can split into two or more tasks.
3. Which of the following uses its own address space?
a) thread
b) process
c) task
d) kernel
View Answer
Answer: a
Explanation: Threads uses a shared memory space and it uses the memory space of the process.
94. Which of the following does not uses a shared memory?
a) process
b) thread
c) task
d) kernel
View Answer
Answer: a
Explanation: The program in execution is known as the process. The process does not share the
memory space but the threads have a shared memory address. When the CPU switches from
process to another, the current information is stored in the process descriptor.
95. Which of the following can own and control the resources ?
a) thread
b) task
c) system
d) peripheral
View Answer
Answer: b
Explanation: The task and process have several characteristics and one such is that the task or
process can own or control resources and it has threads of execution which are the paths through
the code.
96. Which can be supported if the task or process maintains a separate data area for each thread?
a) single thread system
b) mono thread system
c) multiple threads
d) dual threads
View Answer
Answer: c
Explanation: The multiple threads can be supported only if the process or task can maintain a
separate data areas for each thread.
97. Which of the following possesses threads of execution?
a) process
b) thread
c) kernel
d) operating system
View Answer
Answer: a
Explanation: The process has threads of execution which are the paths through the code.
98. Which of the following is inherited from the parent task?
a) task
b) process
c) thread
d) kernel
View Answer
Answer: c
Explanation: The threads are a part of the process, that is, it uses a shared memory of the process
and therefore said that its resources are inherited from the parent process or task.
99. Which term is used to encompass more than a simple context switch?
a) process
b) single thread system
c) thread
d) multithread
View Answer
Answer: a
Explanation: The process includes the additional information which is used to encompass more
than a simple context switch. This is similar to the task switching, that is why it is said that
process and task are interchangeable.
100. Which can be considered as the lower level in the multitasking operating system?
a) process
b) task
c) threads
d) multi threads
View Answer
Answer: c
Explanation: In the multitasking operating system, the process and tasks form the higher level
whereas the thread is the lower level. But in a simple operating system, there is no difference
between the context switch of thread and the process
101. Which of the following are the pin efficient method of communicating between other
devices?
a) serial port
b) parallel port
c) peripheral port
d) memory port
View Answer
Answer: a
Explanation: The serial ports are considered to be the pin efficient method of communication
between other devices within an embedded system.
102. Which of the following depends the number of bits that are transferred?
a) wait statement
b) ready statement
c) time
d) counter
View Answer
Answer: c
Explanation: The time taken for the data transmission within the system depends on the clock
frequency and the number of bits that are transferred.
103. Which of the following is the most commonly used buffer in the serial porting?
a) LIFO
b) FIFO
c) FILO
d) LILO
View Answer
Answer: b
Explanation: Most of the serial ports uses a FIFO buffer so that the data is not lost. The FIFO
buffer is read to receive the data, that is, first in first out.
104. What does SPI stand for?
a) serial parallel interface
b) serial peripheral interface
c) sequential peripheral interface
d) sequential port interface
View Answer
Answer: b
Explanation: The serial parallel interface bus is a commonly used interface which involves
master slave mechanism. The shift registers are worked as master and the slave devices are
driven by a common clock.
105. Which allows the full duplex synchronous communication between the master and the
slave?
a) SPI
b) serial port
c) I2C
d) parallel port
View Answer
Answer: a
Explanation: The serial peripheral interface allows the full duplex synchronous communication
between the master and the slave devices. MC68HC05 developed by Motorola uses SPI for
interfacing the peripheral devices.
106. Which of the following processor uses SPI for interfacing?
a) 8086
b) 8253
c) 8254
d) MC68HC11
View Answer
Answer: d
Explanation: The MC68HC05 and MC68HC11 microcontrollers uses the serial peripheral
interface for the peripheral interfacing.
107. In which register does the data is written in the master device?
a) index register
b) accumulator
c) SPDR
d) status register
View Answer
Answer: c
Explanation: The serial peripheral interface follows a master slave mechanism in which the data
is written to the SPDR register in the master device and clocked out into the slave device SPDR
by using a common clock signal called SCK.
108. What happens when 8 bits are transferred in the SPI?
a) wait statement
b) ready statement
c) interrupt
d) remains unchanged
View Answer
Answer: c
Explanation: The interrupts are locally generated when 8-bits are transferred so that the data can
be read before the next byte is clocked through.
109. Which signal is used to select the slave in the serial peripheral interfacing?
a) slave select
b) master select
c) interrupt
d) clock signal
View Answer
Answer: a
Explanation: The slave select signal selects which slave is to receive data from the master.
110. How much time period is necessary for the slave to receive the interrupt and transfer the
data?
a) 4 clock time period
b) 8 clock time period
c) 16 clock time period
d) 24 clock time period
View Answer
Answer: b
Explanation: The SPI uses an eight clock time period for the slave to receive the interrupt and
transfer the data which determines the maximum data rate.
111. Which of the following allows a lower priority task to run despite the higher priority task is
active and waiting to preempt?
a) message queue
b) message passing
c) semaphore
d) priority inversion
View Answer
Answer: d
Explanation: The priority inversion mechanism where the lower priority task can continue to run
despite there being a higher priority task active and waiting to preempt.
112. What happens to the interrupts in an interrupt service routine?
a) disable interrupt
b) enable interrupts
c) remains unchanged
d) ready state
View Answer
Answer: a
Explanation: In the interrupt service routine, all the other interrupts are disabled till the routine
completes which can cause a problem if another interrupt is received and held pending. This can
result in priority inversion.
113. Which of the following is a part of RTOS kernel?
a) memory
b) input
c) ISR
d) register
View Answer
Answer: c
Explanation: The ISR can send the message for the tasks and it is a part of RTOS kernel.
114. Which of the following is an industrial interconnection bus?
a) bus interface unit
b) data bus
c) address bus
d) VMEbus
View Answer
Answer: d
Explanation: The VMEbus is an interconnection bus which is used in the industrial control and
many other real-time applications.
115. Which of the following supports seven interrupt priority level?
a) kernel
b) operating system
c) VMEbus
d) data bus
View Answer
Answer: c
Explanation: The VMEbus supports seven interrupt priority level which allows the prioritisation
of the resources
116. Which allows the parallel development of the hardware and software in the simulation?
a) high-level language simulation
b) low-level language simulation
c) cpu simulator
d) onboard simulator
View Answer
Answer: a
Explanation: The high-level language simulation allows a parallel development of the software
and the hardware and when two parts are integrated, that will work. It can simulate I/O using the
keyboard as the inputs or task which passes input data for other modules.
117. Which of the following are used to test the software?
a) data entity
b) data entry
c) data table
d) data book
View Answer
Answer: c
Explanation: In the high-level language simulation, many techniques are used to simulate the
system and one such is the data table which contains the data sequences which are used to test
the software.
118. Which allows the UNIX software to be ported using a simple recompilation?
a) pSOS+
b) UNIX compatible library
c) pSOS+m
d) pOS+kernel
View Answer
Answer: b
Explanation: The most of the operating system supports or provide the UNIX-compatible library
which supports the UNIX software to be ported using a simple recompilation.
119. Which of the following can simulate the processor, memory, and peripherals?
a) input simulator
b) peripheral simulator
c) memory simulator
d) cpu simulator
View Answer
Answer: d
Explanation: The CPU simulator can simulate the memory, processor, and the peripherals and
allow the low-level assembler code and the small HLL programs to be tested without the actual
hardware.
120. How many categories are there for the low-level simulation?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two categories for the low-level simulation. The first category simulates
the memory system, programming model and can offer simple debugging tools whereas the
second category simulation provides timing information based on the number of clocks.
121. Which of the following can simulate the LCD controllers and parallel ports?
a) memory simulator
b) sds
c) input simulator
d) output tools
View Answer
Answer: b
Explanation: There are certain tools which provide powerful tools for simulation and one such is
the SDS which can simulate the processor, memory systems, integrated processor, onboard
peripherals such as LCD controllers and parallel ports.

122. Which of the following provides a low-level method of debugging software?
a) high-level simulator
b) low-level simulator
c) onboard debugger
d) cpu simulator
View Answer
Answer: c
Explanation: The onboard debugger provides a very low-level method of simulating or
debugging the software. It usually handles EPROMs which are plugged into the board or a set of
application codes by providing a serial connection to communicate with the PC or workstation.
123. Which of the following has the ability to download code using a serial port?
a) cpu simulator
b) high-level language simulator
c) onboard debugger
d) low-level language simulator
View Answer
Answer: c
Explanation: The onboard debugger has the ability to download code from a floppy disk or by
using a serial port.
124. What does the processor fetches from the EPROM if the board is powered?
a) reset vector
b) ready vector
c) start vector
d) acknowledge vector
View Answer
Answer: a
Explanation: The processor fetches its reset vector from the table which is stored in the EPROM
when the board is powered and then starts the initialize the board.
125. Which of the following device can transfer the vector table from the EPROM?
a) ROM
b) RAM
c) CPU
d) peripheral
View Answer
Answer: b
Explanation: When the board gets powered up, the reset vector from the table stored in the
EPROM makes the initialisation of the board and is transferred to the RAM from the EPROM
through the hardware where the EPROM memory address is temporarily altered.
126. Which of the following allows the reuse of the software and the hardware components?
b) memory design
c) peripheral design
d) input design
View Answer
Answer: a
Explanation: The platform design allows the reuse of the software and the hardware components
in order to cope with the increasing complexity in the design of embedded systems.
127. Which of the following is the design in which both the hardware and software are
considered during the design?
c) software/hardware codesign
d) peripheral design
View Answer
Answer: c
Explanation: The software/hardware codesign is the one which having both hardware and
software design concerns. This will help in the right combination of the hardware and the
software for the efficient product.
128. What does API stand for?
a) address programming interface
b) application programming interface
c) accessing peripheral through interface

d) address programming interface
View Answer
Answer: b
Explanation: The platform-based design helps in the reuse of both the hardware and the software
components. The application programming interface helps in extending the platform towards the
software applications.
129. Which activity is concerned with identifying the task at the final embedded systems?
a) high-level transformation
b) compilation
c) scheduling
d) task-level concurrency management
View Answer
Answer: d
Explanation: There are many design activities associated with the platforms in the embedded
system and one such is the task-level concurrency management which helps in identifying the
task that needed to be present in the final embedded systems.
130. In which design activity, the loops are interchangeable?
a) compilation
b) scheduling
c) high-level transformation
d) hardware/software partitioning
View Answer
Answer: c
Explanation: The high-level transformation are responsible for the high optimizing
transformations, that is, the loops can be interchanged so that the accesses to array components
become more local.
131. Which design activity helps in the transformation of the floating point arithmetic to a fixed
point arithmetic?
b) scheduling
c) compilation
View Answer
Answer: a
Explanation: The high-level transformation are responsible for the high optimizing
transformations, that is, for the loop interchanging and the transformation of the floating point
arithmetic to the fixed point arithmetic can be done by the high-level transformation.
a) scheduling
c) hardware/software partitioning
d) compilation
View Answer
Answer: c
Explanation: The hardware/software partitioning is the activity which is in charge of mapping
operations to the software or to the hardware.
133. Which of the following is approximated during hardware/software partitioning, during tasklevel
concurrency management?
a) scheduling
b) compilation
c) task-level concurrency management
d) high-level transformation
View Answer
Answer: a
Explanation: The scheduling is performed in several contexts. It should be approximated with the
other design activities like the compilation, hardware/software partitioning, and task-level
concurrency management. The scheduling should be precise for the final code.
134. Which of the following is a process of analyzing the set of possible designs?
a) design space exploration
b) scheduling
c) compilation
View Answer
Answer: a
Explanation: The design space exploration is the process of analyzing the set of designs and the
design which meet the specification is selected.
135. Which of the following is a meet-in-the-middle approach?
a) peripheral based design
b) platform based design
c) memory based design
d) processor design
View Answer
Answer: b
Explanation: The platform is an abstraction layer which covers many possible refinements to a
lower level and is mainly follows a meet-in-the-middle approach
1) Which function/s is/are provided by Integrated Memory

Management Unit in 80386 architecture?
a. Optional on-chip paging
b. 4 levels of protection
c. Virtual Memory Support
d. All of the above
2) Which unit in 80386 DX architecture plays a crucial role in the
conversion of linear address to physical address?
a. Execution
b. Protection
c. Segmentation
d. Paging
ANSWER: (d) Paging
3) In Intel x86 architecture, which general purpose register is used
for repeated string instructions as well as shift, rotate and loop
instructions?
a. EAX (Accumulator)
b. ECX (Counter)
c. EDX (Data register)
d. EBP (Data Pointer)
ANSWER: (b) ECX (Counter)
4) Which status flag in x86 family is used to enable or disable the
interrupt especially when the Pentium processor operates in the
virtual mode?
a. ID
b. VIP
c. VIF
d. AC
ANSWER: (c) VIF
5) Which control register in x86 family is reserved for future use
and generally not adopted for current implementation?
a. CR0
b. CR1
c. CR2
d. CR4
ANSWER: (b) CR1
6) Which functional unit of ARM family architecture is responsible
for upgrading the address register contents before the core reads
or writes the next register value from memory location?
a. Data bus
b. Barrel Shifter
c. Incrementer
d. Instruction Decoder
ANSWER: (c) Incrementer
7) Which type of non-privileged processor mode is entered due to
raising of high priority of an interrupt?
a. User mode
b. Fast Interrupt Mode (FIQ)
c. Interrupt Mode (IRQ)
d. Supervisor Mode (SVC)
ANSWER: (b) Fast Interrupt Mode (FIQ)
8) Abort mode generally enters when _______
a. an attempt access memory fails
b. low priority interrupt is raised
c. ARM processor is on rest
d. undefined instructions are to be handled
ANSWER: (a) an attempt access memory fails
9) In the process of pipelining, which instructions are fetched from
the memory by the ARM processor during the execution of current
instruction?
a. Previous
b. Present
c. Next
d. All of the above
ANSWER: (c) Next
10) If the three stages of execution in pipelining are overlapped,
how would be the speed of execution?
a. Higher
b. Moderate
c. Lower
d. Unpredictable
ANSWER: (a) Higher
11) Which parameter/s is/are included in ‘Time to market’ design
metric of an embedded system?
a. Time to prototype
b. Time to refine
c. Time to produce in bulk
d. All of the above
12) How is the nature of instruction size in CISC processors?
a. Fixed
b. Variable
c. Both a and b
ANSWER: (b) Variable
13) What is/are the configuration status of control unit in RISC
Processors?
a. Hardwired
b. Microprogrammed
c. Both a and b
ANSWER: (a) Hardwired
14) At an active HIGH reset pin of 8051 microcontroller, for how
many machine cycles should the positive going pulse be provided, if
the power is switched ON?
a. only one
b. two
c. three
d. four
ANSWER: (b) two
15) While designing an embedded system, which sub-task oriented
process allocates the time steps for various modules that share the
similar resources?
a. Simulation and Validation
b. Iteration
c. Hardware-Software Partitioning
d. Scheduling
ANSWER: (d) Scheduling
16) In DAC 0808, which among the following is configured as a
reference in addition to R-2R ladder and current switches?
a. Voltage amplifier
b. Current amplifier
c. Transconductance amplifier
d. Transresistance amplifier
ANSWER: (b) Current amplifier
17) In DAC 0808, what is the high speed multiplying input slew
rate?
a. 2 mA/μ sec
b. 4 mA/μ sec
c. 8 mA/μ sec
d. 16 mA/μ sec
ANSWER: (c) 8 mA/μ sec
18) In LPC 2148, which among the following is/are the functions of
Mask register?
a. Byte addressability
b. Relocation to ARM local bus for fastest posible I/O timing
c. Treating sets of port bits in the form of group without changing other
bits
d. All of the above
ANSWER: (c) Treating sets of port bits in the form of group without
changing other bits
19) What is the size range of the alphanumeric LCDs?
a. 1 to 8 characters
b. 8 to 80 characters
c. 100 to 150 characters
d. 250 to 400 characters
ANSWER: (b) 8 to 80 characters
20) Which type of handshake packet indicates that the device is
incapable of accepting data as it is supposed to be busy with some
another task?
a. ACK
b. NAK
c. STALL
ANSWER: (b) NAK
21) Which among the following is/are integrated by OTG
controller in order to implement OTG dual-role device
functionality?
a. Host Controller
b. Device Controller
c. Master-only I2C bus interface
d. All of the above
22) Which mode of operation is exhibited by RS-485 standard?
a. Single ended
b. Differential
c. Both a and b
ANSWER: (b) Differential
23) In Von Neumann architecture, which among the following
handles all the operations of the system that are inside and outside
the processor?
a. Input Unit
b. Output Unit
c. Control Unit
d. Memory Unit
ANSWER: (c) Control Unit
24) In CPU structure, where is one of the operand provided by an
accumulator in order to store the result?
a. Control Unit
b. Arithmetic Logic Unit
c. Memory Unit
d. Output Unit
ANSWER: (b) Arithmetic Logic Unit
25) In CPU structure, which register provides the address for
fetching of data or instruction especially by means of processor?
a. Data Register
b. Instruction Register
c. Accumulator
d. Memory Address Register
ANSWER: (d) Memory Address Register
26) In CPU structure, what kind of instruction to be executed is
held by an instruction Register (IR)?
a. Current (present)
b. Previous
c. Next
d. All of the above
ANSWER: (a) Current (present)
27) In ADSP 21xx architecture, which notation represents ALU
overflow condition?
a. AC
b. AV
c. NE
d. EQ
ANSWER: (b) AV
28) Which kind of low-order 16 bits control register is also
regarded as ‘Machine Status Word’ (MSW) in order to make it
compatible with i286?
a. CR0
b. CR1
c. CR2
d. CR3
ANSWER: (a) CR0
29) In the test registers, what do/does the linear address bit
hold/s with respect to TLB (Translation Look-aside Buffers)?
a. Physical address
b. Selection between write and lookup of TLB
c. Tag field
d. All of the above
ANSWER: (c) Tag field
30) For addressing in real mode, which segment plays a significant
role in the storage of destination operands during the string
operation?
a. Code Segment
b. Data Segment
c. Stack Segment
d. Extra Segment
ANSWER: (d) Extra Segment
31) In x86 architecture, which type of gate acts as an intermediary
between code segments at different privilege levels (PLs)?
a. Call gates
b. Task gates
c. Interrupt gates
d. Trap gates
ANSWER: (a) Call gates
32) In Pentium processor, which write buffer is used by the
pipeline ALUs in order to write the result to the memory?
a. External Snoop Write Buffer
b. Internal Snoop Write Buffer
c. Line Replacement Write Buffer
d. Write-back Buffer
ANSWER: (d) Write-back Buffer
33) Which stage associated with pipelining mechanism recognizes
the instruction that is to be executed?
a. Fetch
b. Decode
c. Execute
ANSWER: (b) Decode
34) Which kind of addressing mode for memory access operands
support pre-index and post-index in addition to the generation of
memory address by an immediate value added to a register?
a. Register indirect addressing mode
b. Relative register indirect addressing mode
c. Base indexed indirect addressing mode
d. Base with scale register addressing mode
ANSWER: (b) Relative register indirect addressing mode
35) Which mnemonic implies ‘plus’ meaning in the branch
instructions?
a. BPL
b. BEQ
c. BMI
d. BAL
ANSWER: (a) BPL
36) In the branch instructions of ARM, what does the mnemonic
BVC imply?
a. Overflow Set
b. Carry Set
c. Carry Clear
d. Overflow Clear
ANSWER: (d) Overflow Clear
37) Which type of branching instructions of thumb possesses 11-
bit address & is generally applicable for slightly longer jumps in
order to implement the instructions like GOTO of high level
languages?
a. Short Conditional Branch
b. Medium Range Unconditional Branch
c. Long Range Subroutine Calls
ANSWER: (b) Medium Range Unconditional Branch
38) Which types of an embedded systems involve the coding at a
simple level in an embedded ‘C’, without any necessity of RTOS?
a. Small Scale Embedded Systems
b. Medium Scale Embedded Systems
c. Sophisticated Embedded Systems
d. All of the above
ANSWER: (a) Small Scale Embedded Systems
39) Which microcontrollers are adopted for designing medium
scale embedded systems?
a. 8-bit
b. 16-bit to 32-bit
c. 64-bit
d. All of the above
ANSWER: (b) 16-bit to 32-bit
40) In Cortex-A processor series, which among the following is the
standalone and smallest processor in size constraints with high-end
application support?
a. Cortex-A5
b. Cortex-A9
c. Cortex-A53
d. Cortex-A59
ANSWER: (a) Cortex-A5
41) Which interrupt controller is present in Cortex-A15
processor?
a. GIC-390
b. GIC-500
c. Integrated GIC
d. GIC-400
ANSWER: (c) Integrated GIC
42) In Cortex-R processor series, which among the following
represent/s dual core configuration along with the space saving the
floating point unit?
a. Cortex-R 4
b. Cortex-R 5
c. Cortex-R 7
d. All of the above
ANSWER:(b) Cortex-R 5
43) For the supplied data, which edge level is necessary for LCD in
order to latch the data?
a. High-to-Low
b. Low-to-High
c. High-to-High
d. Low-to-Low
ANSWER: (a) High-to-Low
44) In LCD, which function is executed by ‘0x05’ hex command?
a. Shift display left
b. Shift display right
c. Clear display
d. Return cursor to home
ANSWER: (b) Shift display right
45) In LCD, which hex command performs the function of ‘Display
on, cursor on and blinking’?
a. 0x0A
b. 0x0C
c. 0x0E
d. 0x0F
ANSWER: (d) 0x0F
46) In DC motor interfacing, which field/s is/are generated by
forcing current through the coil for spinning of the motor?
a. Electric field
b. Electrostatic field
c. Magnetic field
d. All of the above
ANSWER: (c) Magnetic field
47) In DC motor interfacing, which modulation controls the duty
cycle of square wave provided at the output by generating variation
in the average DC voltage?
a. Amplitude Modulation
b. Frequency Modulation
c. Pulse Width Modulation
d. Phase Modulation
ANSWER: (c) Pulse Width Modulation
48) What is the value of maximum data rate in RS 232 standard?
a. 20 kb/s
b. 40 kb/s
c. 80 kb/s
d. 100 kb/s
ANSWER: (a) 20 kb/s
49) In Modbus Protocol, which codes are included in Request PDU?
a. Function code, Response data
b. Function code, Function data
c. Error code, Exception code
d. All of the above
ANSWER: (b) Function code, Function data
50) Which category of function code represents the currently used
codes by some companies especially for legacy products?
a. Public
b. User-defined
c. Reserved
d. Exceptions
ANSWER: (c) Reserved
51) In ISA, what is/are the application/s of Timer2 which acts as a
speaker timer?
a. Date & time maintenance in RAM
b. General purpose timer
c. Diagnostic purpose
d. All of the above
ANSWER: (c) Diagnostic purpose
52) In ISA, Timer 0 is also regarded as ______
a. System Timer
b. Refresh Timer
c. Speaker Timer
d. All of the above
ANSWER: (a) System Timer
53) Match the following STKY multiplier (MAC) flag notations with
their meanings in ADSP 21 xx family architecture.
A. MOS —————— 1) Multiplier floating-point invalid operation
B. MIS ——————- 2) Multiplier Underflow
C. MUS —————— 3) Multiplier floating-point overflow
D. MVS —————— 4) Multiplier fixed-point overflow
a. A-3, B-2, C-4, D-1

b. A-2, B-3, C-1, D-4
c. A-1, B-4, C-3, D-2
d. A-4, B-1, C-2, D-3
ANSWER: (d) A-4, B-1, C-2, D-3
54) In ADSP 21 xx architecture, how many previously executed
instructions are stored in instruction cache of cache memory?
a. 4
b. 8
c. 16
d. 32
ANSWER: (c) 16
55) In TMS 320 C5X processor, which operation/s is/are
performed by Compare Select & Store Unit (CSSU)?
a. Selection of large word in accumulator for storing into the data
memory
b. Comparison between high & low word of accumulator
c. Maintain the record of transition histories
d. All of the above
56) In TMS 320 C5X processor, which memory segment provides
interfacing to external memory mapped peripherals and also
serves as extra data storage space?
a. Program Memory
b. Data memory
c. I/O Memory
d. All of the above
ANSWER: (c) I/O Memory
57) How are the instructions executed in DSP Processors?
a. In Parallel manner
b. In Sequential manner
c. Both a and b
ANSWER: (a) In Parallel manner
1. Which serial data communication mode is standard 8-bit UART?
a. mode 0 b. mode 1 c. mode 4 d. mode 3
Ans: d
2. Which is used for time-sharing applications?
a. Star b. loop c. hybrid d. bus
Ans: a
3. Which is used for data-gathering applications?
Ans: b
4. The ___ is a good choice when the number of nodes is small.

Ans: a
5. Which serial data communication mode is standard 8-bit UART?
Ans: b
6. Which serial data communication mode is high speed?
Ans: a
7. Which serial data communication mode is 8-bit shift register?
Ans: a
8. A standard for OS interfaces proposed by IEEE is
a. POSIX b. QNX c. AMX d. Intel
Ans: a
9. The basic building block of software written under an RTOS is the
a. scheduler b. task c. context d. reentrancy
Ans: b
10. The ___ state means that this task has not got to do right now, even if the CPU is available.
a. running b. ready c. blocked d. suspended
Ans: c
11. A _____ function may not use the hardware in a monatomic way.
a. mutex b. task c. reentrant d. semaphore
Ans: c
12. Under most RTOS a task is simply a _____.
a. routine b. subroutine c. interrupt d. exception
Ans: b
13. A ____ RTOS will stop a lower-priority task as soon as the higher-priority task unblocks.
a. preemptive b. non preemptive c. interpret d. exception
Ans: a
14. A_____ RTOS will only take the microprocessor away from the lower-priority task when that
task blocks.
a. preemptive b. non preemptive c. interpret d. exception
Ans: b
15. A function that works properly even if it is called by more than one task is called a ____
function.
a. mutex b. task c. reentrant d. semaphore
Ans: c
16. The ____ state means that the microprocessor is executing the instructions that make up this.
Ans: a
17. The ___ state means that some other task is in the running state but that this task
the things that it could do if the microprocessor becomes available.
Ans: b
18. A semaphore that does not specify the order in which processes are removed from the queue
is _
a. mutex b. strong c. counting d. weak
Ans: d
19. The process that has been blocked the longest is released from the queue
Ans: b
20. Semaphores
a. are used to do I/O
b. synchronize critical resources to present condition.
c. synchronize critical resources to avoid dead lock.
d. allow processes to communicate with one another.
Ans: c
21. The non-binary semaphore is often referred to as ________ semaphore
Ans: c
22. Binary semaphore is also known as
a. General semaphore b. Mutex c. Cluster d. Spooling
Ans: b
23. For both counting semaphores and binary semaphores, a _____ is used to hold processes
waiting on the semaphores.
a. stack b. queue c. dequeue d. circular queue
Ans: b
24. ______ guarantees freedom from starvation.
a. Strong semaphores b. Weak semaphores c. Delay semaphores d. Binary semaphores
Ans: a
25. The barbershop problem is an example of
a. Deadlock b. Starvation c. Semaphore d. Live lock
Ans: c
26. In the producer/consumer problem, there are
a. one or more producers and one or more consumers
b. single producer and single consumer
c. single producer and one or more consumers
d. one or more producers and single consumer
Ans: d
27. A semaphore count of negative n means (s= -n) that the queue contains waiting process.
a. n+1 b. n c. n-1 d. 0
Ans: b
28. ______ can be considered as an array of mailboxes
a. pipes b. semaphore c. timer d. message queue
Ans: d
29. In a time sharing operating system, when the time slot given to a process is completed ,
the process goes from the RUNNING state of the
a. BLOCKED state b. READY state c. SUSPENDED state d. TERMINATE state
Ans: b
30.A mutex can be
a. locked state b. unlocked state c. either in locked state or unlocked state d. neither in locked
state nor unlocked state
Ans: c
Which task method follows a currently running task to be stopped by a higher priority task?
a.
b.
c.
d.
Answer: (d).pre-emption
52. Which of the following requires programming within the application?
a. time slice
b. scheduling algorithm
c. pre-emption
d. cooperative multitasking
Answer: (d).cooperative multitasking
53. What does RMS stand for?
a. rate monotonic scheduling
b. rate machine scheduling
c. rate monotonic software
d. rate machine software
Answer: (a).rate monotonic scheduling
54. Which of the following task swapping method is a better choice in the embedded systems design?
a. RMS
b. pre-emptive
c. cooperative multitasking
d. time slice
Answer: (b).pre-emptive
55. Which of the following allows a lower priority task to run despite the higher priority task is active and waitin
a. message queue
b. message passing
c. semaphore
d. priority inversion
Answer: (d).priority inversion
56. What happens to the interrupts in an interrupt service routine?
a. disable interrupt
b. enable interrupts
c. remains unchanged
d. ready state
Answer: (a).disable interrupt
57. Which of the following is a part of RTOS kernel?
a. memory
b. input
c. ISR
d. register
Answer: (c).ISR
58. Which of the following is an industrial interconnection bus?
a. bus interface unit
b. data bus
c. address bus
d. VMEbus
Answer: (d).VMEbus
59. Which of the following supports seven interrupt priority level?
a. kernel
b. operating system
c. VMEbus
d. data bus
Answer: (c).VMEbus
60. What type of interrupt handling is seen in multiprocessor applications?
a. centralised interrupt
b. handled by one MASTER
c. distributed handling
d. shared handling
Answer: (c).distributed handling

. ___ is the basic building block of software written under an RTOS.
Ans. Task
2. TCB stands for ___.

Ans. Task Control Block
3. When other tasks can run, the kernel can switch control to the user-supplied
routine instead of to the idle task. (True or False)
Ans. False
4. When a task is first created and made ready to run, the kernel puts it into the ___.
Ans. ready state
5. ___ occurs when higher priority tasks use all of the CPU execution time and lower
priority tasks do not get to run.
Ans. CPU starvation
6. On a single-processor system, only one task can run at a time. (Yes or No)
Ans. Yes
7. What happens when memory is acquired but not released?

Ans. A memory leak occurs
8. Endless-loop tasks do the majority of the work in the application by handling

inputs and outputs.
(True or False)
Ans. True
9. Tasks synchronize and communicate amongst themselves by using ___.

Ans. intertask primitives
10. The ___ tracks the number of times a semaphore has been acquired or released
by maintaining a token count.
Ans. Kernel
11. The ___ is the part of the scheduler that performs context switching and changes
the flow of execution.
Ans. dispatcher
12. When a binary semaphore’s value is 0, the semaphore is considered ___.

Ans. Unavailable
13. Ownership of a mutex is gained when a task first locks the mutex by releasing it.
(True or False)
Ans. False
14. What happens when a higher priority task is blocked and is waiting for a resource
being used by a lower priority task?
Ans. Priority inversion occurs
15. ___ specify the initial semaphore state and the task-waiting order.
Ans. Binary
16. To clear all tasks waiting on a semaphore task-waiting list, some kernels support
a ___ operation.
Ans. Flush
17. Two tasks can communicate for the purpose of synchronization without
exchanging data. (True or False)
Ans. True
18. A ___ can be used to serialize access to a shared resource.

Ans. semaphore
19. A message queue is like a ___.

Ans. Pipeline
20. QCB stands for ___.

Ans. Queue Control Block
21. Which scheduling provides each task with an equal share of the CPU execution
time?
Ans. Round-robin
22. ___ are concurrent and independent threads of execution that can compete for
CPU execution time.
Ans. Tasks
23. Different kernels store message queues in different locations in memory. (True or
False)
Ans. True
24. ___ are much like queues.

Ans. Mailboxes
25. ___ are kernel objects that provide unstructured data exchange and facilitate
synchronization among tasks.
Ans. Pipes
26. Creating a named pipe is similar to creating a ___.

Ans. File
27. A pipe is mainly used for ___ or ISR-to-task data transfer.

Ans. task-to-task
28. An event register can count the occurrences of the same event while it is
pending. (True or False)
Ans. False
29. A ___ is a software interrupt that is generated when an event has occurred.
Ans. Signal
30. The number and type of signals defined is both system-dependent and ___
dependent.
Ans. RTOS
31. A condition variable can be associated with ___.

Ans. multiple conditions
32. A task must first acquire the ___ before evaluating the predicate.
Ans. mutex
33. Embedded systems must be reliable. (True or False)

Ans. True
34. Typically, the processor’s performance is expressed in ___.

Ans. MIPS
35. ___ IO operations are at certain fixed data rates.

Ans. Synchronous
36. ___ are the portions of the program code that handle the interrupt requests.
Ans. Interrupt Service Routines (ISR)
37. The time required for the CPU to return to the interrupted code /highest priority
task is called ___.
Ans. interrupt recovery time
38. An embedded system with a single CPU can run only one process at an instance.
(True/False)
Ans. True
39. Errors dealing with queues can be reduced by ___.

Ans. Encapsulation
40. In embedded systems code must be stored in ___ and data in ___.
Ans. ROM, RAM
41. ___ is a real-time operating system made and sold by Wind River Systems of
Alameda, California, USA.
Ans. VxWorks
42. ___ is based on the idea of running most of the OS in the form of a number of
small tasks, known as servers.
Ans. QNX
43. In a multi-tasking RTOS, each task needs to be allocated with an amount of

memory for storing their contexts for ___.
Ans. context switching
44. Heap memory is typically used by the kernel for dynamic memory allocation of
data space for tasks. (True/False)
Ans. False
45. Fundamental to the operation of most pre-emptive RTOSs is the concept of a tick
timer or heartbeat. (True/False)
Ans. True
46. What is the advantage of a short system tick?

Ans. Accurate timings
47. ARM is an acronym for ___.

Ans. Advanced RISC Machines
48. The RISC architecture follows the philosophy that ___ instruction should be
performed every clock cycle.
Ans. One
49. ___ is a von Neumann architecture machine, while ___ uses Harvard architecture.
Ans. ARM7, ARM9
50. SHARC is a high-performance floating-point and fixed-point DSP from Analog
Devices. (True/False)
Ans. True
51. CAN stands for ___.

Ans. Controller Area Network
52. ___ is generically referred to as a “two-wire interface”.

Ans. I²C
53. The I²C reference design has a ___ address space with 16 reserved addresses.
Ans. 7-bit
54. The transmission starts when SDL is pulled low while SCL remains high. (True or
False)
Ans. True
55. The CAN is a ___ type of bus.

Ans. broadcast
56. CAN is a synchronous bus – all transmitters must send at the same time for bus
arbitration to work.
(True or False)
Ans. True
57. When all nodes are transmitting 1s, the bus is said to be in the ___ state.
Ans. recessive
58. Using ___ devices, high baud rates and high busloads with many messages can be
handled.
Ans. Full CAN
59. ___ protocol provides connectionless, packet-based communication.

Ans. Internet
60. A node that transmits data among different types of networks is known as a ___.
Ans. Router
61. 68. The canonical example of a pipelined processor is a ___ processor, with five
stages.
Ans. RISC
62. HTTP stands for ___.

Ans. HyperText Transport Protocol
63. ___ is a little-endian processor.
Ans. SHARC
64. Which is the latest processor in the TigerSHARC family?

Ans. ADSP-TS201
65. Modern processors have ___ instruction pipelines.

Ans. multi-stage
1. Which of the following are the proposals for multiprocessor thread scheduling and
processor assignment?
i) Load Sharing ii) Gang Scheduling iii) Dynamic Scheduling iv) Load Scheduling
A) i, ii and iii only
B) ii, iii and iv only
C) i, iii and iv only
D) All i, ii, iii and iv
2. In ………………… a set of related threads is scheduled to run on a set of processors at the

same time, on a one to one basis.
A) Load Sharing
B) Gang Scheduling
C) Dynamic Scheduling
D) Load Scheduling
3. In a……………… approach for multiprocessor thread scheduling and processor

assignment, processes are not assigned to a particular processor.
A) Load Sharing
B) Gang Scheduling
D) Load Scheduling
4. In …………………. approach, the scheduling routine of the operating system is run of that
processor to select the next thread.
A) Load Sharing
B) Gang Scheduling
D) Load Scheduling
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5. Which of the following is/are the advantages of load sharing.
i) Preempted threads are unlikely to resume execution on the same processor.
ii) The central queue occupies a region of memory that must be accessed in a manner that
enforces mutual exclusion.
iii) If all threads are treated as a common pool of threads, it is unlikely that all of the
threads of a program will gain access to processors at the same time.
A) i and ii only
B) ii and iii only
C) i and iiii only
D) All i, ii and iii
6. scheduling overhead may be reduced on …………………. because a single decision affects

a number of processors and processes at one time.
A) Load Sharing
B) Gang Scheduling
D) Dedicated processor assignment
7. An ……………. has a deadline by which it must finish or start, or if may have a constraint
on both and finish time.
A) hard real-time task
B) soft real-time task
C) aperiodic task
D) periodic task
8. An operating system is ……………………. to the extent that it performs operations at

fixed, predetermined times or within predetermined time intervals.
A) deterministic
B) responsiveness
C) reliable
D) operative
9. ………….. is concerned with how long, after acknowledgment, it takes an operating

system to service the interrupt.
A) Deterministic
B) Responsiveness
C) Reliable
D) Operative
10. …………………. is concerned with how long operating system delays before
acknowledging an interrupt.
A) Determinism
B) Responsiveness
C) Reasonableness
D) Operatives
11. State whether the following statements are True or False for the features of the real-
time operating system.
i) fast process or thread switch
ii) the ability to respond to external interrupts quickly.

iii) minimization of intervals during which interrupts are enabled.
iv) preemptive scheduling based on priority
A) i, ii and iii only
B) ii, iii and iv only
C) i, ii and iv only
D) All i, ii, iii and iv
12. ………………….. is a characteristic that refers to the ability of a system to fail in such a
way as to preserve a system to fail in such a way as to preserve as much capacity and data
is possible.
A) User control
B) Responsiveness
C) Fail soft operation
D) Reliability
13. The result of the ……………… in real-time scheduling is a schedule that determines, at
run time, when a task must begin execution.
A) Static table-driven approaches
B) Dynamic best effort approaches
C) Static priority-driven preemptive approaches
D) Dynamic planning based approaches
14. No feasibility analysis is performed in ………………. of real-time scheduling.

15. In …………….. feasibility is determined at run time rather than offline prior to the start
of execution.
16. In …………….. of real-time scheduling, the system tries to meet all deadlines and aborts
any started process whose deadline is missed.
17. ………………. is applicable to tasks that are periodic. Input to the analysis consists of the
periodic ending deadline and relative priority of each task.
A) Static table-driven scheduling
B) Dynamic best-effort scheduling
C) Static priority-driven preemptive scheduling
D) Dynamic planning based scheduling
18. ………………. makes use of the priority-driven preemptive scheduling mechanism

common to most non-real-time multi-programming systems.
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19. With ……………… after a task arrives, but before its execution begins, an attempt is
made to create a schedule that contains the previously scheduled tasks as well as the new
arrival.
20. …………………. is the approach used by many real-time systems that are currently
commercially available.
A) Static table driven scheduling
1. What are the services operating System provides to both the users
and to the programs?
A. File System manipulation
B. Error Detection
C. Program execution
D. Resource Allocation
View Answer
Ans : C
Explanation: An Operating System provides services to both the users and to the
programs. It provides programs an environment to execute and It provides users the
services to execute the programs in a convenient manner.
2. Which of the following few common services provided by an

operating system?
A. Protection
B. Program execution
C. I/O operations
D. All of the above
View Answer
Ans : D
Explanation: All of the above are services provided by an operating system.
3. Which of the following are examples of storage media?

A. magnetic disk
B. optical disk
C. Both A and B
View Answer
Ans : C
Explanation: Examples of storage media include magnetic tape, magnetic disk and
optical disk drives like CD, DVD.
4. Which of the following is true about Program execution?

A. Restrict to load a program into memory.
B. Provides a mechanism for process synchronization.
C. Do not provides a mechanism for process communication.
D. Do not provides a mechanism for deadlock handling.
View Answer
Ans : B
Explanation: Option B is correct.
5. Which of the following is false about I/O Operation?

A. Operating system does not provides the access to the I/O device
B. I/O operation means read or write operation
C. An I/O subsystem comprises of I/O devices
View Answer
Ans : A
Explanation: Operating system provides the access to the required I/O device when
required.
6. Which of the following is false about File system manipulation?

A. Computers can store files on the disk (Primary storage), for long-term
storage purpose
B. Program needs to read a file or write a file.
C. Operating System provides an interface to the user to create/delete files.
D. Operating System provides an interface to create the backup of file
system.
View Answer
Ans : A
Explanation: Computers can store files on the disk (secondary storage), for long-term
storage purpose. Examples of storage media include magnetic tape, magnetic disk and
optical disk drives like CD, DVD.
7. Which of the following is true about Communication?

A. The OS handles routing and connection strategies, and the problems of
contention and security.
B. Two processes often require data to be transferred between them
C. Communication may be implemented by two methods, either by Shared
Memory or by Message Passing.
D. All of the above
View Answer
Ans : D
Explanation: All statement are correct.
8. Which of the following is true about Communication?

A. Errors can occur anytime and anywhere.
B. An error may occur in CPU, in I/O devices or in the memory hardware.
C. OS constantly checks for possible errors.
D. All of the above
View Answer
Ans : D
Explanation: All statement are correct.
9. The OS ensures that all access to system resources is controlled.The

major activities of an operating system with respect to?
A. Error handling
B. Resource Management
C. Protection
D. Communication
View Answer
Ans : C
Explanation: the major activities of an operating system with respect to protection : The
OS ensures that all access to system resources is controlled.
10. Two processes often require data to be transferred between them.

The major activities of an operating system with respect to?
A. Error handling
B. Resource Management
C. Protection
D. Communication
View Answer
Ans : D
Explanation: The major activities of an operating system with respect to communication :

Two processes often require data to be transferred between them
1. Which of the following is a set of specially selected input patterns?
a) test pattern
b) debugger pattern
c) bit pattern
d) byte pattern
View Answer
Answer: a
Explanation: While testing any devices or embedded systems, we apply some selected inputs which
is known as the test pattern and observe the output. This output is compared with the expected
output. The test patterns are normally applied to the already manufactured systems.
2. Which is applied to a manufactured system?
a) bit pattern
b) parity pattern
c) test pattern
d) byte pattern
View Answer
Answer: c
Explanation: For testing any devices or embedded systems, we use some sort of selected inputs
which is known as the test pattern and observe the output and is compared with the expected
output. These test patterns are normally applied to the manufactured systems.
3. Which of the following is based on fault models?
a) alpha-numeric pattern
b) test pattern
c) bit pattern
d) parity pattern
View Answer
Answer: b
Explanation: The test pattern generation is normally based on the fault models and this model is also
known as the stuck-at model. The test pattern is based on a certain assumption, that is why it is
called the stuck-at model.
4. Which is also called stuck-at model?
a) byte pattern
b) parity pattern
c) bit pattern
d) test pattern
View Answer
Answer: d
Explanation: The test pattern generation is basically based on the fault models and this type of
model is also known as the stuck-at model. These test patterns are based on a certain assumption,
hence it is known as the stuck-at model.
5. How is the quality of the test pattern evaluated?
a) fault coverage
b) test pattern
c) size of the test pattern
d) number of errors
View Answer
Answer: a
Explanation: The quality of the test pattern can be evaluated on the basis of the fault coverage. It is
the percentage of potential faults that can be found for a given test pattern set, that is fault
coverage equals the number of detectable faults for a given test pattern set divided by the number
of faults possible due to the fault model.
6. What is DfT?
a) discrete Fourier transform
b) discrete for transaction
c) design for testability
d) design Fourier transform
View Answer
Answer: c
Explanation: The design of testability or DfT is the process of designing for the better testability.
7. Which of the following is also known as boundary scan?

a) test pattern
b) JTAG
c) FSM
d) CRC
View Answer
Answer: b
Explanation: The JTAG is a technique for connecting scan chains of several chips and is also known as
boundary scan.
8. What does BILBO stand for?
a) built-in logic block observer
b) bounded input bounded output
c) built-in loading block observer
d) built-in local block observer
View Answer
Answer: a
Explanation: The BILBO or the built-in logic block observer is proposed as a circuit combining, test
response compaction, test pattern generation, and serial input/output capabilities.
9. What is CRC?
a) code reducing check
b) counter reducing check
c) counting redundancy check
d) cyclic redundancy check
View Answer
Answer: d
Explanation: The CRC or the cyclic redundancy check is the error detecting code which is commonly
used in the storage device and the digital networks.
10. What is FSM?
a) Fourier state machine
b) finite state machine

c) fast state machine
d) free state machine
View Answer
Answer: b
Explanation: The FSM is the finite state machine. It will be having a finite number of states and is
used to design both the sequential logic circuit and the computer programs. It can be used for
testing the scan design in the testing techniques.
11. Which of the following have flip-flops which are connected to form shift registers?
a) scan design
b) test pattern
c) bit pattern
d) CRC
View Answer
Answer: a
Explanation: All the flip-flop storing states are connected to form a shift register in the scan design. It
is a kind of test path.
1. Which allows the parallel development of the hardware and software in the simulation?
a) high-level language simulation
b) low-level language simulation
c) cpu simulator
d) onboard simulator
View Answer
Answer: a
Explanation: The high-level language simulation allows parallel development of the software and the
hardware and when two parts are integrated, that will work. It can simulate I/O using the keyboard
as the inputs or task which passes input data for other modules.
2. Which of the following are used to test the software?
a) data entity
b) data entry
c) data table
d) data book
View Answer
Answer: c
Explanation: In the high-level language simulation, many techniques are used to simulate the system
and one such is the data table which contains the data sequences which are used to test the
software.
3. Which allows the UNIX software to be ported using a simple recompilation?
a) pSOS+
b) UNIX compatible library
c) pSOS+m
d) pOS+kernel
View Answer
Answer: b
Explanation: The most of the operating system support or provide the UNIX-compatible library which
supports the UNIX software to be ported using a simple recompilation.
4. Which of the following can simulate the processor, memory, and peripherals?
a) input simulator
b) peripheral simulator
c) memory simulator
d) cpu simulator
View Answer
Answer: d
Explanation: The CPU simulator can simulate the memory, processor, and the peripherals and allow
the low-level assembler code and the small HLL programs to be tested without the actual hardware.
5. How many categories are there for the low-level simulation?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two categories for the low-level simulation. The first category simulates the
memory system, programming model and can offer simple debugging tools whereas the second
category simulation provides timing information based on the number of clocks.
6. Which of the following can simulate the LCD controllers and parallel ports?
a) memory simulator
b) sds
c) input simulator
d) output tools
View Answer
Answer: b
Explanation: There are certain tools which provide powerful tools for simulation and one such is the
SDS which can simulate the processor, memory systems, integrated processor, onboard peripherals
such as LCD controllers and parallel ports.
7. Which of the following provides a low-level method of debugging software?
a) high-level simulator
b) low-level simulator
c) onboard debugger
d) cpu simulator
View Answer
Answer: c
Explanation: The onboard debugger provides a very low-level method of simulating or debugging the
software. It usually handles EPROMs which are plugged into the board or a set of application codes
by providing a serial connection to communicate with the PC or workstation.
8. Which of the following has the ability to download code using a serial port?
a) cpu simulator
b) high-level language simulator
c) onboard debugger
d) low-level language simulator

View Answer
Answer: c
Explanation: The onboard debugger has the ability to download code from a floppy disk or by using a
serial port.
9. What does the processor fetch from the EPROM if the board is powered?
a) reset vector
b) ready vector
c) start vector
d) acknowledge vector
View Answer
Answer: a
Explanation: The processor fetches its reset vector from the table which is stored in the EPROM
when the board is powered and then starts the initialize the board.
10. Which of the following device can transfer the vector table from the EPROM?
a) ROM
b) RAM
c) CPU
d) peripheral
View Answer
Answer: b
Explanation: When the board gets powered up, the reset vector from the table stored in the EPROM
makes the initialisation of the board and is transferred to the RAM from the EPROM through the
hardware where the EPROM memory address is temporarily altered.
11. Which of the following is used to determine the number of memory access in an onboard
debugger?
a) timer
b) counter
c) input
d) memory
View Answer
Answer: b
Explanation: The counter is used to determine a preset number of memory accesses, which is
assumed that the table has been transferred by the debugger and the EPROM address can be safely
be changed.
12. Which of the following has the ability to use the high-level language functions, instructions
instead of the normal address?
a) task level debugging
b) low level debugging
c) onboard debugging
d) symbolic debugging
View Answer
Answer: d
Explanation: The symbolic debugging has the ability to use high-level language functions,
instructions and the variables instead of the normal addresses and their contents.
13. Which of the following debugger works at the operating system level?
a) task level debugging
b) low level debugging
c) onboard debugging
d) symbolic debugging
View Answer
Answer: a
Explanation: The task level debugging has the ability to works at the operating level or at the
particular tasks whereas the low-level debugger cannot set for particular task functions or
operations, it can only set a breakpoint at the start of the routine which sends a message.
1. The time taken to respond to an interrupt is known as
a) interrupt delay
b) interrupt time
c) interrupt latency
d) interrupt function
View Answer
Answer: c
Explanation: The interrupts are the most important function of the embedded system and are
responsible for many problems while debugging the system. The time taken to respond to an
interrupt is called the interrupt latency.
2. Into how many parts does the interrupt can split the software?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: The software interrupt can split into two parts. These are foreground work and
background work.
3. Which of the following allows the splitting of the software?
a) wait statement
b) ready
c) interrupt
d) acknowledgement
View Answer
Answer: c
Explanation: The interrupt can make the software into two main parts and these are foreground
work and background work.
4. Which part of the software is transparent to the interrupt mechanism?
a) background
b) foreground
c) both background and foreground
d) lateral ground
View Answer
Answer: a
Explanation: The interrupt mechanism is transparent to the background software, that is, the
background software is not aware of the existence of the foreground software.
5. Which part of the software performs tasks in response to the interrupts?
a) background
b) foreground
c) lateral ground
d) both foreground and background
View Answer
Answer: b
Explanation: In the foreground work, the tasks are performed in response to the interrupts but in
the background work, the tasks are performed while waiting for an interrupt.
6. In which of the following method does the code is written in a straight sequence?
a) method 1
b) timing method
c) sequence method
d) spaghetti method
View Answer
Answer: d
Explanation: In the spaghetti method, the code is written in a straight sequence in which the analysis
software goes and polls the port to see if there is data.
7. Which factor depends on the number of times of polling the port while executing the task?
a) data
b) data transfer rate
c) data size
d) number of bits
View Answer
Answer: b
Explanation: The data transfer rate can determine the number of times the port is polled while
executing the task.
8. Which of the following can improve the quality and the structure of a code?
a) polling
b) subroutine
c) sequential code
d) concurrent code
View Answer
Answer: b
Explanation: The subroutine can improve the quality and the structure of the code. By using the
polling method, as the complexity increases the software structure rapidly fall and it will become
inefficient. So the subroutine method is adopted.
9. Which of the following are asynchronous to the operation?
a) interrupts
b) software
c) DMA
d) memory
View Answer
Answer: a
Explanation: The interrupts are asynchronous to the operation and therefore can be used with
systems that are the event as opposed to the time driven.
10. Which of the following can be used to create time-driven systems?
a) memory
b) input
c) output
d) interrupts
View Answer
Answer: d
Explanation: The interrupts which are asynchronous can be used with systems that are the event as
opposed to the time driven.
11. What does ISR stand for?
a) interrupt standard routine
b) interrupt service routine
c) interrupt software routine
d) interrupt synchronous routine
View Answer
Answer: b
Explanation: The data transfer codes are written as part of the interrupt service routine which is
associated with the interrupt generation by the hardware.
12. Which can activate the ISR?
a) interrupt
b) function
c) procedure
d) structure
View Answer
Answer: a
Explanation: When the port receives the data, it will generate an interrupt which in turn activates
the ISR.
13. Which code is written as part of the ISR?
a) data receive code
b) sequential code
c) data transfer code
d) concurrent code
View Answer
Answer: c
Explanation: The data transfer codes are written as part of the interrupt service routine which is
associated with the interrupt generation by the hardware.
1. Which interrupts are generated by the on-chip peripherals?
a) internal
b) external
c) software
d) hardware
View Answer
Answer: a
Explanation: The internal interrupts are generated by the serial and parallel ports which are on-chip
peripherals.
2. Which of the following is the common method for connecting the peripheral to the processor?
a) internal interrupts
b) external interrupts
c) software
d) exception
View Answer
Answer: b
Explanation: The common method for connecting the peripheral to the processor is the external
interrupts. The external interrupts are provided through the external pins which are connected to
the peripherals.
3. Which interrupt can make a change in the processor’s mode?
a) internal interrupt
b) external interrupts
c) exceptions
d) software mode
View Answer
Answer: c
Explanation: An exception is an event which changes the software flow to process the event. It
includes both internal and external interrupts which cause the processor to change to a service
routine.
4. How many exceptions does an MC68000 have?
a) 256
b) 128
c) 90
d) 70
View Answer
Answer: c
Explanation: The MC68000 have 256 table entries which describe 90 exceptions.
5. Which interrupts allows a protected state?
b) external interrupt
c) software interrupt
d) both internal and external interrupts
View Answer
Answer: c
Explanation: The software interrupt can change the processor into a protected state by changing the
program flow.
6. How a software interrupt is created?
a) instruction set
b) sequential code
c) concurrent code
d) porting
View Answer
Answer: a
Explanation: The software interrupts includes a set of instructions for handling interrupts. The
instruction set allows a currently executing program to change its flow.
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7. What does SWI stand for?
a) standard interrupt instruction
b) sequential interrupt instruction
c) software interrupt instruction
d) system interrupt instruction

View Answer
Answer: c
Explanation: The instruction set of software interrupts are provided by the special instruction set.
One such is the SWI which is commonly used in Z80.
8. Which of the following use SWI as interrupt mechanism?
a) PowerPC
b) MC68000
c) Z80
d) IBM PC
View Answer
Answer: c
Explanation: The PowerPC and MC68000 use TRAP instruction set for accessing software interrupt.
IBM PC uses 8086 NMI. Z80 uses SWI for accessing software interrupts.
9. Which of the following supplies additional data to the software interrupt?
b) external interrupt
d) nmi
View Answer
Answer: c
Explanation: For using the software interrupt more effectively, the additional data are used, which
specifies the type of the request and data parameters are passed to the specific ISR. This additional
data are offered by certain registers.
10. Which software interrupt is used in MC68000?
a) Internal interrupt
b) TRAP
c) SWI
d) NMI
View Answer
Answer: b
Explanation: The MC68000 uses a software interrupt mechanism for accessing interrupts from the
peripheral in which the instruction are created using the TRAP mechanism.
11. Which of the following are accessible by the ISR in software interrupt mechanism?
a) register
b) interrupt
c) nmi
d) memory
View Answer
Answer: a
Explanation: The additional data are offered by certain registers and these additional data are used
to specify the type of the data parameter and the request with the specific ISR when running in the
software interrupt mode.
12. What allows the data protection in the software interrupt mechanism?
a) Different mode
b) Same mode
c) SWI
d) TRAP
View Answer
Answer: a
Explanation: The switching between user mode and supervisor mode provides protection for the
processor, that is, the different modes in the software interrupt allows the memory and the
associated code and data to be protected from each other.
13. What does NMI stand for?
a) non-machine interrupt
b) non-maskable interrupt
c) non-massive interrupt
d) non-memory interrupt
View Answer
Answer: b
Explanation: The NMI stand for the non-maskable interrupt in which the external interrupts cannot
be masked out.
14. Which NMI is used in the IBM PC?
a) SWI
b) TRAP
c) 80×86 NMI
d) Maskable interrupt
View Answer
Answer: c
Explanation: The most commonly used non-maskable interrupt is the 80×86 NMI, which is
implemented in the IBM PC.
15. Which can be used to pass the status information to the calling software in the software
interrupt mechanism?
a) register
b) memory
c) flag
d) nmi
View Answer
Answer: a
Explanation: In order to use the software interrupt more effectively, the additional data are used to
specify the type of the request and data parameters are passed to the specific ISR. This additional
data are offered by certain registers. These registers are accessible by the ISR and it can also be used
to pass the status information back to the calling software.
1. Which of the following uses clock edge to generate an interrupt?
a) edge triggered
b) level-triggered
d) nmi
View Answer
Answer: a
Explanation: In the edge-triggered interrupt, the clock edge is used to generate an interrupt. The
transition is from a logical low to high or vice versa.
2. In which interrupt, the trigger is dependent on the logic level?
a) edge triggered
b) level-triggered
d) nmi
View Answer
Answer: b
Explanation: In the level-triggered interrupt, the trigger is completely dependent on the logic level.
The processors may require the level to be in a certain clock width so that the shorter pulses which
are shorter than the minimum pulse width are ignored.
3. At which point the processor will start to internally process the interrupt?
a) interrupt pointer
b) instruction pointer
c) instruction boundary
d) interrupt boundary
View Answer
Answer: c
Explanation: After the recognition of the interrupt, and finds that it is not an error condition with the
currently executing interrupt, then the interrupt will not be internally executed until the current
execution has completed. This point is known as the instruction boundary. At this point, the
processor will start to internally process the interrupt.
4. What does 80×86 use to hold essential data?
a) stack frame
b) register
c) internal register
d) flag register
View Answer
Answer: a
Explanation: The MC68000 and 80×86 family use stack frame for holding the data whereas RISC
processors use special internal registers.
5. What does the RISC processor use to hold the data?
a) flag register
b) accumulator
c) internal register
d) stack register
View Answer
Answer: c
Explanation: The RISC processors uses special internal registers to hold data whereas the 80×86 and
MC68000 family uses stack register to hold the data.
6. Which of the following is a stack-based processor?
a) MC68000
b) PowerPC
c) ARM
d) DEC Alpha
View Answer
Answer: a
Explanation: The MC68000, Intel 80×86 and most of the b-bit controllers are based on the stack-
based processors whereas PowerPC, DEC alpha, and ARM are RISC families which have a special
internal register for holding the data.
7. Which of the following is used to reduce the external memory cycle?
a) internal hardware stack
b) internal software stack
c) external software stack
d) internal register
View Answer
Answer: a
Explanation: Some of the processors use internal hardware stack which helps in reducing the
external memory cycle necessary to store the stack frame.
8. How many interrupt levels are supported in the MC68000?
a) 2
b) 3
c) 4
d) 7
View Answer
Answer: d
Explanation: The MC68000 has an external stack for holding the data. The MC68000 family supports
a seven interrupt level which are encoded into three interrupt pins.
9. How many interrupt pins are used in MC68000?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: The MC68000 family supports a seven interrupt level which are encoded into three
interrupt pins. These interrupt pins are IP0, IP1, and IP2.
10. Which priority encoder is used in MC68000?
a) 4-to-2 priority encoder
b) LS148 7-to-3
c) 2-to-4 priority encoder
d) LS148 3-to-7
View Answer
Answer: b
Explanation: The LS148 7-to-3 priority encoder is used in MC68000. This converts the seven external
pins into a three-bit binary code.
11. Which of the following converts the seven external pins into a 3-bit binary code?
a) priority encoder
b) 4-to-2 priority encoder
c) LS148 7-to-3
d) 2-to-4 priority encoder
View Answer
12. Which of the following ensures the recognition of the interrupt?
a) interrupt ready
b) interrupt acknowledge
c) interrupt terminal
d) interrupt start
View Answer
Answer: b
Explanation: The interrupt level remains asserted until its interrupt acknowledgment cycle ensures
the recognition of the interrupt.
13. Which of the following is raised to the interrupt level to prevent the multiple interrupt request?
a) internal interrupt mask
b) external interrupt mask
c) non-maskable interrupt
d) software interrupt
View Answer
Answer: a
Explanation: The internal interrupt mask is raised to the interrupt level, in order to prevent the
multiple interrupt acknowledgments.
1. What does ICE stand for?
a) in-circuit emulation
b) in-code EPROM
c) in-circuit EPOM
d) in-code emulation
View Answer
Answer: a
Explanation: The ICE or in-circuit emulation is one the traditional method used to emulate the
processor in the embedded system so that the software can be downloaded and can be debugged in
situ in the end application.
2. Which of the following is a traditional method for emulating the processor?
a) SDS
b) ICE
c) CPU simulator
d) Low-level language simulator
View Answer
Answer: b
Explanation: The SDS is one of the simulation tool used in the embedded systems. CPU simulator and
the low-level simulator are the other kinds of the simulator used in the embedded system design.
3. Which of the following does not have the ability to get hundred individual signal cables into the
probe in the emulation technique?
a) OnCE
b) BDM
c) ICE
d) JTAG
View Answer
Answer: c
Explanation: The in-circuit emulation does not have the ability to get a hundred individual signal
cables into the probe. This problem comes under the physical limitation of the probe, that is as the
density of the processor increases the available sockets which provide good electrical contacts is
becoming harder which causes a restriction to the probe.
4. What does JTAG stand for?
a) joint tag address group
b) joint test address group
c) joint test access group
d) joint test action group

View Answer
Answer: d
Explanation: The JTAG is a joint test action group which is an electronics industry association which
developed the interfacing port that is standardised for testing the devices.
5. Which of the following allows access to all the hardware within the system?
a) debugger
b) JTAG
c) onboard debugger
d) simulator
View Answer
Answer: b
Explanation: The JTAG can access all the hardware within the system. They provide a way of taking
over the pins of a device and allows the different bit patterns to be imposed on the pins which allow
other circuits to be tested with the imposed pins.
6. Which of the following works by using a serial port?
a) Simulator
b) JTAG
c) BDM
d) OnCE
View Answer
Answer: b
Explanation: The JTAG works by using a serial port and clocking data into a shift register and the
output of the shift register drives the pins under the control of the port.
7. What is meant by OnCE?
a) on-chip emulation
b) off-chip emulation
c) one-chip emulation
d) once-chip emulation
View Answer
Answer: a
Explanation: The OnCE is an on-chip emulation which is a debugging facility used in the digital signal
processor chips.
8. Which debugging facility is used in the Motorola’s DSP 56x0x family?
a) JTAG
b) ICE
c) OnCE
d) BDM
View Answer
Answer: c
Explanation: The on-chip emulation provides a debugging facility in the DSP chips. The OnCE is
developed for Motorola’s DSP 56x0x family.
9. Which facility provides the provision of the debug ports in the ICE technique?
a) simulator
b) emulator
c) debug support
d) jtag
View Answer
Answer: c
Explanation: The debugging support to the processor enables the processor to be a single stepped
and breakpoint under remote control from a host or the workstation. This facility can provide the
provision of the debug ports.
10. How the additional registers are accessed in the OnCE?
a) parallel port
b) serial port
c) jtag
d) address register
View Answer
Answer: b
Explanation: The on-chip emulation can access additional registers by using a special serial port
within the device that provides control over the processor and access to its internal registers.
11. Which of the following emulators can provide its own in circuit emulation facility?
a) Simulator
b) Debugger
c) SDS
d) OnCE
View Answer
Answer: d
Explanation: Every system can provide its own in circuit emulation facilities by hooking the port to an
interface port in a workstation or in the PC while connecting the OnCE port to an external connector.
12. What does BDM stand for?
a) background debug mode
b) basic debug mode
c) basic debug microcode
d) background decode mode
View Answer
Answer: a
Explanation: The BDM or background debug mode is similar to the on-chip emulator with a slight
difference. BDM is provided on the Motorola MC683xx series of processors and for the 8-bit
microcontroller like MC68HC12 etc.
13. Which emulator is used in MC68HC12?
a) JTAG
b) BDM
c) On-CE
d) SDS
View Answer
Answer: b
Explanation: The BDM or the background debug mode is provided on the Motorola MC683xx series
of processors and for several 8-bit microcontrollers. One such microcontroller is the MC68HC12.
14. Which of the following takes the processor, when the processor enters the BDM mode?
a) address code
b) high-level microcode
c) low-level microcode
d) data code
View Answer
Answer: c
Explanation: When the processor enters into the BDM mode, low-level microcode takes the
processor which allows the breakpoint to be set, registers to be accessed and so on.
15. Which of the following has the additional circuitry which supports the background debug mode?
a) memory
b) input
c) peripheral
d) processor
View Answer
Answer: d
Explanation: The processor has the additional circuitry which can provide special support for the
background debug mode and is under the control of the remote system connected to its BDM port.
1. Which of the following allows the reuse of the software and the hardware components?
b) memory design
c) peripheral design
d) input design
View Answer
Answer: a
Explanation: The platform design allows the reuse of the software and the hardware components in
order to cope with the increasing complexity in the design of embedded systems.
2. Which of the following is the design in which both the hardware and software are considered
during the design?
c) software/hardware codesign
d) peripheral design
View Answer
Answer: c
Explanation: The software/hardware codesign is the one which having both hardware and software
design concerns. This will help in the right combination of the hardware and the software for the
efficient product.
3. What does API stand for?
a) address programming interface
b) application programming interface
c) accessing peripheral through interface
d) address programming interface
View Answer
Answer: b
Explanation: The platform-based design helps in the reuse of both the hardware and the software
components. The application programming interface helps in extending the platform towards
software applications.
4. Which activity is concerned with identifying the task at the final embedded systems?
b) compilation
c) scheduling
View Answer
Answer: d
Explanation: There are many design activities associated with the platforms in the embedded system
and one such is the task-level concurrency management which helps in identifying the task that
needed to be present in the final embedded systems.
5. In which design activity, the loops are interchangeable?
a) compilation
b) scheduling
c) high-level transformation
View Answer
Answer: c
Explanation: The high-level transformation is responsible for the high optimizing transformations,
that is, the loops can be interchanged so that the accesses to array components become more local.
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6. Which design activity helps in the transformation of the floating point arithmetic to fixed point
arithmetic?
b) scheduling
c) compilation
View Answer
Answer: a
Explanation: The high-level transformation are responsible for the high optimizing transformations,
that is, for the loop interchanging and the transformation of the floating point arithmetic to the fixed
point arithmetic can be done by the high-level transformation.
a) scheduling
c) hardware/software partitioning
d) compilation
View Answer
Answer: c
Explanation: The hardware/software partitioning is the activity which is in charge of mapping

operations to the software or to the hardware.
8. Which of the following is approximated during hardware/software partitioning, during task-level

concurrency management?
a) scheduling
b) compilation
c) task-level concurrency management
d) high-level transformation
View Answer
Answer: a
Explanation: The scheduling is performed in several contexts. It should be approximated with the
other design activities like the compilation, hardware/software partitioning, and task-level
concurrency management. The scheduling should be precise for the final code.
9. Which of the following is a process of analyzing the set of possible designs?
a) design space exploration
b) scheduling
c) compilation
View Answer
Answer: a
Explanation: The design space exploration is the process of analyzing the set of designs and the
design which meet the specification is selected.
10. Which of the following is a meet-in-the-middle approach?
a) peripheral based design
b) platform based design
c) memory based design
d) processor design
View Answer
Answer: b
Explanation: The platform is an abstraction layer which covers many possible refinements to a lower
level and is mainly follows a meet-in-the-middle approach.

Unit 2 - Week 1: Assignment 1

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16/05/2018 Real Time Operating System - - Unit 2 - Week 1

Courses » Real Time Operating System

Announcements Course Ask a Question Progress Mentor

Week 1 1) Which one of the following is an important characteristic of a hard 1 point

The result produced by the task is discarded if produced after deadline

Issue a book using a library management system

No, the answer is incorrect.

Maximization of throughput

They have diﬀerent periods

No, the answer is incorrect.

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Courses » Real Time Operating System

Announcements Course Ask a Question Progress Mentor

Priority(T1)=1, Priority(T2)=2, Priority(T3)=3

Priority(T1)=2, Priority(T2)=1, Priority(T3)=3

No, the answer is incorrect.

Poor transient overload handling

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Courses » Real Time Operating System

Announcements Course Ask a Question Progress Mentor

Week 4 Task Execution Time Period Deadline

Task1 20 100 100

Task3 40 400 400

Not likely to be schedulable but no guarantee can be given

Likely to be schedulable but no guarantee can be given

Task Phase Execution Time Period Deadline

Task1 200 20 100 100

Task2 150 25 150 150

A piece of code in which a shared non-preemptable resource is

T1, T2, and T4

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Courses » Real Time Operating System

Announcements Course Ask a Question Progress Mentor

T1, T2, and T4

It is not possible to design a resource sharing algorithm when task

In the resultant allocation, the typical utilization of each processor is

The priority ceiling protocol (PCP) can be considered to be a satisfactory

POSIX 1003.4 (real-time standard) requires that real-time processes be

The cost of developing and testing a program on the operating system

Maintenance cost would increase for programs running on the operating

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Courses » Embedded Systems-- Design Verification and Test

Announcements Course Ask a Question Progress Mentor FAQ

System-level Accepted Answers:

2 inputs and 2 outputs

© 2014 NPTEL - Privacy & Terms - Honor Code - FAQs -

1 of 3 Friday 09 November 2018 07:02 AM

System 4) A clock withPowered

No, the answer is incorrect.

No, the answer is incorrect.

first-come, first-served scheduling

shortest job scheduling

none of the mentioned

No, the answer is incorrect.

Complex Scheduler in terms of computation

2 of 3 Friday 09 November 2018 07:02 AM

Schedule takes a lot of time

none of the above

No, the answer is incorrect.