1.

ARM stands for _____________

a) Advanced Rate Machines
b) Advanced RISC Machines
c) Artificial Running Machines
d) Aviary Running Machines
View Answer
Answer: b
Explanation: ARM is a type of system architecture.
2. The main importance of ARM micro-processors is providing operation with ______
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management
View Answer
Answer: a
Explanation: The Stand alone feature of the ARM processors is that they’re economically viable.
3. ARM processors where basically designed for _______
a) Main frame systems
b) Distributed systems
c) Mobile systems
d) Super computers
View Answer
Answer: c
Explanation: These ARM processors are designed for handheld devices.
4. The ARM processors don’t support Byte addressability.
a) True
b) False
View Answer
Answer: b
Explanation: The ability to store data in the form of consecutive bytes.
5. The address space in ARM is ___________
a) 224
b) 264
c) 216
d) 232
View Answer
Answer: d
Explanation: None.
6. The address system supported by ARM systems is/are ___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian
View Answer
Answer: d
Explanation: The way in which, the data gets stored in the system or the way of address
allocation is called as address system.
7. Memory can be accessed in ARM systems by __________ instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v
View Answer
Answer: b
Explanation: None.
8. RISC stands for _________
a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer
View Answer
Answer: c
Explanation: This is a system architecture, in which the performance of the system is improved
by reducing the size of the instruction set.
9. In the ARM, PC is implemented using ___________
a) Caches
b) Heaps
c) General purpose register
d) Stack
View Answer
Answer: c
Explanation: PC is the place where the next instruction about to be executed is stored.
10. The additional duplicate register used in ARM machines are called as _______
a) Copied-registers
b) Banked registers
c) EXtra registers
d) Extential registers
View Answer
Answer: b
Explanation: The duplicate registers are used in situations of context switching.
11. The banked registers are used for ______
a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned
View Answer
Answer: a
Explanation: When switching from one mode to another, instead of storing the register contents
somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual
registers.
12. Each instruction in ARM machines is encoded into __________ Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
View Answer
Answer: c
Explanation: The data is encrypted to make them secure.
13. All instructions in ARM are conditionally executed.
a) True
b) False
View Answer
Answer: a
Explanation: None.
14. The addressing mode where the EA of the operand is the contents of Rn is ______
a) Pre-indexed mode
b) Pre-indexed with write back mode
c) Post-indexed mode
d) None of the mentioned
View Answer
Answer: c
Explanation: None.
15. The two I2C signals are _____________and ____________.

a. Serial data, serial clock

b. Serial select, serial access

c. Serial address, parallel data

d. Parallel address, Parallel clock

16. Serial Peripheral Interface bus allows ___________.

a. Half/full

b. Synchronous

c. Serial communication with external devices

d. All of the above

17. Thumb-2 technology enhances the 16 bit Thumb instruction set with

a. Intermixing of 32 bits and 16 bits instructions

b. Only 32 bits instructions

c. Only 16 bits instructions

d. None of the above

18.

Fixed instruction length is a feature of one of the following architecture.

a) CISC
b) RISC
c) X86
d) None of the above

19. Evaluate the following statements and select the appropriate answer given from the choices
below.
I. Von Neumann Architecture shares common memory for Data and Instructions
II. Harvard Architecture has separate physical memories for Data and Instructions
a) Only I is true
b) Only II is true
c) Both I and II are true
d) None of them is true

20. If the Most Significant Byte (MSB) is stored first while ordering byte values for storing data
in memory, it is called as
a) Big-endian
b) Little-endian
c) Big- and Little-endian
d) None of them
21. Which of the following processors belong to Reduced Instruction Set Computers (RISC)
family?
a) ARM
b) AVR
c) MIPS
d) All of the above

22.
Stack is a form of
a) Last In First Out (LIFO)
b) First In First Out (FIFO)
c) Both a and b
d) None of the above

23.
In the ARM Nomenclature ARMxTDMI, D and M stand for
a) Debug and Fast Multiplier units are present
b) Division and Multiplier units are present
c) Debugger and Multiplier units are not present
d) Division and Multiplier units are not present
24.
Evaluate the following statements
I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current
processor mode
II. R14 is the link register where the core puts the return address on executing a subroutine
III. R15 is the program counter and contains the address of the next instruction to be fetched
a) All the options are true
b) I and II are true
c) II and III are true
d) I and III are true

25.
When the processor is executing simple data processing instructions, the pipeline enables one
instruction to be completed every clock cycle, this is also called as _____
a) Throughput
b) Latency
c) Execution
d) None of the above

26.
An instruction that is used to move data from an ARM Register to a Status Register (CPSR or
SPSR) is called _______.
a) MRC
b) MRS
c) MSR
d) MCS

27.
The fastest data access is provided using _______.
a) Caches
b) DRAM‟s
c) SRAM‟s
d) Registers

28. Memory size of ARM Processor is

a) 1Gb
b) 2Gb
c) 4Gb
d) 8Gb
29. ARM Cortex M3 is a
a)16 bit processor
b) 32 bit processor
c) 8 bit processor
29. Arm processor each register is
a) 16 bit
b)32 bit
c) 8 bit
d) 64 bit

30. In Von Neumann architecture, which among the following handles all the operations of the
system that are inside and outside the processor?
a. Input Unit
b. Output Unit
c. Control Unit
d. Memory Unit
ANSWER: (c) Control Unit

31.
Abort mode generally enters when _______
a. an attempt access memory fails
b. low priority interrupt is raised
c. ARM processor is on rest
d. undefined instructions are to be handled
ANSWER: (a) an attempt access memory fails
32.
Which type of non-privileged processor mode is entered due to raising of high priority of
an interrupt?
a. User mode
b. Fast Interrupt Mode (FIQ)
c. Interrupt Mode (IRQ)
d. Supervisor Mode (SVC)
ANSWER: (b) Fast Interrupt Mode (FIQ)

1. In automotive system , High speed electronic control unit (HECU) are deployed in
a) Fuel injection system
b) Antilock brake systems
c) Power window
d) Only (a) and (b)
2. In Automotive system , Low speed electronic control units (LECU) are deployed in
a) Electronic throttle
b) Steering control
c) Transmission control
d) Mirror control
3. The first embedded system used in automotive application is the microprocessor based
fuel injection system introduced by _______________ in 1968
a) BMW
b) Volkswagen 1600
c) Benz E Class
d) All the above
4. Which of the following serial bus is (are) used for communication in Automotive
Embedded Application ?
a) Controller area network ( CAN)
b) Local interconnected Network ( LIN)
c) Media Oriented System Transport (MOST)
d) All the above
5. CAN Bus is an event driven protocol for communication . State true or false
a) True
b) False
6. What is the minimum number of interface lines required for implementing SPI interface ?
a) 2
b) 3
c) 4
d) 5
7. Which of the following are synchronous serial interface
a) I2C
b) SPI
c) UART
d) Only (a) and (b)
8. RS-232 is synchronous serial interface , State true or False
a) True
b) False
9. What is the maximum number of USB device that can be connected to a USB host ?
a) Unlimited
b) 128
c) 127
d) None of the above
10. In the Zigbee network, which of the following Zigbee entity stores the information about
the network ?
a) Zigbee Coordinator
b) Zigbee Router
c) Zigbee Reduced Function Device
d) All of them
11. Which of the following model is best suited for modeling a data driven embedded system
a) State Machine
b) Data flow graph
c) All the above
d) None of the above
12. Which of the following architecture is best suited for implementing a Digital Signal
Processing (DSP) embedded system
a) Controller architecture
b) CISC
c) Data path architecture
d) None of the above
13. Which of the following is a multiprocessor architecture?
a) SIMD
b) MIMD
c) VLIW
d) None of the above
14. Which of the following is hardware description language?
a) C
b) C++
c) VHDL
d) JAVA
e)