JAIN COLLEGE OF ENGINEEERING AND

TECHNOLOGY, HUBBALLI
(Approved by AICTE, Affiliated to VTU Belagavi, and Recognized by Govt. of Karnataka)

ARM MICROCONTROLLER AND

EMBEDDED SYSTEMS

17EC62

Dept. of Electronics and Communication

Mr. Manjunath G. Kadashetti

Assistant Professor
Dept. of ECE
Jain college of Engg. Hubballi.

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ARM Microcontroller and Embedded systems (17EC62) Samples of MCQ
1. ARM stands for _____________ c) i, iv, v
a)Advanced Rate Machines d) iii, iv, v
b) Advanced RISC Machines
c) Artificial Running Machines 8. RISC stands for _________
d) Aviary Running Machines a) Restricted Instruction Sequencing
Computer
2. The main importance of ARM micro- b) Restricted Instruction Sequential
processors is providing operation with Compiler
______ c) Reduced Instruction Set Computer
a) Low cost and low power d) Reduced Induction Set Computer
consumption
b) Higher degree of multi-tasking 9. In the ARM, PC is implemented using
c) Lower error or glitches ___________
d) Efficient memory management a) Caches
b) Heaps
3. The address space in ARM is ___________ c) General purpose register
a) 224 d) Stack
b) 264
c) 216 10. The additional duplicate register used
d) 232 in ARM machines are called as _______
a) Copied-registers
4. ARM processors where basically b) Banked registers
designed for _______ c) Extra registers
a) Main frame systems d) Extential registers
b) Distributed systems
c) Mobile systems 11. The banked registers are used for
d) Super computers ______
a) Switching between supervisor and
5. The ARM processors don’t support interrupt mode
Byte addressability. b) Extended storing
a) True c) Same as other general-purpose
b) False registers
d) None of the mentioned
6. The address system supported by
ARM systems is/are ___________ 12. Each instruction in ARM machines is
a) Little Endian encoded into __________ Word.
b) Big Endian a) 2 byte
c) X-Little Endian b) 3 byte
d) Both Little & Big Endian c) 4 byte
d) 8 byte
7. Memory can be accessed in ARM
systems by __________ instructions. 13. All instructions in ARM are
i) Store ii) MOVE iii) Load iv) conditionally executed.
arithmetic v) logical a) True
a) i, ii, iii b) False
b) i, ii

Dept. of ECE, JCET, Hubballi 1

ARM Microcontroller and Embedded systems (17EC62)
14. Interrupt priority levels present in a) i
Cortex-M3 processor are b) ii
A. 4 to 124 c) Both i and ii
B. 6 to 144 d) Insufficient data
C. 12 to 64
D. 8 to 256 20. __________ directive is used to indicate
the beginning of the program
15. The instruction, MLA R0,R1,R2,R3 instruction or data.
performs _________ a) EQU b) START
a) R0<-[R1]+[R2]+[R3] c) AREA d) SPACE
b) R3<-[R0]+[R1]+[R2]
c) R0<-[R1]*[R2]+[R3] 21. _________ directive specifies the start of
d) R3<-[R0]*[R1]+[R2] the execution.
a) START b) ENTRY
16. The instructions which are used to
c) MAIN d) ORIGIN
load or store multiple operands are
called as_________ 22. _________ directives are used to
a) Banked instructions initialize operands.
b) Lump transfer instructions a) INT
c) Block transfer instructions b) DATAWORD
d) DMA instructions c) RESERVE
d) DCD
17. The BEQ instructions is used
____________ 23. _________ directive is used to name the
a) To check the equality condition register used for execution of an
between the operands and then branch instruction.
b) To check if the Operand is greater a) ASSIGN
than the condition value and then b) RN
branch c) NAME
c) To check if the flag Z is set to 1 and d) DECLARE
then causes branch
d) None of the mentioned 24. The pseudo instruction used to load
an address into the register is _________
18. The condition to check whether the a) LOAD
branch should happen or not is given b) ADR
by ____________ c) ASSIGN
a) The lower order 8 bits of the d) PSLOAD
instruction
b) The higher order 4 bits of the 25. The instruction, ADD R1, R2, R3 is
instruction decoded as ___________
c) The lower order 4 bits of the a) R1<-[R1]+[R2]+[R3]
instruction b) R3<-[R1]+[R2]
d) The higher order 8 bits of the c) R3<-[R1]+[R2]+[R3]
instruction d) R1<-[R2]+[R3]

19. Which of the two instructions sets the
condition flag upon execution?
i) ADDS R0,R1,R2 ii) ADD R0,R1,R2
Dept. of ECE, JCET, Hubballi
26. Processors that are typically used in
mobile phone, mobile computing
devices, television, and some of the
energy efficient servers are
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ARM Microcontroller and Embedded systems (17EC62)
A. Cortex-R processors
B. Cortex-A processors
C. Cortex-M processors
D. ARM9E series

27. In Cortex-M processors, 'M' stands for

A. multimedia
B. microcontrollers
C. memory
D. MPU

28. In ARM processors, MMU stands for

A. Memory Management Unit
B. Memory Measurement Unit
C. Mold Management Unit
D. Multiple Management Unit

29. _______ instruction is used to get the 1’s

complement of the operand.
a) COMP b) BIC
c) ~CMP d) MVN

30. The offset used in the conditional

branching is __________ bit.
a) 24
b) 32
c) 16
d) 8

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