Microcontroller Sample Questions for CCEE

By. Sumit Kamble

Visiting Faculty
CDAC ACTS, Pune

1) Fixed instruction length is a feature of one of the following architecture.

a) CISC
b) RISC
c) X86
d) None of the above
2) Which of the following register in ARM7 is used to point to the location of currently executing instruction
in a program?
a) R1
b) R5
c) R15
d) R8
3) Evaluate the following statements and select the appropriate answer given from the choices below.
I. Von Neumann Architecture shares common memory for Data and Instructions
II. Harvard Architecture has separate physical memories for Data and Instructions
a) Only I is true
b) Only II is true
c) Both I and II are true
d) None of them is true
4) If the Most Significant Byte (MSB) is stored first while ordering byte values for storing data in memory, it
is called as
a) Big-endian
b) Little-endian
c) Big- and Little-endian
d) None of them
5) How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing
Mode instructions?
a) Faster
b) Slower
c) No difference
d) None of the above
6) Which of the following processors belong to Reduced Instruction Set Computers (RISC) family?
a) ARM
b) AVR
c) MIPS
d) All of the above
7) Stack is a form of
a) Last In First Out (LIFO)
b) First In First Out (FIFO)
c) Both a and b
d) None of the above
8) A CPU wrote „register content‟ into the memory in a Big-endian mode. When the same content is read
back from the memory into a register, the CPU reads it in Little-endian mode.
a) The new content in the register will be different from what was written.
b) The content will be the same.
c) The content may be same or different.
d) Endianness need not be the same while reading and writing the contents into/from the memory.
9) Which of the following statements are true
I. In Little endian mode it is easier to determine a sign of the number
II. Little endian mode is easier for addition and multiplication of multi-precision numbers
III. Big endian mode is easier to divide two numbers
IV. Big endian mode is easier to compare two numbers
a) I & II are true
b) III & IV are true
c) I & III are true and II and IV are false
d) I & II are false and III and IV are true
10) Consider a four-bit ALU which does four bit arithmetic. When the following four bit numbers are added,
what is the status of NZCV flags?
1101
+ 1011
a) NZCV = 0111
b) NZCV = 1000
c) NZCV = 1001
d) NZCV = 1010
11) In the ARM Nomenclature ARMxTDMI, D and M stand for
a) Debug and Fast Multiplier units are present
b) Division and Multiplier units are present
c) Debugger and Multiplier units are not present
d) Division and Multiplier units are not present
12) The MCLK speed can be reduced to allow access to ______________.
a) Faster peripherals
b) Slower peripherals
c) CPU
d) All of the above
13) A bus cycle request that transfers to or from an address which is unrelated to the address used in the
preceding cycle is called a ___________.
a) Sequential Cycle
b) Internal Cycle
c) Non-Sequential Cycle
d) Coprocessor Register Transfer Cycle
14) Evaluate the following statements
I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode
II. R14 is the link register where the core puts the return address on executing a subroutine
III. R15 is the program counter and contains the address of the next instruction to be fetched
a) All the options are true
b) I and II are true
c) II and III are true
d) I and III are true
15) How many bits are required to specify the Register operands in anARM7 instruction?
a) 32 bits
b) 16 bits
c) 4 bits
d) 2 bits

16) When the processor is executing simple data processing instructions, the pipeline enables one instruction
to be completed every clock cycle, this is also called as _____
a) Throughput
b) Latency
c) Execution
d) None of the above

17) If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4
instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or
exceptions while executing them.
a) 12 cycles
b) 6 cycles
c) 9 cycles
d) 4 cycles

18) Which of the following statements are true with respect to pipelining.
I. Pipelining is an implementation technique whereby multiple instructions are overlapped in execution. It is
not visible to the programmer
II. Each step is called a pipe stage or pipe segment
III. Pipeline machine cycle is the time required to move an instruction one step down the pipeline
a) All are true
b) I and III are true
c) II and III are true
d) None of them are true

19) Control signals can be categorized by the pipeline stage that uses them. Which one of the following
signal could be used in the Execution stage of an instruction?
a) MemRead
b) RegWrite
c) ALUop
d) PCsrc

20) When the number of stages in a pipeline increases from 3 to 5, then the ______.
a) Throughput reduces
b) Latency reduces
c) Throughput and latency increases
d) Throughput increases and latency reduces
21) State whether the following statement is either true or false. Reset vector is the location of the first
instruction executed by the processor when power is applied. This instruction branches to the initialization
code.
a) True
b) False
22) An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is
called _______.
a) MRC
b) MRS
c) MSR
d) MCS

23) Instruction used to Test equality of two 32-bit values in ARM7 is called _____.
a) TEQ
b) TST
c) EOR
d) None of the above

24) Instruction used to multiply R5 contents by R4 and to store the result into R6 is called ______________.
a) MUL R6, R5, LSL #2
b) MUL R6, R5, R4
c) MUL R6, R5, LSR #2
d) None of the above

25) Which among the following data processing instructions does not use the barrel shifter?
a) ADD R2, R5, R4
b) MOV R5, R4, LSL #2
c) MOV r5, R4, LSR #2
d) MOV r5, R4, ROR #2

26) If the initial register contents of R0, R1 and R2were

R0= 0x00000000
R1= 0x02040608
R2= 0x10305070
Assume R0 is the result register, after one of the operations below was performed on
R1 and R2, which has been modified to R0 = 0x12345678
What was the operation performed on the contents of R2 and R1?
a) AND
b) ORR
c) BIC
d) MUL

27) R1 = 0b1111
R2 = 0b0101
BIC R0, R1, R2
a) R0 = 0b1010
b) R0 = 0b1111
c) R0 = 0b0101
d) R0 = 0b1100
28) Status of Z flag after the execution of CMP instruction given below, when
R0 = 12; R9 = 12; is
CMP R0, R9
a) Z = 1
b) Z = 0
c) Same as previous value
d) None of the above
29) What are the contents of R1 and R2after
MVNR1 R2 are executed, assume R2 is 0x01010101
a) i) R2 = 0x01010101 ii) R1 = 0x01010101
b) i) R2 = 0x01010101 ii) R1 = 0x10101010
c) i) R2 = 0x10101010 ii) R1 = 0x01011101
d) i) R2 = 0x01100110 ii) R1 = 0x01010101

30) Equivalent of Rd = NOT(Rm) this operation is performed by which instruction

a) MVN
b) NEG
c) EOR
d) TST

31) Which of the following instruction ignores Operand1

a) MOV
b) MUL
c) ADD
d) SUB

32) The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN
Why is the V flag unaffected by the logical data processing instructions?
a) Since V flag and C flag are always the same after any logical operations
b) Because it will delay the execution of logical operations
c) V flag is relevant only when an Arithmetic operation is performed
d) None of the above

33) A data processing instruction where PC(R15)is written into takes the following cycles for execution:
a) 1S
b) 1S+I
c) 2S+1N
d) 2S+1N+1I

34) Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer
contained in R0 and R1, and place the result in R4 and R5.
a) ADD r4, r0, r2 ; ADC r5, r1, r3 ;
b) ADDS r4, r0, r2 ; ADCS r5, r1, r3 ;
c) ADD r4, r0, r2 ; ADD r5, r1, r3 ;
d) ADD r4, r0, r2 ; ADCS r5, r1, r3 ;

35) State whether the following statement is either true or false. We can represent any number in more than
one normalized notation.
a) True
b) False

36) In a 32- bit IEEE 754 notation, biased value of exponent value ranges from________________.
a) -126 to 127
b) 0 to 127
c) -126 to 0
d) None of the above
37) State whether the following statement is either true or false. Mantissa and exponent will improve the
range and precision respectively.
a) True
b) False

38) Exponent and fraction values for a denormalized number are

a) 0, 0
b) 0 < E < Max, Any bit pattern
c) All 1‟s, Any bit pattern
d) 0, Any non-zero bit pattern

39) Minimum possible denormalized number representation is possible with single precision IEEE 754
format is
a) 2-126
b) 2-127
c) 2-149
d) 2-128

40) Vector processor architecture falls under the following computer architecture
a) SISD
b) MIMD
c) SIMD
d) MISD

41) Vector Floating Point (VFP) architecture is power efficient because of reduction in _______________
and ____________________.
a) Instruction bandwidth and Data hazard checking
b) Instruction bandwidth and pipelining
c) Data Hazard checking and pipelining
d) All of the above

42) Vector Floating Point (VFP) architecture provides ___________floating point architectures.
a) Single precision
b) Double precision
c) Both a and b
d) None of the above

43) If Vector Floating Point (VPF) has to handle 8-single precision numbers, VPF architecture must have
_______ processing elements that work in parallel.
a) 8
b) 16
c) 24
d) 1

44) MRC, MCR are the _______________.

a) Co-processor register transfer instructions
b) Thumb instructions
c) Both a and b
d) Shift instructions
45) The fastest data access is provided using _______.
a) Caches
b) DRAM‟s
c) SRAM‟s
d) Registers

46) The memory which is used to store acopy of data or instructions stored in larger memories, inside the
CPU is called _______.
a) Level 1 cache
b) MMU
c) Registers
d) TLB

47) In the memory hierarchy, as the speed of memory accessincreases the memory size________.
a) Increases
b) Decreases
c) Both
d) None of the above

48) Size of L1 cache compared to that of L2 cache in a system is ___________.

a) Higher
b) Lower
c) Same
d) None of the above

49) Coherence means

a) Multiple copies of different data are not available at each level of hierarchy.
b) Multiple copies of same data are available at each level of hierarchy.
c) Single copy of data is available at only one level of hierarchy.
d) Multiple copies of different data are available at only one level of hierarchy.

50) State whether the following statement is either true or false. In direct mapping, the presence of the block
in memory is checked with the help of block field.
a) True
b) False

51. If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the
Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access
with cache and without cache will be ____________ and ________.
a) 250 nS and 1500 nS
b) 250mS and 150 nS
c) 25 nS and 1500nS
d) 250mS and 1500mS

52. Cache design elements are

a) Block size
b) Cache size
c) Mapping functions
d) All of the above
53. The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______.
a) Set associative
b) Associative
c) Direct
d) Indirect

54. State whether the following statement is either true or false. The set associative map technique combines
the benefits of the direct and associative mapping techniques.
a) True
b) False

55. The memory blocks in Main Memory are mapped on to the cache blocks with the help of ______.
a) Hash functions
b) Vectors
c) Mapping functions
d) None of the above

56. The average time required to reach a storage location in memory and obtain its contents is called_____.
a) Latency time
b) Access time
c) Turnaround time
d) Response time

57. Memory unit accessed by its content is called______.

a) Read only memory
b) Programmable Memory
c) Virtual Memory
d) Associative Memory

58. “Write Back” cache write policy is more efficient in a system where ____.
a) Number of writes are more than reads
b) Number of reads are more than writes
c) Does not depend on the number of reads and writes
d) None of the above

59. Cache memory acts between_______.

a) CPU and Main Memory
b) CPU and FPU
c) MMU and Hard Disk
d) None of these

60. The idea of cache memory exploits the following property of programs ______.
a) Principle of locality
b) on the heuristic 90-10 rule
c) on the fact that references generally tend to be farther
d) all of the above

61. Write Through technique is used in one of the following to write the data back.
a) Virtual memory
b) Main memory
c) Auxiliary memory
d) Cache memory

62. The amount of time required to read a block of data from a disk into memory is composed of seek time,
rotational latency, and transfer time. Rotational latency refers to ______.
a) the time it takes for the platter to make a full rotation
b) the time it takes for the read-write head to move into position over the appropriate track
c) the time it takes for the platter to rotate the correct sector under the head
d) none of the above

63. Which of the following is the reason that the Least Recently Used (LRU) algorithm is usually not used as
a page replacement algorithm?
a) Other practical schemes such as MIN do a better job
b) LRU requires knowledge of the future to work correctly
c) LRU is too inefficient to implement in practice
d) The Clock algorithm always outperforms LRU

64. State whether the following statement is either true or false. Increasing the block size of cache memory is
likely to increase performance primarily because programs exhibit spatial locality.
a) True
b) False

65. State whether the following statement is either true or false. Address of any data in cache memory always
refers to the address of the data in Main Memory and not the address within the cache.
a) True
b) False

66. In an Operating System, each process has its own _____________.

a) address space and global variables
b) open files
c) pending alarms, signals and signal handlers
d) all of the above

67. What is inter-process communication?

a) Communication within the process
b) Communication between two processes
c) Communication between two threads of same process
d) None of the above

68. A scheduling algorithm can use either ___________ priority or ________ priority.
a) static, still
b) static, dynamic
c) live, dead
d) None of the above

69. The priority of a process will _________ if the scheduler assigns it a static priority.
a) change
b) remain unchanged
c) depend on the operating system
d) None of the above
70. State whether the following statement is either true or false. In a system with Unified cache, access to
data in the cache may impact program execution as well.
a) True
b) False

71. The L1 cache is typically split into _____ and ______ cache for the pipelined system
a) Instruction, Data
b) Instruction, Instruction
c) Data, Data
d) All of the above

72. State whether the following statement is either true or false. In a multilevel system cache system, the L2
cache may contain data that is not found in L1 cache.
a. True
b. False

73. Memory management technique in which the OSstores and retrieves data from secondary storage for use
in main memory is called ____________.
a) Fragmentation
b) Paging
c) Mapping
d) None of the above

74. Run time mapping from virtual to physical address is done by ____
a) Memory Management Unit
b) CPU
c) PCI
d) None of the above

75. Operating System maintains the page table for _____________.

a) Each data element
b) Each instruction
c) Each address
d) Each process

76. _____ is the concept in which a process memory is copied into the main memory from the secondary
memory according to the requirement.
a) Paging
b) Demand paging
c) Segmentation
d) Swapping

77. A process is thrashing if ___________________.

a) it is spending more time paging management than executing
b) it is spending less time paging than executing
c) page fault occurs very infrequently
d) swapping could not take place

78. A Page Table contains information on the page including ___________.

a) Base address of each page in physical memory
b) Page read/write permissions
c) Page was written into or not
d) All of the above

79. A virtual memory system uses „First In First Out‟ (FIFO) page replacement policy and allocates a fixed
number of frames to a process. Consider the following statements: P: Increasing the number of page frames
allocated to a process sometimes increases the page fault rate Q: Some programs do not exhibit locality of
reference which of the following is TRUE?
a) Both P and Q are true, and Q is the reason for P
b) Both P and Q are true, but Q is not the reason for P
c) P is false but Q is true
d) Both P and Q are false

80. When a page is selected for replacement, and its modify bit is set :
a) the page is clean
b) the page has been modified since it was read in from the disk
c) the page is dirty
d) a and b

81. When a global variable may be modified by an exception handler, it should be declared as:
a) Constant
b) Static
c) Dynamic
d) Volatile

82. State whether the following statement is either true or false. Interrupt signal can stop the execution of an
assembly instruction in the middle while it is being executed.
a) False
b) True

83. State whether the following statement is either true or false. Full technical specifications of the target
hardware, memory map of the target system may not be available during SW development in most of the
cases.
a. True
b. False

84. When semi-hosting is executed, the debug agent _______________.

a. Suspends program execution
b. Continues program execution
c. Both a and b
d. None of the above

85. ELF means ________________

a. External Library Format
b. Executable and Linkable Format
c. Exclusive Loadable Format
d. None of the above

86. Which of the following is not one of the source files of a linker to form an executable?
a. .obj
b. .lef
c. .so
d. .lib

87. Choose the correct order for default memory map

a. RW->RO->ZI
b. ZI->RO->RW
c. RO->RW->ZI
d. RO->ZI->RW

88. State whether the following statement is either true or false. A high performance bus can be connected to
a low performance bus without bridge.
a. True
b. False

89. When a transfer is required the APB bus moves into the _____________.
a. hold state
b. setup state
c. Rising state
d. None

90. The multi-layer architecture acts as a crossbar switch between___________ ina AMBA 3 AHB
a. Master and slave
b. Master and master
c. Slave and slave
d. None of the above

91. Which of the following may not be on the APB bus

a. USART
b. RAM
c. Keypad
d. Timer module

92. The main advantage of multiple bus organization over the single bus is ________.
a. Reduction in the number of cycles for execution
b. Increase in size of the register
c. Better connectivity
d. None of the above

93. By default DMA is not a ______________.

a. Master
b. Slave
c. Clock
d. All of the above

94. Frequency of sampling is called _________________.

a. Sampling rate
b. Quantization
c. Modulation
d. All of the above

95. A band limited signal can be reconstructed exactly if it is sampled at a rate atleast
a. Maximum frequency
b. Twice the maximum frequency
c. Thrice the maximum frequency
d. All of the above

96. Main advantage of the PWM is that ______________________.

a. Power loss in the switching devices is very high
b. Power loss in the switching devices is very low
c. No power loss in switching devices
d. None of the above

97. I2C master features:

a. Programmable I2C address detection
b. Clock generation
c. Stop bit detection
d. All of the above

98. The two I2C signals are _____________and ____________.

a. Serial data, serial clock
b. Serial select, serial access
c. Serial address, parallel data
d. Parallel address, Parallel clock

99. Serial Peripheral Interface bus allows ___________.

a. Half/full
b. Synchronous
c. Serial communication with external devices
d. All of the above

100. Thumb-2 technology enhances the 16 bit Thumb instruction set with
a. Intermixing of 32 bits and 16 bits instructions
b. Only 32 bits instructions
c. Only 16 bits instructions
d. None of the above

101. On reset, what are the contents of the SREG register?

a)00h
b)ffh
c)1fh
d)11h
102. TIMSK register is used for?
a) Knowing the status of the timer count
b) used for masking the interrupts flags of the Timer0, Timer1 and Timer2
c) it is used for enabling all the timer interrupts
d) it is used for resetting the value of the interrupts
103. Why RETI instruction is used after an ISR?
a) Because it returns with carry
b) because it returns to the main program with all the flags of the SREG raised
c) because it returns to the main program after clearing the roll over flag of the interrupt, so that the
interrupt can be caused again
d) none of the mentioned
104. In AVR what is the Function to Enable Global Interrupt?
a) Cli();
b) Sei();
c) Interrupt Enable();
d) all of the mentioned

105. What is the Use of Enable pin in LCD?

a) To Provide a Pulse
b) At logic low at enable pulse , processor does not process any data
c) To push the data into micro controlled of lcd
d) all of the mentioned
106. In which Communication protocol of AVR Transmit and Receive share same address space?
a) SPI
b) USART
c) UART
d) Both b and c
107. ADC of an AVR Can be operated into two modes?
a) ______________
b) ______________
Answer:
a. Free Running mode
b. Single Shot / one shot mode

108. LCD is connected to Port_______ of Atmega 128/64 and the first Command ____hex is used to
initialize lcd in ___ bit Mode?
Answer:
a) Port A
b) 0x28
c) 4 bit Mode

109. In SPI Protocol the registers used for data transfer are?
a) Shift Registers
b) 32 bit Registers
c) Status Registers
d) Control Register

110. What will happen in that condition, if an interrupt occurs while the micro controller is serving any other
interrupt?
a) both the interrupts will be handled simultaneously
b) the interrupt which is being done first will be served first
c) the interrupt that is more priority in the interrupt vector table will be served first
d) the interrupt having low priority in the interrupt vector table will be served first
111. In AVR what is the ISR address for an external hardware interrupt?
a) 0002h
b) 0004h
c) 0006h
d) all of the mentioned
112. What is the address in the interrupt service routine assigned for the timer0 overflow flag?
a) 0012h
b) 000Ah
c) 0016h
d) all of the mentioned
113. Is the same address is assigned for the timer0 and timer1 overflow flag in the interrupt vector table of
the interrupts?
a) true
b) false
c) can’t be determined
d) depends on the situation
114. External hardware interrupts are assigned to which pins of the atmega32?
a) PORTD.2
b) PORTD.3
c) all of the mentioned
d) none of the mentioned
115. Which register is responsible for handling all the external hardware interrupts?
a) TIMSK
b) GICR
c) MCUCR
d) IVCE
116. By default, INT0-INT2 interrupts are?
a) edge triggered
b) level triggered
c) all of the mentioned
d) none of the mentioned
117. In AVR, which of the following registers are not used for programming timers?
a) TCNT
b) TCON
c) TIFR
d) none of the mentioned
118. What is the use of the prescalar in the operation of the timer?
a) for fast calculations
b) for increasing the time delay given by the timer by decreasing its frequency of operation
c) for removing the concept the reloading of count
d) for easy counter operations
119. What modes are generally used in the operation of the timer0?
a) normal mode
b) CTC mode
c) PWM mode
d) all of the mentioned
120. Timer 0 can act as a counter
a) if the CS02-CS00 are 110 or 111
b) if the FOC0 bit is set to 110
c) none of the mentioned
d) all of the mentioned
121. Which of the timer can operate in the 16 bit condition?
a) timer0
b) timer1
c) timer2
d) all of the mentioned
122. Which of the following will generate the maximum time delay (where f is frequency)?
a) f/2
b) f/4
c) f/16
d) f/32
123. What is the difference in operation of a normal and a CTC mode of a timer?
a) in CTC mode PWM is used
b) here serial timer is monitored
c) her the contents are compared with the OCR register, if value becomes equal then only the timer is
cleared
d) none of the mentioned
124. We can count the pulses on the positive or the negative edge triggered pulse of the clock?
a) true
b) false
c) can’t be determined
d) depends on the circumstances
125. Which pin is used for the input clock of the counter0?
a) PORTB.0
b) PORTB.1
c) PORTB.2
d) PORTB.3
126. Which resource provides clock pulse to AVR timers if CS02-00=6?
a) Internal clock of the AVR
b) external clock of the AVR
c) none of the mentioned
d) all of the mentioned
127. In AVR, which registers are there for the I/O programming of ports?
a) PORT
b) PIN
c) DDR
d) all of the mentioned
128. The data will not go from the port registers to the pin unless:
a) DDR register of that port is set to 0
b) PORT register of that port is set to 1
c) DDR register of that port is set to 1
d) PORT register of that port is set to 0
129. On reset DDR registers of all ports are set to:
a) 0
b) 1
c) none of the mentioned
d) both of the mentioned
130. Which of the following statements are correct?
a) PIN register of a port is used to bring data into CPU from pins
b) PORT register is used to send data out to pins
c) DDR register is used to control the direction of a port
d) all of the mentioned
131. All series of AVR has 8 pins in all of their ports?
a) true
b) false
c) none of the mentioned
d) can’t be determined
132. Which of the following is not a single bit instruction in AVR?
a) SBI
b) PORT
c) CBI
d) all of the mentioned
133. Which of the following is correct about the SBIS instruction?
a) it is used to the monitor the status of the HIGH for the single bit of a port
b) it is a byte oriented instruction
c) It is a 4 byte instruction
d) all of the mentioned
134. Instruction CBI PORTB,1 means
a) clearing the PORTB register
b) clearing the first bit of the PORTB register
c) setting the PORTB register
d) setting the first bit of the PORTB register
135. Which of the following instruction can used to toggle a bit of the PORT?
a) SBI
b) CBI
c) both of the mentioned
d) none of the mentioned
136. What is the main function of the SBIC instruction?
a) it is used to clear a particular bit of a port
b) it is used to jump unconditionally
c) it is used to skip the instruction if a particular bit of a port is zero
d) none of the above mentioned
137. Is the following instruction correct LDI R3,50?
a) Yes
b) No
c) Cant be said
d) none of the mentioned
138. Registers R0-R31 are used for what type of works?
a) they are used for arithmetic and logic instructions
b) they are used for data copy
c) they are used for calculations
d) none of the mentioned
139. Largest value that can be loaded in an 8 bit register is?
a) 11111111h
b) Fh
c) FFh
d) 00h
140. The total space for the data memory available in the AVR based micro controller is?
a) FFH
b) FFFH
c) FFFFH
d) FFFFFH
141. Which out of the following instructions don’t affect the flags of the status register?
a) AND
b) INC
c) OR
d) ADD
142. What is the difference between the two given instructions?
LDI R16,0x34 and LDI R16,$34
a) One copies the hexadecimal value to R16 and the other copies the decimal value to the R16 register
b) One is for command, other is for data
c) One is for assignment, other is for operations
d) Both the commands are the same
143. Which out of the following is not a directive?
a) .EQU
b) .DEVICE
c) .ORG
d) .LDI
144. Is an assembly language a high level language?
a) Yes
b) No
c) Cant be said
d) none of the mentioned
145. A 14 bit program counter can execute a maximum of _________ memory locations?
a) 4K
b) 8K
c) 16K
d) 64K
146. When AVR wakes up, then the value of PC becomes?
a) 00H
b) 000H
c) 0000H
d) 00000H
147. A micro controller at-least should consist of:
a) RAM, ROM, I/O devices, serial and parallel ports and timers
b) CPU, RAM, I/O devices, serial and parallel ports and timers
c) CPU,RAM, ROM, I/O devices, serial and parallel ports and timers
d) CPU, ROM, I/O devices and timers
148. Unlike micro processors, micro controllers make use of batteries because they have:
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
149. What is the order decided by a processor or the CPU of a controller to execute an instruction?
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
150. How are micro controllers classified on the basic of internal bus width?
a) 8,16,32,64 bits
b) 4,8,16,32 bits
c) 8,16 bits
d) 4,16,32 bits
151. How is the performance and the computer capability affected by increasing its internal bus width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width don’t affect the performance in any way
152. Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
153. Give the names of the buses present in a controller for transferring data from one place to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
154. What is the file extension that is loaded in a micro controller for executing any instruction?
a) .doc
b) .c
c) .txt
d) .hex
155. What are the most appropriate criterion for choosing the right micro controller of our choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
156. Why micro controllers are not called general purpose devices?
a) because they are based on VLSI technology
b) because they are not meant to do a single work at a time
c) because they are cheap
d) because they consume low power
157. In AVR micro controllers, ADD instruction affects the status of which of the following bits of a status
register?
a) Z
b) C
c) N
d) all of the mentioned
158. ADC instruction is used for?
a) addition of two 16 bit numbers
b) analog to digital conversion
c) automatic digital control
d) none of the above mentioned
159. In executing subtraction based instructions, state the role of the C flag?
a) if C=1, the result is negative
b) if C=1, the result is positive
c) none of the mentioned
d) all of the mentioned
160. Which of the following is correct about the MUL instruction?
a) it is a byte-by- byte multiplication instruction
b) the product is stored in two registers R1 and R0
c) both of the mentioned
d) none of the mentioned
161. CP instruction alters the value of the register?
a) true
b) false
c) none of the mentioned
d) can’t be said
162. To Generate a delay of 400 ms how many nop instructions will have to be executed on the AVR running
at 8Mhz?
A. 3200000
B. 2300000
C. 2400000
D. 4000000
163. What is the approximate write/Erase cycles of EEPROM ?
A. 100 write/Erase cycles
B. 1000 write/Erase cycles
C. 10000 write/Erase cycles
D. 100000 write/Erase cycles
164. What watchdog timer is capable of doing?
A. Stops microcontroller permanently
B. Reset microcontroller
C. Generate PWM waveform
D. None of these
165. In AVR microcontroller Z pointer register is used for accessing
A. SRAM
B. Flash
C. EEPROM
D. Both Flash & EEPROM
166. The “LPM “ instruction uses register …………….as the address pointer.
A. X
B. Y
C. Z
D. T
167. Find C , Z and H flags bits for the following code
LDI r20 , 0x67
LDI r21 , 0x99
ADD r20 , r21
A. C = 0 , Z =0 , H= 0
B. C = 1 , Z =0 , H= 0
C. C = 1 , Z =1 , H= 1
D. C = 1 , Z =1, H= 0

168. What does this line of code do?

PORTD&= ~(1<<7);

A. it will reset the 7th bit of PORTD without affecting the other bits
B. it will set the 7th bit of PORTD without affecting the other bits.
C. It will reset PORTD
D. It will set PORTD

169. What is the correct sequence of event that happens when an interrupt occurs in AVR.
1. The processor executes the ISR.
2. Current instruction execution is completed.
3. Address of the ISR is loaded into the PC.
4. The address of the next instruction is stored on to the stack.
5. The end of the ISR is indicated by the RETI instruction.
6. The processor loads the PC with the value stored on the stack.

A. 6 – 1 – 4 – 5 – 3 – 2
B. 4 – 3 – 1 – 2 – 5 – 6
C. 2 – 4 – 3 -1 – 5 – 6
D. 4 – 3 – 1 -5 -2 -6
170. In normal mode of 8-bit timer in AVR, when the counter rolls over it goes from …………… to
………………..
A. 0x00 to 0xFF
B. 0xFF to 0xFE
C. 0xFF to 0x00
D. None of these
180. I2C used for …………… communication.
A. serial
B. parallel
C. both serial and parallel
D. none of these
181. AVR instruction which operate only on registers R16 to R31.
A. SBCI
B. SUBI
C. ANDI
D. All of the above
182. COM Rd instruction is used for
A. compare Rd
B. 1’s complement of Rd
C. 2’s complement of Rd
D. 9’s complement of Rd
183. During interrupts and subroutine calls, the return address Program Counter value is stored in
A. Flash memory
B. Stack
C. Both
D. None of these
184. In AVR microcontrollers which of the following is false about interrupts?
A. Priority levels of interrupt sources are fixed.
B. Priority levels of interrupt sources can be changed in software
C. Interrupts can be disabled in software.
D. On reset all interrupt sources are disabled.
185. For a reference voltage of 5 volts, 10-bit ADC represents
A. 0.15 V
B. 4.8 mV/bit
C. 11.7 mV/bit
D. 375 mV/bit

186. To connect a PC by RS232 to an AVR you typically use the AVRs.

A. TWI interface
B. SPI interface
C. UART/USART interface
D. CAN

187. The instruction “IJMP label ”uses ………………. addressing mode.

A. Register indirect addressing mode
B. Immediate addressing mode
C. Indirect addressing mode
D. Register addressing mode

188. When CALL instruction is executed how many location of stack is used?
A. 1
B. 2
C. 3
D. 4
189. What pins are required for serial programming (ISP)?
A. VCC, GND, TXD and RXD
B. VCC, GND, RESET, MISO, MOSI and SCK
C. VCC, GND, TMS, TCK, TDI and TDO
D. None of above
190. If the Watchdog Timer is enabled, it will be enabled in
A. all sleep modes
B. only in power down mode
C. only in extended standby mode
D. ADC noise canceller mode
191. How many total registers are there in arm?
A. 16
B. 17
C. 36
D. 37
192. When the processor is in reset, it is
A. User mode
B. Fast interrupt request mode
C. System mode
D. Supervisor mode
193. Shift from ARM state to Thumb state is achieved using
A. Some form of branching instruction
B. Software interrupt
C. Modifying CPSR
D. None
194. ARM 9 supports …………… stage pipeline
A. 3
B. 4
C. 5
D. 6
195. What is the output of the following?
R0 = 0x00000000
R1 = 0x00000077
RSB R0, R1, #0
A. 0x00000001
B. 0x00000000
C. 0xFFFFFF98
D. 0xFFFFFF89
196. Give an example of an instruction which does not require 'S' to modify the flag bits in the program
status register
i. CMP
ii. CMN
iii. TST
iv. TEQ

A. i,ii,iii,iv
B. i,ii,iii
C. i,ii,iv
D. i,iii,iv

197. What is the significance of “!” in single register load/store instruction of ARM processor?
A. Don’t update base register in post-indexed load/store
B. Don’t update base register in pre-indexed load/store
C. Update base register in post-indexed load/store
D. Update base register in pre-indexed load/store

198. Cortex M3 processor uses

A. ARM ISA
B. Thumb ISA
C. Both ARM & Thumb ISA
D. Thumb2 ISA

199. Which is used when the processor cannot decode an instruction?

A. Software interrupt
B. Data abort vector
C. Undefined instruction vector
D. Interrupt request vector
200. In ARM processors, which of the following registers is automatically saved whenever an interrupt
occurs?
A. CPSR
B. SPSR
C. LR
D. All of the above
201. Which one is ARM bus technology?
A. AMBA
B. SPI
C. PCI
D. USB
202. How many bits of CPSR are used to specify ARM Processor Mode?\
A. 6 bits
B. 5 bits
C. 4 bits
D. 3 bits
203. Which exception vector location need not have a branch or load PC instruction for jumping to its
exception handler?
A. Reset
B. FIQ
C. IRQ
D. SWI
204. What are the two pipelining stages included in ARM 9 from ARM 7?
A. Memory, Execute
B. Memory, Write
C. Write, Execute
D. None of these
205. The interrupt controller (VIC or NVIC) of an ARM microcontroller is connected to the CPU core using
A. Advanced high performance bus (AHB)
B. Advanced peripheral bus (APB)
C. Local bus interface
D. External bus interface
206. The process of removing an existing cache line as part of servicing a cache miss is known as
A. Data streaming
B. Cleaning
C. Eviction
D. Flushing

207. After the execution of the following what is the output of R1

R0 = 0x00000000
R1 = 0x00090000
Mem32 [0x00009000] = 0x01010101
Mem32 [0x00009004] = 0x02020202
LDR R0, [R1, #4]!
A. 0x02020202
B. 0x00009004
C. 0x00009008
D. 0x01010101
208. When an exception occurs, what is the next step the ARM processor performs after the following?
I. Copies CPSR into SPSR_<mode>
II. Sets appropriate CPSR bits
III. Stores the return address in LR_<mode>
A. IV. Set PC to the appropriate exception handler address
B. IV. Set PC to the appropriate vector address
C. IV. Set PC to the reset vector address
D. IV. Change the processor to Thumb state

209. What is the vector address of IRQ?

A. 0x1C
B. 0x18
C. 0x10
D. 0x0C

210. Exception processing must begin in which processor state?

A. ARM state
B. THUMB state
C. ARM or THUMB state
D. None of the above

211. Which of the following is false pertaining to AVR microcontrollers?

A. It has instruction level pipelining
B. Based on RISC architectural design
C. Has Harvard architecture
D. Has Princeton architecture

212. The ideal throughput of an AVR Microcontroller working at 1 MHz is:

A. 16 MIPS (Millions of instructions per second)
B. 1 MIPS (Millions of instructions per second)
C. 12 MIPS (Millions of instructions per second)
D. 20 MIPS (Millions of instructions per second)

213. The drawback of using RISC processor is in terms of ____________?

A. Code density
B. Speed of execution
C. Power Consumption
D. All of the above

214. ATMega 128 microcontroller has _______________.

A. 128 k bytes of internal flash memory
B. 128 k bytes of external flash memory
C. 128 k bytes of internal RAM memory
D. 128 k bytes of external RAM memory

215. AVR microcontroller has _________________.

A. Memory mapped I/o concept
B. I/o mapped I/o concept
C. Both memory mapped and I/o mapped I/o concept
D. None of the above

216. In AVR microcontroller the program counter (PC) points to:

A. FLASH region
B. EEPROM region
C. Both FLAH & EEPROM regions
D. SRAM region

217. The flash memory in ATMega64 microcontroller is organized as _________

A. 64k x 8 bits
B. 64k x 16 bits
C. 32k x 8 bits
D. 32k x 16 bits

218. In AVR microcontroller the stack pointer points __________.

A. Only to internal SRAM
B. Only to external RAM
C. Can point to both internal SRAM and external RAM
D. Only to internal EEPROM

219. In ATMega 128 microcontroller the reset value of stack pointer (SP) is?
A. Undefined
B. 0x10ff
C. 0x00
D. 0x100

220. Which of the following pointer register is used for accessing internal SRAM in AVR?
A. Z pointer
B. X pointer
C. Y pointer
D. All the above

221. The clock source for EEPROM in AVR microcontroller is _________

A. Internal calibrated RC oscillator
B. External clock source
C. External crystal oscillator
D. programmable and can be any of the above
222. In AVR microcontroller EEPROM is used as _____________
A. Program space
B. Data Space
C. Both program space and data space
D. stack space

223. SRAM regions in AVR microcontroller can be accessed by ______________

A. Direct addressing mode
B. Indirect addressing mode
C. Indirect with post increment
D. All the above

224. Which of the following is an invalid instruction in AVR microcontroller?

A. PUSH R0
B. POP R5
C. LD R5, Z+
D. LPM R0, Y+

225. Which flag is checked for the following instruction?

BRLO go_to_back
A. C
B. Z
C. S
D. V

226. In AVR microcontroller, DDRx=0x00 ; ( x is A,B,C ports) and PORTx=0xff; this means________
A. Port is configured as output and writing all port pins logic high
B. Port is configured as output and enabling internal pull-ups
C. Port is configured as input and writing all port pins logic high
D. Port is configured as input and enabling internal pull-ups

227. In AVR microcontroller, which of the following is an example of asynchronous interrupt?

A. INT 0
B. INT 1
C. INT 2
D. All the above

228. In AVR microcontroller, critical section is achieved by the following combination of instructions
__________
A. First instruction SEI and last instruction CLI
B. First instruction CLI and last instruction SEI
C. First instruction CLI and last instruction RETI
D. First instruction SEI and last instruction RETI

229. In AVR microcontroller, which of the following is having the higher priority interrupt?
A. INT 4
B. INT 5
C. INT 6
D. INT 7
230. In ATMega 128 microcontroller, which of the following power saving modes results in very least power
consumption?
A. Power down mode
B. Power save mode
C. Standby mode
D. Idle mode

231. In ATMega 128 microcontroller, which of the following timer modes is best suited for generating
periodic delays?
A. CTC Mode (Clear timer on compare match)
B. Normal Mode
C. PWM modes
D. All the above

232. In ARM architecture, which of the following modes share general purpose registers as well as stack
pointer and link registers?
A. User mode and Supervisor mode
B. Supervisor mode and System mode
C. User mode and System mode
D. IRQ mode and FIQ mode

233. In ARM architecture which of the following modes does not have SPSR register?
A. IRQ mode
B. FIQ mode
C. Supervisor mode
D. User mode

234. In ARM processor, which of the following instructions takes more than 1 clock cycle?
A. ADD r1, r2, r3, ASR # 10
B. SBC r1, r2, r3
C. LDR r1, [r2]
D. All the above

235. Which bit of the CPSR defines the state in ARM processors?
A. CPSR[0]
B. CPSR[1]
C. CPSR[5]
D. CPSR[32]

236. In ARM Cortex M3 processor, the application programs are running in which mode?
A. Handler mode
B. B. Thread Mode
C. Manual Mode
D. D. System Mode

237. In ARM Cortex M3 processor, the stack pointer used by operating system and exception handlers is
______________
A. Main stack pointer
B. B. Process stack pointer
C. Kernel stack pointer
D. All of the above
238. In context of ARM cortex M3 architecture, which statement is not true?
A. Supports NVIC unit to provide the nesting of the interrupt.
B. Systick is 24-bit down-counter used in the Operation system environment.
C. In OS environment application can use SVC instructions to access OS kernel functions and device drivers
D. None of the above.

239. In ARM cortex M3 microcontrollers if an error occurs during the exception processing then it is called
as ________________
A. Pend SV
B. B. Usage fault
C. Hard fault
D. exception error

240. In ARM cortex M3 microcontroller, Interrupt program status register contains ______________?
A. The priority level of the interrupt.
B. Interrupt Service Routine number of the current exception
C. The Interrupt Service Routine number of the serviced exception
D. None of the above

241. In ARM cortex M3 microcontroller, which region supports bit banding?

A. Code
B. B. Peripheral
C. Private Peripheral Bus
D. All of the above

242. Which of the following protocols has open drain configuration on its hardware pins?
A. I2C
B. B. SPI
C. UART
D. CAN

243. In I2C protocol, a master transmitter receives Acknowledge bit (A) from the slave receiver when
________________ happens.
A. Correct slave address is sent
B. Correct data is received be the slave
C. Arbitration lost by master but addressed to slave.
D. All of the above

244. Which of the following communication protocols have prioritized arbitration mechanism in it?
A. SPI
B. I2C
C. UART
D. CAN

245. Thumb-2 technology is implemented in which of the following?

A. All ARM processors
B. All ARM v7 processors
C. ARM v7-A processors only
D. ARM v7-A and ARM v7-R but not ARM v7-M
246. In ATMega 128 microcontroller, multiprocessor communication for UART is achieved primarily using
______________.
A. 9 bit character frame format
B. 10 bit character frame format
C. 8 bit character frame format
D. 11 bit character frame format

247. As per ARM-Thumb procedure call standard (ATPCS), what is the maximum number of arguments
passed to a function to be considered as most efficient?
A. 4 arguments
B. 6 arguments
C. 8 arguments
D. 16 arguments

248. Which of the following processors would be best suited to a system requiring hard real-time responses,
such as a hard drive controller?
A. ARM1136
B. Cortex-A5
C. Cortex-R4
D. Cortex-A9

249. Which assembly instruction would you use to load 5 words starting from the memory location
0x40000000 into the registers r0-r4?
(Assume r9 contains the base address 0x40000000)
A. LDMDB r9, {r0-r4}
B. LDMIA r9, {r0-r4}
C. LDMIB r9, {r0-r4}
D. LDMDA r9, {r0-r4}

250. Which of the following is synchronous full duplex communication protocol?

A. I2C
B. SPI
C. CAN
D. UART

251. How is memory accessed in RISC architecture?

A. load and store instruction
B. opcode instruction
C. memory instruction
D. bus instruction

252. In AVR, which of the following registers are not used for programming timers?
A. TCNT
B. TCON
C. TIFR
D. None of the mentioned

253. Which of the Following is not the Bi-directional Port

A. PORTA
B. PORTB
C. PORTC
D. None of the Above

254. TIMSK register is used for?

A. knowing the status of the timer count
B. used for masking the interrupts flags of the Timer0, Timer1 and Timer2
C. it is used for enabling all the timer interrupts
D. it is used for resetting the value of the interrupts

255. In AVR, what is the ISR address for an external hardware interrupt?
A. 0002h
B. 0004h
C. 0006h
D. all of the mentioned

256. Signal E pin in LCD is used to

A. to latch the data into the data register or command register.
B. Starts data read/write.
C. Both A and B
D. None of the above.

257. What does ISP stands for?

A. In-System Programming.
B. In-Serial Programming.
C. In-System Peripheral.
D. In-Serial Peripheral.

258. In ARM7TDMI, D Stands For

A. embeddedICE Software
B. on-chip Decoder support
C. on-chip Debug support
D. embeddedICE hardware

259. Which of the following is not the Operating mode in ARM

A. USER
B. FIQ
C. Supervisor
D. Define

260. Which type of non-privileged processor mode is entered due to raising of high priority of an
interrupt?
A. User mode
B. Fast Interrupt Mode (FIQ)
C. Interrupt Mode (IRQ)
D. Supervisor Mode (SVC)

261. Abort mode generally enters when _______

A. an attempt access memory fails
B. low priority interrupt is raised
C. ARM processor is on rest
D. undefined instructions are to be handled
262. Which micro controller don't match with its architecture below?
A. Microchip PIC- Harvard
B. MSP430- Harvard
C. ARM7- Von Neumann
D. ARM9- Harvard

263. Which of the following is false, when the execption occurs

A. Copies CPSR to SPSR
B. Stores return Address in LR
C. Sets Aprropriate CPSR bits
D. None of these

264. In Cortex-M3, the Vector Table Offset Register is programmed to be 0x40000000 after reset.
From which address does the Cortex-M3 fetch the address of NMI handler?
A. 0x00000004
B. 0x00000008
C. 0x40000004
D. 0x40000008

265. By default, the "Peripheral" memory region has which memory type?
A. Normal memory
B. Device memory
C. Strongly ordered memory
D. Shared memory

266. The Cortex-M3 processor is the first ARM processor-based on

A. the ARMv7-M architecture
B. the ARMv9-M architecture
C. the ARMv5-M architecture
D. All of the above

267. Which of the following is not Execption handling type

A. Reset
B. SysTick Interrupt
C. SVCall
D. All of above

268. In Fast PWM, we cannot change the frequency of the wave.

A. True
B. False

269. Why are the pulse width modulated outputs required in most of the applications?
A. To control average value of an input variables
B. To control average value of output variables
C. Both A & B
D. None of the above

270. SPI is _____________ .

A. Serial Pheripheral Intercommunication
B. Serial Propostional Interface
C. Serial Pheripheral Interface
D. Serial Pheripheral Intercommunication

271. For SPI, in which register does the data is written in master device?
A. Index register
B. SPDR
C. SPCR
D. Accumulator

272. What is the directional nature of two active wires SDA & SCL usually adopted in I2C Bus for
carrying the information between the devices?
A. Bi-directional
B. Uni-directional
C. Multi-directional
D. None of the above

273. A processor having Harvard architecture in main memory has

(i) distinct address spaces for accessing the program memory and data memory,
(ii)distinct control signals for accessing the program memory and data memory,
(iii) distinct processor instructions for accessing the program memory and data memory,
(iv) distinct data paths for the bytes for data and for the program,
(v) helps easier handling of streams of data that are required to be accessed in cases of
single instruction multiple data type instructions and DSP instructions.
Which of the above is correct??

A. i, iii, iv and v
B. i, ii, iv
C. i, iii and iv
D. all correct

274. In I2C, rising edge on SDA while SCL is high denotes

A. Start condition (S)
B. Stop condition (P)
C. Transfer in progress
D. None of the above

275. Which of the following is a register used for programming AVR's I2C module?
A. TWBR
B. TWCR
C. TWSR
D. All of the mentioned

276. What is the internal Vref of an Atmega32 series?

A. 5V
B. 3.3V
C. 2.56V
D. All of the above

277. In an ADC, we can calculate the output voltage from the formula
A. Step size / Vin
B. Vin / step size
C. Step size * Vin
D. Vref / step size

278. Which of the following is a type of error associated with digital-to-analog converters
(DACs)?
A. Nonmonotonic error
B. Incorrect output codes
C. Nonmonotonic and offset error
D. Offset error

279. In data transfer in UART is done in __________ .

A. Asynchronous start stop format
B. Synchronous start stop format
C. EBDIC format
D. None of the above

280. In UART, RBR register contains the ___________ .

A. Next transmitted character to be read
B. Next received character to be read
C. Current received character to be read
D. Current transmitted character to be read

281. In CAN frame if the IDE bit= 1 then ID field is .......bits.

A. 11 bits
B. 29 bits
C. 12 bits
D. 28 bits

282. What is the start of frame bit of standard frame of CAN bus protocol ?
A. Dominant bit
B. Recessive bit
C. Both A and B
D. None of the above

283. In ARM Cortex M3, watchdog timer consists of a __________ and a 32-bit counter.
A. divide by 2
B. divide by 4
C. divide by 8
D. divide by 16

284. Registers R0-R31 are used for what type of works?

A. they are used for arithmetic and logic instructions
B. they are used for data copy
C. they are used for calculations
D. none of the mentioned

285. The WDMOD (watchdog timer mode) contains _______________.

A. Basic mode
B. Status of the watchdog timer
C. Both A and B
D. None of the Above
286. Which out of the following instructions don't affect the flags of the status register?
A. AND
B. INC
C. OR
D. ADD

287. In AVR data memory is composed of:

A. General Purpose register.
B. I/O memory
C. Internal data SRAM
D. All Of the above

288. On reset DDR registers of all ports are set to:

A. 0
B. 1
C. None of the mentioned
D. Both of the mentioned

289. Which of the below mentioned are not the conditional jumps?
A. BRLO
B. BRMI
C. BRVC
D. None of the mentioned

290. In memory-mapped I/O ____________

A. The I/O devices and the memory share the same address space
B. The I/O devices have a separate address space
C. The memory and I/O devices have an associated address space
D. A part of the memory is specifically set aside for the I/O operation