1.

ARM stands for _____________

a) Advanced Rate Machines
b) Advanced RISC Machines
c) Artificial Running Machines
d) Aviary Running Machines
View Answer
Answer: b
Explanation: ARM is a type of system architecture.
2. The main importance of ARM micro-processors is providing operation with ______
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management
View Answer
Answer: a
Explanation: The Stand alone feature of the ARM processors is that they’re economically viable.
3. ARM processors where basically designed for _______
a) Main frame systems
b) Distributed systems
c) Mobile systems
d) Super computers
View Answer
Answer: c
Explanation: These ARM processors are designed for handheld devices.
4. The ARM processors don’t support Byte addressability.
a) True
b) False
View Answer
Answer: b
Explanation: The ability to store data in the form of consecutive bytes.
5. The address space in ARM is ___________
a) 224
b) 264
c) 216
d) 232
View Answer
Answer: d
Explanation: None.
6. The address system supported by ARM systems is/are ___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian
View Answer
Answer: d
Explanation: The way in which, the data gets stored in the system or the way of address
allocation is called as address system.
7. Memory can be accessed in ARM systems by __________ instructions.
i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v
View Answer
Answer: b
Explanation: None.
8. RISC stands for _________
a) Restricted Instruction Sequencing Computer
b) Restricted Instruction Sequential Compiler
c) Reduced Instruction Set Computer
d) Reduced Induction Set Computer
View Answer
Answer: c
Explanation: This is a system architecture, in which the performance of the system is improved
by reducing the size of the instruction set.
9. In the ARM, PC is implemented using ___________
a) Caches
b) Heaps
c) General purpose register
d) Stack
View Answer
Answer: c
Explanation: PC is the place where the next instruction about to be executed is stored.
10. The additional duplicate register used in ARM machines are called as _______
a) Copied-registers
b) Banked registers
c) Extra registers
d) Extential registers
View Answer
Answer: b
Explanation: The duplicate registers are used in situations of context switching.
11. The banked registers are used for ______
a) Switching between supervisor and interrupt mode
b) Extended storing
c) Same as other general purpose registers
d) None of the mentioned
View Answer
Answer: a
Explanation: When switching from one mode to another, instead of storing the register contents
somewhere else it’ll be kept in the duplicate registers and the new values are stored in the actual
registers.
12. Each instruction in ARM machines is encoded into __________ Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte
View Answer
Answer: c
Explanation: The data is encrypted to make them secure.
13. All instructions in ARM are conditionally executed.
a) True
b) False
View Answer
Answer: a
Explanation: None.
14. The addressing mode where the EA of the operand is the contents of Rn is ______
a) Pre-indexed mode
b) Pre-indexed with write back mode
c) Post-indexed mode
d) None of the mentioned
View Answer
Answer: c
Explanation: None.
15. The effective address of the instruction written in Post-indexed mode, MOVE[Rn]+Rm is
_______
a) EA = [Rn]
b) EA = [Rn + Rm]
c) EA = [Rn] + Rm
d) EA = [Rm] + Rn
View Answer
Answer: a
Explanation: Effective address is the address that the computer acquires from the current
instruction being executed.
16. Which of the following is False?

A. The ability to store data in the form of consecutive bytes.

B. These ARM processors are designed for handheld devices.
C. ARM is a type of system architecture.
D. Both A and B
View Answer
Ans : A

Explanation: Option A is false.

17.The offset used in the conditional branching is __________ bit.

A. 8
B. 16
C. 24
D. 32
View Answer
Ans : C

Explanation: The offset is used to get the new branching address of the process.
18. The duplicate registers are used in situations of _________.

A. Banked switching
B. Extential switching
C. context switching
D. Internal switching
View Answer
Ans : C

Explanation: The duplicate registers are used in situations of context switching.

19. Which instruction is used to list the registers used for execution?

A. ASSIGN
B. RN
C. PSLOAD
D. ADR
View Answer
Ans : B

Explanation: This instruction is used to list the registers used for execution.

20. Which instruction is basically used to check the branch enable bit?

A. BEQ
B. ASSIGN
C. PSLOAD
D. ADR
View Answer
Ans : A

Explanation: BEQ instruction is basically used to check the branch enable bit
1)   Which function/s is/are provided by Integrated Memory Management
Unit in 80386 architecture?
a. Optional on-chip paging
b. 4 levels of protection
c. Virtual Memory Support
d. All of the above
ANSWER: (d) All of the above

2)   Which unit in 80386 DX architecture plays a crucial role in the

conversion of linear address to physical address?
a. Execution
b. Protection
c. Segmentation
d. Paging
ANSWER: (d) Paging
3)   In Intel x86 architecture, which general purpose register is used for
repeated string instructions as well as shift, rotate and loop instructions?
a. EAX (Accumulator)
b. ECX (Counter)
c. EDX (Data register)
d. EBP (Data Pointer)
ANSWER: (b) ECX (Counter)
4)   Which status flag in x86 family is used to enable or disable the
interrupt especially when the Pentium processor operates in the virtual
mode?
a. ID
b. VIP
c. VIF
d. AC
ANSWER: (c) VIF
5)   Which control register in x86 family is reserved for future use and
generally not adopted for current implementation?
a. CR0
b. CR1
c. CR2
d. CR4
ANSWER: (b) CR1
6)   Which functional unit of ARM family architecture is responsible for
upgrading the address register contents before the core reads or writes the
next register value from memory location?
a. Data bus
b. Barrel Shifter
c. Incrementer
d. Instruction Decoder
ANSWER: (c) Incrementer
7)   Which type of non-privileged processor mode is entered due to raising
of high priority of an interrupt?
a. User mode
b. Fast Interrupt Mode (FIQ)
c. Interrupt Mode (IRQ)
d. Supervisor Mode (SVC)
ANSWER: (b) Fast Interrupt Mode (FIQ)
8)   Abort mode generally enters when _______
a. an attempt access memory fails
b. low priority interrupt is raised
c. ARM processor is on rest
d. undefined instructions are to be handled
ANSWER: (a) an attempt access memory fails
9)   In the process of pipelining, which instructions are fetched from the
memory by the ARM processor during the execution of current
instruction?
a. Previous
b. Present
c. Next
d. All of the above
ANSWER: (c) Next
10)   If the three stages of execution in pipelining are overlapped, how
would be the speed of execution?
a. Higher
b. Moderate
c. Lower
d. Unpredictable
ANSWER: (a) Higher
11)   Which parameter/s is/are included in ‘Time to market’ design metric
of an embedded system?
a. Time to prototype
b. Time to refine
c. Time to produce in bulk
d. All of the above
ANSWER: (d) All of the above
12)   How is the nature of instruction size in CISC processors?
a. Fixed
b. Variable
c. Both a and b
d. None of the above
ANSWER: (b) Variable
13)   What is/are the configuration status of control unit in RISC
Processors?
a. Hardwired
b. Microprogrammed
c. Both a and b
d. None of the above
ANSWER: (a) Hardwired
14)   At an active HIGH reset pin of 8051 microcontroller, for how many
machine cycles should the positive going pulse be provided, if the power is
switched ON?
a. only one
b. two
c. three
d. four
ANSWER: (b) two
15)   While designing an embedded system, which sub-task oriented process
allocates the time steps for various modules that share the similar
resources?
a. Simulation and Validation
b. Iteration
c. Hardware-Software Partitioning
d. Scheduling
ANSWER: (d) Scheduling
16)   In DAC 0808, which among the following is configured as a reference
in addition to R-2R ladder and current switches?
a. Voltage amplifier
b. Current amplifier
c. Transconductance amplifier
d. Transresistance amplifier
ANSWER: (b) Current amplifier
17)   In DAC 0808, what is the high speed multiplying input slew rate?
a. 2 mA/μ sec
b. 4 mA/μ sec
c. 8 mA/μ sec
d. 16 mA/μ sec
ANSWER: (c) 8 mA/μ sec
18)   In LPC 2148, which among the following is/are the functions of Mask
register?
a. Byte addressability
b. Relocation to ARM local bus for fastest posible I/O timing
c. Treating sets of port bits in the form of group without changing other bits
d. All of the above
19)   What is the size range of the alphanumeric LCDs?
a. 1 to 8 characters
b. 8 to 80 characters
c. 100 to 150 characters
d. 250 to 400 characters
ANSWER: (b) 8 to 80 characters
20)   Which type of handshake packet indicates that the device is incapable
of accepting data as it is supposed to be busy with some another task?
a. ACK
b. NAK
c. STALL
d. None of the above
ANSWER: (b) NAK
21)   Which among the following is/are integrated by OTG controller in
order to implement OTG dual-role device functionality?
a. Host Controller
b. Device Controller
c. Master-only I2C bus interface
d. All of the above
ANSWER: (d) All of the above
22)   Which mode of operation is exhibited by RS-485 standard?
a. Single ended
b. Differential
c. Both a and b
d. None of the above
ANSWER: (b) Differential
23)   In Von Neumann architecture, which among the following handles all
the operations of the system that are inside and outside the processor?
a. Input Unit
b. Output Unit
c. Control Unit
d. Memory Unit
ANSWER: (c) Control Unit
24)   In CPU structure, where is one of the operand provided by an
accumulator in order to store the result?
a. Control Unit
b. Arithmetic Logic Unit
c. Memory Unit
d. Output Unit
ANSWER: (b) Arithmetic Logic Unit
25)   In CPU structure, which register provides the address for fetching of
data or instruction especially by means of processor?
a. Data Register
b. Instruction Register
c. Accumulator
d. Memory Address Register
ANSWER: (d)  Memory Address Register
26)   In CPU structure, what kind of instruction to be executed is held by an
instruction Register (IR)?
a. Current (present)
b. Previous
c. Next
d. All of the above
ANSWER: (a) Current (present)
27)   In ADSP 21xx architecture, which notation represents ALU overflow
condition?
a. AC
b. AV
c. NE
d. EQ
ANSWER: (b) AV
28)   Which kind of low-order 16 bits control register is also regarded as
‘Machine Status Word’ (MSW) in order to make it compatible with i286?
a. CR0
b. CR1
c. CR2
d. CR3
ANSWER: (a) CR0
29)   In the test registers, what do/does the linear address bit hold/s with
respect to TLB (Translation Look-aside Buffers)?
a. Physical address
b. Selection between write and lookup of TLB
c. Tag field
d. All of the above
ANSWER: (c) Tag field
30)   For addressing in real mode, which segment plays a significant role in
the storage of destination operands during the string operation?
a. Code Segment
b. Data Segment
c. Stack Segment
d. Extra Segment
ANSWER: (d) Extra Segment
31)   In x86 architecture, which type of gate acts as an intermediary
between code segments at different privilege levels (PLs)?
a. Call gates
b. Task gates
c. Interrupt gates
d. Trap gates
ANSWER: (a) Call gates
32)   In Pentium processor, which write buffer is used by the pipeline ALUs
in order to write the result to the memory?
a. External Snoop Write Buffer
b. Internal Snoop Write Buffer
c. Line Replacement Write Buffer
d. Write-back Buffer
ANSWER: (d) Write-back Buffer
33)   Which stage associated with pipelining mechanism recognizes the
instruction that is to be executed?
a. Fetch
b. Decode
c. Execute
d. None of the above
ANSWER: (b) Decode
34)   Which kind of addressing mode for memory access operands support
pre-index and post-index in addition to the generation of memory address
by an immediate value added to a register?
a. Register indirect addressing mode
b. Relative register indirect addressing mode
c. Base indexed indirect addressing mode
d. Base with scale register addressing mode
ANSWER: (b) Relative register indirect addressing mode
35)   Which mnemonic implies ‘plus’ meaning in the branch instructions?
a. BPL
b. BEQ
c. BMI
d. BAL
ANSWER: (a) BPL
36)   In the branch instructions of ARM, what does the mnemonic BVC
imply?
a. Overflow Set
b. Carry Set
c. Carry Clear
d. Overflow Clear
ANSWER: (d) Overflow Clear
37)   Which type of branching instructions of thumb possesses 11-bit
address & is generally applicable for slightly longer jumps in order to
implement the instructions like GOTO of high level languages?
a. Short Conditional Branch
b. Medium Range Unconditional Branch
c. Long Range Subroutine Calls
d. None of the above
ANSWER: (b) Medium Range Unconditional Branch
38)   Which types of an embedded systems involve the coding at a simple
level in an embedded ‘C’, without any necessity of RTOS?
a. Small Scale Embedded Systems
b. Medium Scale Embedded Systems
c. Sophisticated Embedded Systems
d. All of the above
ANSWER: (a) Small Scale Embedded Systems
39)   Which microcontrollers are adopted for designing medium scale
embedded systems?
a. 8-bit
b. 16-bit to 32-bit
c. 64-bit
d. All of the above
ANSWER: (b)  16-bit to 32-bit
40)   In Cortex-A processor series, which among the following is the
standalone and smallest processor in size constraints with high-end
application support?
a. Cortex-A5
b. Cortex-A9
c. Cortex-A53
d. Cortex-A59
ANSWER: (a) Cortex-A5
41)   Which interrupt controller is present in Cortex-A15 processor?
a. GIC-390
b. GIC-500
c. Integrated GIC
d. GIC-400
ANSWER: (c) Integrated GIC
42)   In Cortex-R processor series, which among the following represent/s
dual core configuration along with the space saving the floating point unit?
a. Cortex-R 4
b. Cortex-R 5
c. Cortex-R 7
d. All of the above
ANSWER:(b) Cortex-R 5
43)   For the supplied data, which edge level is necessary for LCD in order
to latch the data?
a. High-to-Low
b. Low-to-High
c. High-to-High
d. Low-to-Low
ANSWER: (a) High-to-Low
44)   In LCD, which function is executed by ‘0x05’ hex command?
a. Shift display left
b. Shift display right
c. Clear display
d. Return cursor to home
ANSWER: (b) Shift display right
45)   In LCD, which hex command performs the function of ‘Display on,
cursor on and blinking’?
a. 0x0A
b. 0x0C
c. 0x0E
d. 0x0F
ANSWER: (d) 0x0F
46)   In DC motor interfacing, which field/s is/are generated by forcing
current through the coil for spinning of the motor? 
a. Electric field
b. Electrostatic field
c. Magnetic field
d. All of the above
ANSWER: (c) Magnetic field
47)   In DC motor interfacing, which modulation controls the duty cycle of
square wave provided at the output by generating variation in the average
DC voltage?
a. Amplitude Modulation
b. Frequency Modulation
c. Pulse Width Modulation
d. Phase Modulation
ANSWER: (c) Pulse Width Modulation
48)   What is the value of maximum data rate in RS 232 standard?
a. 20 kb/s
b. 40 kb/s
c. 80 kb/s
d. 100 kb/s
ANSWER: (a) 20 kb/s
49)   In Modbus Protocol, which codes are included in Request PDU?
a. Function code, Response data
b. Function code, Function data
c. Error code, Exception code
d. All of the above
ANSWER: (b) Function code, Function data
50)   Which category of function code represents the currently used codes
by some companies especially for legacy products?
a. Public
b. User-defined
c. Reserved
d. Exceptions
ANSWER: (c) Reserved
51)   In ISA, what is/are the application/s of Timer2 which acts as a speaker
timer?
a. Date & time maintenance in RAM
b. General purpose timer
c. Diagnostic purpose
d. All of the above
ANSWER: (c) Diagnostic purpose
52)   In ISA, Timer 0 is also regarded as ______
a. System Timer
b. Refresh Timer
c. Speaker Timer
d. All of the above
ANSWER: (a) System Timer
53)   Match the following STKY multiplier (MAC) flag notations with their
meanings in ADSP 21 xx family architecture.
A. MOS —————— 1) Multiplier floating-point invalid operation
B. MIS ——————- 2) Multiplier Underflow
C. MUS —————— 3) Multiplier floating-point overflow
D. MVS —————— 4) Multiplier fixed-point overflow

a. A-3, B-2, C-4, D-1

b. A-2, B-3, C-1, D-4
c. A-1, B-4, C-3, D-2
d. A-4, B-1, C-2, D-3
ANSWER: (d) A-4, B-1, C-2, D-3
54)   In ADSP 21 xx architecture, how many previously executed
instructions are stored in instruction cache of cache memory?
a. 4
b. 8
c. 16
d. 32
ANSWER: (c) 16
55)   In TMS 320 C5X processor, which operation/s is/are performed by
Compare Select & Store Unit (CSSU)?
a. Selection of large word in accumulator for storing into the data memory
b. Comparison between high & low word of accumulator
c. Maintain the record of transition histories
d. All of the above
ANSWER: (d) All of the above
56)   In TMS 320 C5X processor, which memory segment provides
interfacing to external memory mapped peripherals and also serves as
extra data storage space?
a. Program Memory
b. Data memory
c. I/O Memory
d. All of the above
ANSWER: (c) I/O Memory
57)   How are the instructions executed in DSP Processors?
a. In Parallel manner
b. In Sequential manner
c. Both a and b
d. None of the above
ANSWER: (a) In Parallel manner