Q Marks

No
UNIT-I
PIC16FXXX Mid-Range MCU Family Architecture,
Instruction Flow and pipelining,
general instruction format,
Arithmetic Logical Unit (ALU),
Program and data Memory organization,
Basic instruction set summary.
1.BASICS
1 1 The assembler list file generated by an assembler R1_P3_5
mainly includes ________
a. binary codes
b. assembly language statements
c. offset for each instruction
d. All of the above

A (d) All of the above

2 2 1. A microcontroller at-least should consist of:
a) RAM, ROM, I/O devices, serial and parallel ports
and timers
b) CPU, RAM, I/O devices, serial and parallel ports
and timers
c) CPU, RAM, ROM, I/O devices, serial and parallel
ports and timers
d) CPU, ROM, I/O devices and timers
A Answer: c
Explanation: A microcontroller must consist of a
processor as its CPU with some additional peripherals
like RAM, ROM, serial and parallel ports, timers etc.
3 3 Unlike microprocessors, microcontrollers make use of
batteries because they have:
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
A Answer: b
Explanation: Micro Controllers are made by using the
concept of VLSI technology. So here, CMOS based
logic gates are coupled together by this technique that
consumes low power.

4 4 What is the order decided by a processor or the CPU

of a controller to execute an instruction?
a) decode, fetch, execute
b) execute, fetch, decode
c) fetch, execute, decode
d) fetch, decode, execute
A Answer: d
Explanation: While any instruction is being executed,
a microcontroller first fetches the instruction (captures
its operand and operator). After capturing it converts
these operands and operators into their corresponding
hex codes. Hence after this, an instruction can be
 5executed as now it is in the form of 0’s and 1’s (the
format understood by a microcontroller).
5 5 How are microcontrollers classified on the basis of
internal bus width?
a) 8,16,32,64 bits
b) 4,8,16,32 bits
c) 8,16 bits
d) 4,16,32 bits
A Answer: b
Explanation: A microcontroller is classified as a 4 bit
microcontroller if it executes a nibble at a time. It is
called an 8 bit controller if it executes a byte at a time
and is called 16 or 32 bit controller if it executes 2 and
4 bytes at a time respectively.
6 6  How are the performance and the computer capability
affected by increasing its internal bus width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width doesn’t affect the performance in
any way
A Answer: a
Explanation: As the bus width increases, the number
of bits carried by bus at a time increases as a result of
which the total performance and computer capability
increases.
7 7 Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced
Instruction Set Computer
b) Complex Instruction Set Computer, Reduced
Instruction Set Computer
c) Complex Instruction Set Computer, Reliable
Instruction Set Computer
d) Complete Instruction Set Computer, Reliable
Instruction Set Computer
A Answer: b
Explanation: CISC means Complete Instruction Set
Computer because in this a microcontroller has an
instruction set that supports many addressing modes
for the arithmetic and logical instructions, data transfer
and memory accesses instructions. RISC means
Reduced Instruction Set Computer because here a
microcontroller has an instruction set that supports
fewer addressing modes for the arithmetic and logical
instructions and for data transfer instructions.
8 8 Give the names of the buses present in a controller for
transferring data from one place to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
A Answer: c
Explanation: There are 3 buses present in a
microcontroller they are data bus (for carrying data
 from one place to another), address bus (for carrying
the address to which the data will flow) and the control
bus (which tells the controller to execute which type of
work at that address may be it read or write
operation).
9 9 What is the file extension that is loaded in a
microcontroller for executing any instruction?
a) .doc
b) .c
c) .txt
d) .hex
A Answer: d
Explanation: Microcontrollers are loaded with .hex
extension as they understand the language of 0’s and
1’s only.
10 10 What is the most appropriate criterion for choosing the
right microcontroller of our choice?
a) speed
b) availability
c) ease with the product
d) all of the mentioned
A Answer: d
Explanation: For choosing the right microcontroller for
our product we must consider its speed so that the
instructions may be executed in the least possible
time. It also depends on the availability so that the
particular product may be available in our
neighbouring regions or market in our need. It also
depends on the compatibility with the product so that
the best results may be obtained.
11 11 Why microcontrollers are not called general purpose
devices?
a) because they are based on VLSI technology
b) because they are not meant to do a single work at a
time
c) because they are cheap
d) because they consume low power
A Answer: b
Explanation: They are not called general purpose
because they are not meant to do a single work at a
time.
12 12 Which architecture provides separate buses for
program and data memory?
a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
d) All of the mentioned
A Answer: a
Explanation: In Harvard architecture both the volatile
and the non volatile memories are involved, so
separate buses are required for program and data
memory.
13 13 Harvard architecture allows:
a) separate program and data memory
 b) pipe-ling
c) complex architecture
d) all of the mentioned
A Answer: d
Explanation: Harvard architecture allows separate
program and data memory, pipe-line and also has a
complex architecture.
14 14 Which microcontroller doesn’t match with its
architecture below?
a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
A Answer: b
Explanation: MSP430 supports Von Neumann
architecture.
15 15 Which of the two architecture saves memory?
a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
d) None of the mentioned
A Answer: b
Explanation: As only one memory is present in the
Von Neumann architecture so it saves a lot of
memory.
R1_P4
16 Q Which form of clocking mechanism is highly R1_P4_27
efficient and reliable for crystal or ceramic clock
sources for operating at the range of 5- 200 kHz in
PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)

A (b) LP (Low-Power Clocking)

17 Q Which significant feature/s of crystal source R1_P4_28

contribute/s to its maximum predilection and
utility as compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
A (a) All of the above
18 24 Which condition/s of MCLR (master clear) pin allow to R1_P4_16
reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
A (b)  Low
19 25 Generation of Power-on-reset pulse can occur only R1_P4_17
after __________
 a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5
V
c. the detection of variable time delay on power up
mode
d. the detection of current limiting factor
A (a) the detection of increment in VDD from 1.5 V to 2.1
V
20 26 Which crucial feature/function of Brown-Out-Reset R1_P4_24
(BOR) makes the PIC to be completely unique and
distinct from other microcontrollers?
a. It can reset the PIC automatically in running
condition
b. It can reset the PIC even when the supply voltage
increases above 4V
c. It can reset the PIC without enabling the power-up
timer
d. All of the above
A (a)
21 27 What happens when the supply voltage falls below 4V R1_P4_25
during the power-up timer delay of 72ms in PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage
increases irrespective of stability
d. Power-up timer kills 72ms more again

A (a) CPU resets PIC once again in BOR mode

22 28 What output is generated by OSC2 pin in PIC R1_P4_26
oscillator comprising RC components for sychronizing
the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1

A (1/8) x frequency of OSC1

23 29 Which form of clocking mechanism is highly efficient R1_P4_27
and reliable for crystal or ceramic clock sources for
operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
A (b) LP (Low-Power Clocking)
24 30 Which significant feature/s of crystal source R1_P4_28
contribute/s to its maximum predilection and utility as
compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
A (a) All of the above
25 17 Which operational feature of PIC allows it to reset R1_P5_4
 especially when the power supply drops the voltage
below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above
A (b)Brown-out reset
26 18 Which among the below stated reasons is/are R1_P5_5
responsible for the selection of PIC
implementation/design on the basis of Harvard
architecture instead of Von-Newman architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single
instruction cycle
c. Independent bus access provision to data memory
even while accessing the program memory
d. All of the above
A (d) All of the above
2.PIC16FXXX Mid-Range MCU Family Architecture

3.Instruction Flow and pipelining

4. GENERAL INSTRUCTION FORMAT

5. Arithmetic Logical Unit (ALU),

27 1 How many clock pulses are confined by each machine R1_P4_1
cycle of Peripheral-Interface Controllers?
a. 4
b. 8
c. 12
d. 16
A (a) 4
28 2 Which flags are more likely to get affected in status R1_P4_2
registers by Arithmetic and Logical Unit (ALU) of PIC
16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
A (d) All of the above

29 3 Which among the CPU registers of PIC 16C6X/7X is R1_P4_8

not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
A (b) Program Counter Latch (PCLATH) Register
30 4 Which register/s is/are mandatory to get loaded at the R1_P4_9
beginning before loading or transferring the contents
to corresponding destination registers?
a. W
b. INDF
 c. PCL
d. All of the above
A (a) W
31 5 Which status bits exhibit carry from lower 4 bits during R1_P4_12
8-bit addition and are especially beneficial for BCD
addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above
A (b) Digits Carry bit (DC)
32 6 Where do the contents of PCLATH get transferred in R1_P4_15
the higher location of program counter while writing in
PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
A (c) 13th bit
33 7 Where is the result stored after an execution of R1_P5_25
increment and decrement operations over the special
- purpose registers in PIC?
a. File Register
b. Working Register
c. Both a & b 
d. none of the above
A c. Both a & b 
34 8 Which flags of status register are most likely to get R1_P5_26
affected by the single-cycle increment and decrement
instructions?
a. P Flags
b. C Flags
c. OV Flags
d. Z Flags
A  (d)  Z Flags
6. Program and data Memory organization
35 1 How many bits are required for addressing 2K & 4K
program memories of PIC 16C61 respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
A (c) 11 & 12 bits
36 2 Which bank of RFS has a provision of addressing the
status register?
a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2
A (c) Either Bank 1 or Bank 2
37 3 When does it become possible for a bit to get
accessed from bank ‘0’ in the direct addressing mode
of PICs?
a. Only when RPO bit is set ‘zero’
 b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits
of instruction code
d. Cannot Predict
A (a) Only when RPO bit is set ‘zero’

7. Basic Instruction Set Summary

38 1 Which statement is precise in relation to FSR, INDF R1_P4_13
and indirect addressing mode?
a. Address byte must be written in FSR before
executing INDF instruction in indirect
addressing mode
b. Address byte must be written in FSR after
executing INDF instruction in indirect
addressing mode
c. Address byte must be written in FSR at the
same time during the execution of INDF
instruction in indirect addressing mode
d. Address byte must be always written in FSR
as it is independent of any instruction in
indirect addressing mode

a. Only A
b. Only B
c. Only A & B
d. A & D
A (a) Only A
39 2 How many bits are utilized by the instruction of direct R1_p4_33
addressing mode in order to address the register files
in PIC?
a. 2
b. 5
c. 7
d. 8
A c.7

INSTRUCTION SET
40 1 Which instruction is applicable to set any bit while R1_P5_24
performing bitwise operation settings?
a. bcf
b. bsf
c. Both a & b
d. None of the above

A (b) bsf
34
A
35
A
36
A
 IO PORT & PROGRAMMING
41 1 What is the possible range of current limiting resistor R1_P3_20
essential for lightening the LED in certain applications
after pressing the push-button?
a. 25-55 Ω
b. 55-110 Ω
c. 110-220 Ω
d. 220-330 Ω

A (d) 220-330 Ω
42 2 What does the availability of LCD in 16 x 2 typical R1_P3_22
value indicate?
a. 16 lines per character with 2 such lines
b. 16 characters per line with 2 such lines
c. 16 pixels per line with 2 such sets
d. 16 lines per pixel with two such sets

A (b) 16 characters per line with 2 such lines

43 3 Which control line/s act/s as an initiator by apprising R1_P3_23
LCD about the inception of data transmission by the
microcontroller?
a. Enable (EN)
b. Register Select (RS)
c. Read/Write (RW)
d. All of the above
A (a) Enable (EN)
44 4 The display operations in LCD are undertaken on EN R1_P3_24
line with ______
a. 0 to 1 transitions
b. 1 to 0 transitions
c. Both a & b
d. None of the above(b) 1 to 0 transitions
A (b) 1 to 0 transitions
45 5 When can a LCD display the text form of data? R1_P3_25
a. only when RS line is high
b. only when RW line is high
c. only when RS line is low
d. only when RW line is low
A (a) only when RS line is high
46 6 How much delay is necessarily provided after the R1_P3_28
power-on-reset condition in order to overcome the
predicaments related to valid power supply levels
assigned to microcontroller and LCD?
a. 10 ms
b. 12 ms
c. 15 ms
d. 25 ms

A (c) 15 ms
47 7 On which factors do the delay between two characters R1_P3_29
depend for display purposes in LCD?
a. Clock frequency
b. Display module
c. Both a & b
 d. None of the above
A (c) Both a & b
48 8 How many data lines are essential in addition to RS, R1_P3_30
EN and RW control lines for interfacing LCD with
microcontroller?
a. 4
b. 5
c. 8
d. 10
A (c)  8
49 9 How is the latch interfacing with the microcontroller R1_P3_42
related to the number of digital output functions?
a. It increases the number of digital output functions in
a time multiplexed manner
b. It decreases the number of digital output functions
in a time multiplexed manner
c. It increases the number of digital output functions in
a frequency multiplexed manner
d. It decreases the number of digital output functions
in a frequency multiplexed manner
A (a) It increases the number of digital output functions
in a time multiplexed manner
50 10 In an electromechanical relay, the necessity of R1_P3_44
connecting an external base resistance arises only
_________
a. in the presence of an internal pull-up resistor
b. in the absence of an internal pull-up resistor
c. in the absence of an internal push-up resistor
d. in the presence of an internal push-up resistor
A (b) in the absence of an internal pull-up resistor
51 11 Which diodes are employed in the electromechanical R1_P3_45
relays since the inductor current cannot be reduced to
zero?
a. Tunnel Diode
b. Shockley Diode
c. Freewheeling Diode
d. Zener Diode

A (c) Freewheeling Diode

52 12 Where do the power gets dissipated during the R1_P3_46
gradual decay of an inductor current (upto zero value)
by turning OFF the transistor in an electromechanical
relay?
a. Internal resistance of the coil
b. Internal Diode resistance
c. Both a & b
d. None of the above
A (c) Both a & b
53 13  Which register acts as an input-output control as well R1_P_
as data direction register for PORTA in bank 2 of
RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
 d. PCLATH (8A)
A (c) TRISA (85H)

Q
A
Q
A

UNIT-II
ADVANCED PERIPHERALS - Timers, CCP
(Capture/Compare/PWM) module, A/D converter,
Master Synchronous Serial Port (MSSP) module –
SPI mode and I2C mode. Watchdog timer and sleep
mode, Device configuration Bits.
Timers, WDT
1 1 Which timer/s possess an ability to prevent an endless R1_P5_7
loop hanging condition of PIC along with its own on-
chip RC oscillator by contributing to its reliable
operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
A (c) Watchdog Timer (WDT)
2 2 Where are the prescalar assignments applied with a R1_P4_39
usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
A (c) Either RTCC or Watchdog timer
Which bits play a crucial role in specifying the R2_T0_WDT_2

details or reasons associated with the system

wake-up in WDT?

a.PD & TO 
b. C & Z
c. DC & RPO
d. All of the above

3 4 What is the purpose of setting TOIE bit in INTCON

 along with GIE bit?
a. For setting the TOIF flag in INTCON due to
generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to
generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to
generation of PORTB change interrupt
d. None of the above
A (a) 
4 7 Which command enables the PIC to enter into the R1_p4_55
power down mode during the operation of watchdog
timer (WDT)?
a. SLEEP
b. RESET
c. STATUS
d. CLR
A (a) SLEEP
CCP (Capture/Compare/PWM) module
5 Q Where does the comparison level occur for 16-bit R1_P5_1
contents in the compare mode operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0

A (a) Between CCPR1 register & TMR1

6 Q Why are the pulse width modulated outputs required R1_P5_2
in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above
A (b) To control average value of output variables
7 Q What would be the resolution value if oscillator and R1_P5_3
PWM frequencies are 16MHz and 2 MHz
respectively?
a. 2
b. 3
c. 4
d. 8
A (b) 3
8 Q How do the variations in an average value get affected R1_P5_4
by PWM period?
a. Longer the PWM period, faster will be the variation
in an average value
b. Shorter the PWM period, faster will be the variation
in an average value
c. Shorter the PWM period, slower will be the variation
in an average value
d. Longer the PWM period, slower will be the variation
in an average value
A (b) Shorter the PWM period, faster will be the variation
in an average value
9 12 Which among the below mentioned aspect issues are R1_P4_60
 supported by capture/compare/PWM modules
corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
A (d) All of the above
10 13 Which mode allows to deliver the contents of 16-bit R1_P4_61
timer into a SFR on the basis of rising/falling edge
detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
A (a) Capture Mode
11 14 What among the below specified functions is related R1_P4_62
to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable
duty cycle with an user assigned frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change
occurs in an input edge
A (b) Generation of rectangular wave with
programmable duty cycle with an user assigned
frequency
12 Q What happens when the program control enters R1_P4_63
the Interrupt Service Subroutine (ISS) due to
enabling of CCP1IE bit in PIE1 especially during
the initialization of CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new
capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically
copied in TMR1L & TMR1H respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR

A (a) CCP1F bit gets cleared in PIR1 by detecting new R1_P4_64

capture event
13 15 Which register is suitable for the corresponding count,
if the measurement of pulse width is less than 65,535
μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register

A (c) 16-bit register

14 16 The capture operation in counter mode is feasible R1_P4_65
when mode of CCP module is _________
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
 A (a)  synchronized
15 17 What is the fundamental role exhibited by the CCP R1_P4_66
module in compare mode in addition to timer 1?
a. To vary the pin status in accordance to the
precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive
larger periods
d. To vary the status of synchronization levels
A (a) To vary the pin status in accordance to the
precisely controlled time
16 18 How does the pin RC2/CCP1 get configured while R1_P4_67
initializing the CCP module in the compare mode of
operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or
specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1
configuration CCP initialization
A (b) As an output by writing it in TRISC register
19 What is the fundamental role exhibited by the R2_CMP_1
CCP module in compare mode in addition to
timer 1?

a. To vary the pin status in accordance to the

precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to
receive larger periods
d. To vary the status of synchronization levels 

A a. To vary the pin status in accordance to the

precisely controlled time 

20 How does the pin RC2/CCP1 get configured

while initializing the CCP module in the
compare mode of operation?

a. As an input by writing it in TRISC register

b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or
specifying it in TRISC register
d. Compare mode does not support pin
RC2/CCP1 configuration CCP initialization
A/D converter
17 Q Which factors indicate the necessity of sample and R1_P3_47
hold circuit in the process of analog-to-digital
conversion?
a. Instantaneous variation in an input signal
b. Analog-to-digital conversion time
c. Both a & b
 d. None of the above
A (c) Both a & b
18 8 Which channel would be selected if the values of R1_p4_56
channel bits CHS0 & CHS1 are ‘1’ & ‘0’ respectively in
ADC Status Register?
a. AIN0
b. AIN1
c. AIN2
d. AIN3
A (c) AIN2
19 9 Which bit is mandatory to get initiated or set for R1_P4_57
executing the process of analog to digital conversion
in ADCON0?

a. ADIF
b. ADON
c. Go/!Done
d. ADSC1
A (c) Go/!Done
20 10 What would be the value of ADC clock source, if both R1_P4_58
the ADC clock bits are selected to be ‘1’?
a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC
A (d) FRC
21 11 The functionalities associated with the pins RA0- RA3 R1_P4_59
in ADCON1 are manipulated by __________
a. PCFG1 & PCG0
b. VREF
c. ADON
d. All of the above
A (a) PCFG1 & PCG0
22 5 Where do the conversion interrupt flag (ADIF) end R1_p4_52
after an accomplishment of analog-to-digital (ADC)
conversion process?
a. INTCON
b. ADCON0
c. OPTION
d. None of the above
A (b) ADCON0
23 6 How much time is required for conversion per channel R1_p4_53
if PIC 16C71 possesses four analog channels, each
comprising of 8-bits?
a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs
A (c) 20 μs
24 3 Where is the exact specified location of an interrupt R1_P4_40
flag associated with analog-to-digital converter?
a. INTCON
b. ADCON0
c. ADRES
 d. PCLATH
A (b) ADCON0
Master Synchronous Serial Port (MSSP) module –
SPI mode
25 41 Which among the below stated salient feature/s of SPI R1_P3-1
contribute to the wide range of its applicability?
a. Simple hardware interfacing
b. Full duplex communication
c. Low power requirement
d. All of the above

A (d) All of the above

26 Q Which among the below stated conditions are R1_P5_6
selected by the SSPCON & SSPSTAT control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above
A (d) All of the above
27 Q Which bit of SSPCON must be necessarily set so as R1_P5_7
to enable the synchronization of serial port?
a. WCOL
b. SSPOV
c. CKP
d. SSPEN

A (d) SSPEN
28 Q What should be the value of SSPM3:SSPM0 bits so 2 R1_P5_8
that SPI can enter the slave mode by enabling SS pin
control?
a. 0000
b. 0100
c. 0010
d. 0001
A (b) 0100
29 Q How many upper bits of SSPSR are comparable to R1_P5_12
the address located in SSPADD especially after the
shifting of 8 bits into SSPSR under the execution of
START condition?
a. 7
b. 8
c. 16
d. 32
A (a)  7

Master Synchronous Serial Port (MSSP) module –I2C

mode.
30 37 Which bits assist in determining the I2C bit rate during
the initialization process of MSSP module in I2C
 mode?

a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above
A a. SSPADD 
31 38 Which command/s should be essentially written for I2C
input threshold selection and slew rate control
operations?

a. SSPSTAT 
b. SSPIF
c. ACKSTAT
d. All of the above
A a. SSPSTAT 
32 39 Where does the baud rate generation occur and
begins to count the bits required to get transmitted,
after an execution (set) of BF flag?

a. SCL line
b. SDA line
c. Both a & b
d. None of the above

A b. SDA line 
33 40 How many upper bits of SSPSR are comparable to
the address located in SSPADD especially after the
shifting of 8 bits into SSPSR under the execution of
START condition?

a. 7
b. 8
c.16
d.32

A a. 7
34 Q Which bits assist in determining the I2C bit rate during
the initialization process of MSSP module in I2C
mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above

A (a) SSPADD
35 Q Where does the baud rate generation occur and R1_P5_11
begins to count the bits required to get transmitted,
after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above
 A (b) SDA line
36 37 Which bits assist in determining the I2C bit rate during
the initialization process of MSSP module in I2C
mode?

a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above
A a. SSPADD 
37 38 Which command/s should be essentially written for I2C
input threshold selection and slew rate control
operations?

a. SSPSTAT 
b. SSPIF
c. ACKSTAT
d. All of the above
A a. SSPSTAT 
38 39 Where does the baud rate generation occur and
begins to count the bits required to get transmitted,
after an execution (set) of BF flag?

a. SCL line
b. SDA line
c. Both a & b
d. None of the above

A b. SDA line 
39 40 How many upper bits of SSPSR are comparable to
the address located in SSPADD especially after the
shifting of 8 bits into SSPSR under the execution of
START condition?

a. 7
b. 8
c.16
d.32

USART
34 Where should the value of TX9 bit be loaded during
the 9 bit transmission in an asynchronous mode?

a. TXSTA
 b. RCSTA
c. SPBRG
d. All of the above
A a. TXSTA
35 Why is the flag bit TXIF tested or examined in the
PIR1 register after shifting all the data bits during the
initialization process of USART in asynchronous
mode?

a. For ensuring the transmission of byte

b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity
A a. For ensuring the transmission of byte 
36 How is the baud rate specified for high-speed (BRGH
= 1) operation in an asynchronous mode ?

a. FOSC / 8 (X +1 ) 
b. FOSC / 16 (X +1 ) 
c. FOSC / 32 (X +1 ) 
d. FOSC / 64 (X +1 ) 
A b. FOSC / 16 (X +1 )