Final Exam (Summer 2021)
CSE 332/EEE 336: Computer Organization and Architecture
Instructor: Dr. Mainul Hossain (MHo1)
Department of Electrical and Computer Engineering
North South University
Total Marks = 50 Date:15/09/2021 Time = 1 hour 20 mins
ANSWER ALL QUESTIONS
Question 1 (ALU): 10 marks
(a) Convert: -1313.3125 to IEEE 32-bit floating point format. [5 marks]
(b) Divide 6 by 4 using the restoring division algorithm. [5 marks].
Show the workings using an appropriate table with columns for accumulator, dividend and divisor.
Question 2 (Control Unit): 10 marks
(a) For the direct addressing mode, write down the micro-operations needed to complete the instruction,
ADD BL, [2000]. Hint: There will be 6- T-states (T1, T2, T3, T4, T5 and T6). [5 marks]
(b) Compare state-table method and delay element method for hard wired controlled units in terms of
their benefits and drawbacks. [5 marks].
Question 3 (Cache Memory Mapping): 10 marks
(a) For the main memory address [Link], explain how a search is performed in set associative mapping.
Assume that the main memory size is 4 GB, the cache memory is 8 KB and the size of cache block is 32
bytes. [5 marks]
(b) The capacity of RAM is 16MB and size of block is 16Bytes. Capacity of cache is 8KB. Show the address
format in case of Direct Mapping [5 marks].
Question 4 (Memory Paging and ALU): 10 marks
(a) Define hit ratio. What do you understand by memory paging? [2+3 = 5 marks]
(b) Show the hardware implementation of signed binary multiplication using Booth's algorithm.
Discuss the algorithm using suitable flowchart [5 marks]
1
Question 5 (Computer Performance): 5×2 = 10 marks
You are on the design team for a new processor. The clock of the processor runs at 200 MHz. The following
table gives instruction frequencies for Benchmark program, as well as how many cycles the instructions
take, for the different classes of instructions. For this problem, we assume that (unlike many of today's
computers) the processor only executes one instruction at a time.
Instruction Type Frequency CPI
Loads & Stores 30% 6
Arithmetic Instructions 50% 4
All Others 20% 3
a) Calculate the CPI for Benchmark program.
b) What is the MIPS rating of the processor speed?
c) The hardware expert says that if you double the number of registers, the cycle time must be
increased by 20%. What would the new clock speed be (in MHz)?
d) The compiler expert says that if you double the number of registers, then the compiler will generate
code that requires only half the number of Loads & Stores. What would the new CPI be on the
benchmark?
e) How many CPU seconds will the benchmark take if we double the number of registers (taking
into account both changes described above)?
