MAULANA AZAD NATIONAL INSTITUTE OF TECHNOLOGY, BHOPAL

DEPARTMENT OF CSE
Mid Test, 05 Oct-2021

Course: B.Tech Semester: V Branch: CSE-I, II, III

Subject Name: Operating System Subject Code: CSE 312
Time: 09:30 AM – 11:00 AM (submit before 11:15 AM) Max. Marks: 40
Submission email ID: for CSE-1: oscse321manit2021@gmail.com
CSE-2 : oslabcse317@gmail.com
CSE-3: os2021cse3.btech@gmail.com

Note: i. Attempt all questions.

ii. Draw suitable diagram or take example for explanation.
iii. Reply and upload the answer sheet in single pdf file with filename as your scholar number, for example
(191112001.pdf)

S.No. Questions Marks

Q1 A free list contains three memory holes of sizes 6 KB, 15 KB and 12 KB. The next four 5
memory requests are for 10 KB, 2 KB, 5 KB, and 14 KB of memory. Demonstrate the
memory allocation and external fragmentation in case of ,
(i) Best-fit,
(ii) Worst-fit
Q2 Four processes requiring 63 KB, 70 KB, 150 KB, 100 KB, and 300 KB of memory. Paging 5
system with a page size of 4 KB is implemented. Calculate internal fragmentation for
all processes and identify the maximum internal fragmentation due to memory alloca-
tion to these four processes.
Q3 In a system the page fault service time is 10 microseconds and memory access time is 5
20 nanoseconds. If one page fault is generated for every 100 memory accesses, what
is the effective access time for the memory?
Q4 Consider the multi-programmed operating system for the following 3 processes; each 5
process has a CPU burst followed by I/O burst followed by another CPU burst.
Assuming that each process has its own I/O resource.
Process Arrival Time Burst time (CPU, I/O,
CPU)
P1 0 4, 5, 3
P2 2 3, 3, 5
P3 3 5, 3, 1
Assuming Round Robin with time quantum 2, Shortest Remaining Time First
(Preemptive) CPU scheduling. Calculate the following:
a) Average Turnaround time b) Average waiting time
c) CPU utilization d) I/O utilization e) Fraction of CPU idle time
Q5 In a system 3 page frames are used to store process pages in main memory. It uses the 5
Least Recently Used (LRU) page replacement policy. Assume that all the page frames
are initially empty. What is the total number of page faults that will occur while
processing the page reference string given below,
5, 4, 3, 2, 1, 2, 5, 1, 2, 3, 4, 5
Now, system use 4 page frames and page replacement policy remains same. Assume
that all the page frames are initially empty, calculate total number of page faults.
Q6 Consider a logical address space of process 8MB and page size of 8KB. Find the page 5
table entry size with a condition that page table will fit in one frame of main memory.

Q7 Consider a system with a two level paging scheme for virtual to physical address translation 10
in which page tables for both levels are stored in the main memory. Virtual and physical
addresses are both 32 bits wide and memory is byte addressable. Page size is 4KB and the
page table entries in both levels of page tables are 4 byte wide. The processor has a
Translation look-aside buffer (TLB), with a hit rate of 94%. The TLB caches recently used
virtual page numbers and the corresponding physical page numbers. The processor also has
a physically addressed cache with a hit rate of 92%. Main memory access time is 40 ns,
cache access time is 4 ns, and TLB access time is 2 ns. Calculate effective main memory
access time.

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