CSC 314 TUTORIAL SHEET

Reading and comprehensive

1. List the typical 5 levels of the memory hierarchy.

2. Choose the two main tradeoff in this hierarchy? (Price, Speed, Physical size, Weight,
Capacity, Power consumption)?
3. Name two considerations that are not part of this tradeoff.
4. Describe the differences between physical, virtual, and logical memory.
5. How are illegal page addresses recognized and trapped by the operating system?
6. How is a limit register used for protecting main memory?
7. How can you define an Operating System?
8. Name at least two generic purposes of an operating system.
9. What is the difference between a physical address and a virtual address?
10. Explain how a CPU supporting virtual memory would translate a virtual memory address into
the actual memory address, assuming that the requested page is in memory.
11. Explain the difference between internal and external fragmentation.

Question 1:
Suppose we were using a virtual memory system with three page frames, and our program accesses
the pages in the order 1–2–3–1–4–2–5–3. For each of the algorithms FIFO and LRU, identify the
contents of the three page frames after each memory access. Show details.

1. Explain the main purpose of an operating system?

2. What is kernel and his role?
3. How does dynamic loading aid in better memory space utilization?

Question 2
1. When you load an executable program into memory, it is laid out in a contiguous block of
memory with four parts. Illustrate this layout with a diagram and label each part, explain
their role.
2. Name the two advantages of using shared libraries for compiling programs.
3. Base-limit MMUs can support swapping. What is swapping? Can swapping permit an
application requiring 16M memory to run on a machine with 8M of RAM?
4. Explain the basic method for implementing paging.

Question 3
1. Assume a computer system employing a cache, where the access time to the main memory is
100 ns, and the access time to the cache is 20ns. Assume the cache hit rate is 95%. Hint:
Average Access Time (AAT) = Hit*cache_access_time + (1-Hit)*memory_access_time. What is
the average access time (AAT):
a. Without cache time access?
b. With cache time access?
2. Assume the system implements virtual memory using a two-level page table with no TLB
(Translation Lookaside Buffer), and assume the CPU loads a word X from main memory.
Assume the cache hit rate for the page entries as well as for the data in memory is 95%.
What is the average time it takes to load X without and with cache time access? Hint: The
Average Memory Access Time for X (AMAT_X) requires three memory accesses, two for each
page entry, and one for reading X.
 3. Assume the same setting as in point (2.) before, but now assume that page translation is
cached in the TLB (the TLB hit rate is 98%), and the access time to the TLB is 16 ns. What is
the average access time to X? - Hint: consider the cases with and without cache access time,
with and without TLB_hits. By definition, AAT_X is TLB_hit *(TLB_access_time + AAT) + (1-
TLB_hit) * (3 * AAT) and TLB_miss = TLB_hit *(TLB _time + AMAT) + (1-TLB_hit) * (3 * AMAT
+TLB_time).

Question 4:
1. When a program accesses a virtual memory address, each of the following could possibly
occur. For each, write “CPU” if it would be performed by the CPU while executing the
instruction, and write “OS” if it would be performed by the operating system's interrupt
handler for page faults.
a. Translating the virtual memory address to a DRAM address.
b. Marking a page as recently referenced.
c. For a page that isn't in DRAM, determining which existing page in DRAM should be
removed to make room for it.
d. Loading a page off of disk into DRAM.
e. Updating the page table to reflect that the loaded page is now in DRAM.
f. If the program's instruction is a store, marking its page table entry to reflect that the
page is dirty.
2. Describe at least two advantages of a virtual memory system over using the actual Dynamic
RAM addresses.
3. Explain how a hard disk stores and retrieves data (fixed size group of adjacent bits).

Question 5:
Suppose we have a system with a translation lookaside buffer (TLB) and a single level of cache for
regular data. The TLB miss rate is 1%, while the cache miss rate is 5%. Assume that these probabilities
are independent of one another. Accessing the TLB or cache takes one clock cycle, whereas accessing
DRAM takes 30 clock cycles.

1. Explain what a translation lookaside buffer (TLB) is. Where is it stored?

2. What will be the average time to access a memory value addressed using virtual
memory?
3. If there were no TLB at all, what would be the average time to access memory?

Question 6
Suppose we were using a virtual memory system with three page frames, and our program accesses
the pages in the order 1–2–3–1–4–2–5–4.

1. What are objectives of

a. Frame allocation algorithms?
b. Page replacement algorithms?
2. Using Least Recently Used (LRU) Algorithm with stack implementation,
a. Show the content of the three page frames at any stage of memory access.
b. What is the number of page fault?