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Keyence PLC Hardware Basic Operation
Keyence PLC Hardware Basic Operation
DIGITAL APPARATUS
PROGRAMMABLE
MEMORY
PLC DEFINED
LOGIC
SEQUENCING
TIMING
ARITHMETIC
MACHINE OR PROCESS
PLC DEFINED
troubleshooting
• Requires minimal panel space
• Safer Pilot Running
• Visualization
• Easily Documented
• Security
PLC TYPES
• maybe expandable
but only handles
limited I/O’s
PLC TYPES
MODULAR
PLC DEFINED
HYBRID
PLC DEFINED
PLC Sizes
POWER SUPPLY
INPUT OUTPUT
MODULE MODULE
CPU
PLC ARCHITECTURE
PROGRAMMING
DEVICE
HUMAN
MACHINE INTERFACE
SERIAL DEVICES
POWER SUPPLY
Discrete
Analog
High Speed Pulse
Register (BCD)
PLC ARCHITECTURE
DISCRETE INPUT
ELECTRO-MECHANICAL SWITCHES FIBER OPTIC
SENSORS LIMIT SWITCHES
ON or OFF
LIGHT
CURTAINS
ANALOG INPUT
RTD’s TACHOGENERATORS
THERMOCOUPLE
4-20 mA
1-5 Vdc
0-10 Vdc
-10 to +10 Vdc
PLC ARCHITECTURE PULSED INPUT
RELATIVE ROTARY
ENCODER
REGISTERS (BCD) INPUT
THUMBWHEEL
SWITCH
ABSOLUTE ROTARY
ENCODER
PLC ARCHITECTURE
ON or OFF
PLC ARCHITECTURE
LAMPS RELAY
COILS CONTACTOR
COILS
SOLENOID
VALVES
SSR
ANALOG OUTPUT
4-20 mA
1-5 Vdc
0-10 Vdc
-10 to +10 Vdc
PLC ARCHITECTURE
VARIABLE
VARIABLE
VALVE
VALVE POSITIONER
POSITIONER FREQUENCY PANEL METERS
FREQUENCY DRIVE
DRIVE
(ANALOG
(ANALOG INPUT)
INPUT)
PULSED OUTPUT
BCD
OUTPUT MODULE
TRANSISTORIZED OUTPUT
PLC ARCHITECTURE
OUTPUT MODULE
TRANSISTORIZED OUTPUT
PLC ARCHITECTURE
OUTPUT MODULE
TRANSISTORIZED OUTPUT
PLC ARCHITECTURE
OUTPUT MODULE
RELAY OUPUT
PLC ARCHITECTURE
OUTPUT MODULE
RELAY OUPUT
PLC ARCHITECTURE
Central Processing Unit
CPU contains:
• Microprocessor
RAM
KEYE
NCE
PLC ARCHITECTURE
FLA
S
KEH ROM
YEN
• Memory System
CE
• supporting circuitry
PLC ARCHITECTURE MICROPROCESSOR
SYSTEM
PLC ARCHITECTURE
APPLICATION
MEMORY User program and Data
Registers
MEMORY SYSTEM
DOUBLE
MICROPROCESSOR
LAYER
CAPACITOR
INPUT REGISTERS
OUTPUT REGISTERS
TIMER/COUNTER VALUES
DATA MEMORY
FORCED VALUES
USER PROGRAM
MEMORY SYSTEM
MICROPROCESSOR
RAM
PLC ARCHITECTURE
DATA
INPUT REGISTERS
WRITTEN
OUTPUT REGISTERS
IN RAM
TIMER/COUNTER VALUES
DATA MEMORY
FORCED VALUES
USER PROGRAM
MEMORY SYSTEM
MICROPROCESSOR
DOUBLE MICROPROCESSOR
LAYER
CAPACITOR
VOLATILE
RAM
PLC ARCHITECTURE
INPUT REGISTERS
At power
interruptions,
OUTPUT REGISTERS
capacitor holds
TIMER/COUNTER VALUES the data at
DATA MEMORY RAM for 120
FORCED VALUES days at 25OC
operating
USER PROGRAM temp.
MEMORY SYSTEM
MICROPROCESSOR
DOUBLE MICROPROCESSOR
LAYER
CAPACITOR
At save command,
data is copied to
the flash ROM
MEMORY SYSTEM
MICROPROCESSOR
DOUBLE MICROPROCESSOR
LAYER
CAPACITOR
015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INPUT REGISTER
INPUT SCAN
015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INPUT REGISTER
INPUT SCAN
015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INPUT REGISTER
INPUT SCAN
015 014 013 012 011 010 009 008 007 006 005 004 003 002 001 000
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300
1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INPUT REGISTER
OUTPUT PROCESSING
515 014 513 012 511 510 509 508 507 506 505 504 503 502 501 500
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
615 614 613 612 611 610 609 608 607 606 605 604 603 602 601 600
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
715 714 713 712 711 710 709 708 707 706 705 704 703 702 701 700
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
815 814 813 812 811 810 809 808 807 806 805 804 803 802 801 800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
915 914 913 912 911 910 909 908 907 906 905 404 903 902 901 900
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT REGISTER
PS
OUTPUT PROCESSING
515 014 513 012 511 510 509 508 507 506 505 504 503 502 501 500
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
605 604 603 602 601 600 609 608 607 606 605 604 603 602 601 600
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
715 714 713 712 711 710 709 708 707 706 705 704 703 702 701 700
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
805 804 803 802 801 800 809 808 807 806 805 804 803 802 801 800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
915 914 913 912 911 910 909 908 907 906 905 404 903 902 901 900
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT REGISTER
PS
OUTPUT PROCESSING
515 014 513 012 511 510 509 508 507 506 505 504 503 502 501 500
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
605 604 603 602 601 600 609 608 607 606 605 604 603 602 601 600
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
715 714 713 712 711 710 709 708 707 706 705 704 703 702 701 700
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
805 804 803 802 801 800 809 808 807 806 805 804 803 802 801 800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
915 914 913 912 911 910 909 908 907 906 905 404 903 902 901 900
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT REGISTER
PS
OUTPUT PROCESSING
515 014 513 012 511 510 509 508 507 506 505 504 503 502 501 500
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
605 604 603 602 601 600 609 608 607 606 605 604 603 602 601 600
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
715 714 713 712 711 710 709 708 707 706 705 704 703 702 701 700
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
805 804 803 802 801 800 809 808 807 806 805 804 803 802 801 800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
915 914 913 912 911 910 909 908 907 906 905 404 903 902 901 900
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PLC ARCHITECTURE
OUTPUT REGISTER
PS
OUTPUT PROCESSING
515 014 513 012 511 510 509 508 507 506 505 504 503 502 501 500
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
605 604 603 602 601 600 609 608 607 606 605 604 603 602 601 600
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
715 714 713 712 711 710 709 708 707 706 705 704 703 702 701 700
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
805 804 803 802 801 800 809 808 807 806 805 804 803 802 801 800
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
915 914 913 912 911 910 909 908 907 906 905 404 903 902 901 900
PLC ARCHITECTURE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OUTPUT REGISTER
PS
PLC OPERATION
PLC OPERATION
START
Housekeeping Input Scan
Internal checks on The status of
memory, speed RE external inputs
A D
and operation.
I FY (terminal block
Service any
E R voltage) is
communication V written to the
requests, etc. Input Table
PLC OPERATION
SCAN CYCLE
E
UT
W
EC
RI
EX
TE
Program Scan
Output Scan
Each ladder rung is scanned
The Output Table data is using the data in the Input file.
transferred to the external The resulting status (Logic
output circuits, turning the being solved) is written to the
output devices ON or OFF. Output file (“Output Image”).
PLC OPERATION
PROGRAM DOWNLOAD
Microprocessor
Power
Supply AC
PLC OPERATION
READ INPUT
STATUS RUN MODE
MicroProcessor
Power
Supply AC
PLC OPERATION
EXECUTE RUN MODE
PROGRAM
MicroProcessor
Power
Supply AC
PLC OPERATION
WRITE
OUTPUT RUN MODE
MicroProcessor
Power
Supply AC
PLC OPERATION
RUN MODE
MicroProcessor
Power
Supply AC
PLC OPERATION
RUN MODE
MicroProcessor
Power
Supply AC
PLC OPERATION
RUN MODE
USER PROGRAM
000 001 002 500 OUTPUT REGISTER
005 004 003 002 001 000 503 502 501 500
0 0 0 1 1 1 0 0 0 0
1
PLC OPERATION
MicroProcessor
Power
Supply AC
ERROR: stackunderflow
OFFENDING COMMAND: ~
STACK: