Analog Switch

BRD8007/D
Rev. 0, Apr-2000
ON Semiconductor
Analog Switches
ON Semiconductor
Analog Switches
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC
products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of
the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment: CENTRAL/SOUTH AMERICA:
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Email: ONlit-french@hibbertco.com
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EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 For additional information, please contact your local Sales
*Available from Germany, France, Italy, England, Ireland Representative
04/00
BRD8007/D BRD-
8007
REV 0
Analog Switches
BRD8007/D
Rev. 0, Apr–2000
 SCILLC, 2000
“All Rights Reserved”
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Center for ON Semiconductor Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
P.O. Box 5163, Denver, Colorado 80217 USA Email: ONlit–spanish@hibbertco.com
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Email: ONlit@hibbertco.com Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada Toll Free from Hong Kong & Singapore:
001–800–4422–3781
N. American Technical Support: 800–282–9855 Toll Free USA/Canada Email: ONlit–asia@hibbertco.com
EUROPE: LDC for ON Semiconductor – European Support JAPAN: ON Semiconductor, Japan Customer Focus Center
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time) 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549
Email: ONlit–german@hibbertco.com Phone: 81–3–5740–2745
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time) Email: r14525@onsemi.com
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 For additional information, please contact your local
*Available from Germany, France, Italy, England, Ireland Sales Representative.
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2
Table of Contents
Page
Introduction to Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MC14016B Quad SPST Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MC14051B 8–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MC14052B Dual, 4–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MC14053B Triple, 2–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MC14066B Quad Analog Switch / Quad Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MC14067B 16 Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MC14551B Quad 2–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
MC74HC4051A 8–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
MC74HC4052A Dual, 4–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
MC74HC4053A Triple, 2–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
MC74HC4066A Quad SPST Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
MC74HC4316A Quad SPST Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
MC74HC4851A 8–Channel Multiplexer / Demultiplexer with Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC74HC4852A Dual, 4–Channel Multiplexer / Demultiplexer with Charge Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MC74VHC4051 8–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MC74VHC4052 Dual, 4–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MC74VHC4053 Triple, 2–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
MC74VHC1G66 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MC74VHC1GT66 Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
MC74LVX4051 8–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MC74LVX4052 Dual, 4–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
MC74LVX4053 Triple, 2–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
MC74LVX4066 Quad Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
MC74LVXT4066 Quad Multiplexer, TTL Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MC74LVX8051 8–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MC74LVXT8051 8–Channel Multiplexer / Demultiplexer, TTL Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
MC74LVX8053 Triple, 2–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
MC74LVXT8053 Triple, 2–Channel Multiplexer / Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Package Specifications and Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Tape & Reel Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Sales Office List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Document Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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Mosorb and ON–Demand are trademarks of Semiconductor Components Industries, LLC (SCILLC).
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Analog Switches
Analog switches have been offered by ON Semiconductor devices from 2.0 to 6.0 volts for the standard CMOS parts
(formerly SCG of Motorola) as part of the Logic operations and 5.0 volts for the TTL–compatible versions. Typical
product offering for over 20 years. They continue to be part resistance values are less than 15 Ω for many of the devices
of the standard logic family portfolios for Metal Gate, when operating at 5.0 volts. The multi–gate, standard family
High–Speed, Very High–Speed, LVX, and most recently, products are available in both SOIC and TSSOP 16–lead
VHC One–Gate. packages, while the One–Gate devices are available in the
These analog switches, come in a variety of functions and industry standard SC–88A/SC–70 5 lead, SOT–353
have played a very important role in providing system packages.
design support in many market segments. Functions ranging
from data selectors and SPST switches, to multiple–channel New Analog Switch Data Book
multiplexer/demultiplexers continue to gain popularity. The purpose of providing this new Analog Switch Data
They perform unique and important functions in Book is to capture the entire portfolio offering of analog
applications such as audio or video signal switching, A/D switches from the ON Semiconductor Logic Division in a
converter multiplexing, or RF signal switching. In addition, single publication and to provide a vehicle for promoting
analog switches are frequently used as relays (minimal additional planned introductions. It is our intent to provide
signal delays), or simply to provide bilateral isolation easy access to information regarding all of ON
between circuits. Semiconductor’s analog switch products.
System designers also use analog switches to address Many Diverse Applications: Analog switches can be
signal routing issues or to allow for “hot swapping” used in many ways to accomplish switching,
capability of individual devices and system boards. multiplexing/de–multiplexing of both analog and digital
signals. Many so–called digital signals are actually
New Analog Switch Products quasi–analog in nature, such as FSK (frequency shift key),
Throughout the industry, popular analog switch functions PSK (phase–shift key), QAM (Quadrature Amplitude
are offered in practically all of the standard logic families, Modulation), CDMA (Code Division Multiplex, and
to take advantage of technology improvements and to TDMA (Time Division Multiplexing). They need to share
facilitate interfacing analog switch functions to changes in the decoding from several different input sources, while
system design. ON Semiconductor continues to include inserting minimum signal distortion. When switching
them as part of logic family portfolios, and very recently signals between 2 or more items in consumer product
added the first two One–Gate analog switches. Plans are in applications, analog switches play a key role.
place to add additional functions to this and the other ON Semiconductor recently introduced two additional
low–voltage families offered by ON Semiconductor. devices in the advanced high–speed, sub–micron VHC
Eleven, recently introduced devices–MC74LVX4066, One–Gate, CMOS family. The MC74VHC1G66 and
8051, 8053 and their TTL compatible versions MC74VHC1GT66 devices offer a single analog switch
(MC74LVXT4066, 8051, 8053), three new VHC products– function with impressive AC performance levels.
MC74VHC4051, 4052, 4053, and two new One–Gate
devices–MC74VHC1G66/1GT66, round out the current Analog Switch Applications:
ON Semiconductor offering. These new devices Application 1: Change a time constant in a loop filter
compliment the standard offering of analog switch application, for fast “attack” stable “hold”
multiplexer/de–multiplexers. They are single supply
CTRL
C2
1G66
f ref
C1
t1 = RC1
F R t2 = R(C1 + C2)
DC Ctrl for VCO Loop Impedance Remains
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5
Application 2: The three new VHC devices, a 5 volt peak–to–peak waveform, with LVTTL/CMOS
MC74VHC4051, MC74VHC4052, MC74VHC4053 compatibility. The d.c. level is preserved, for the case of
provide improved performance and allow operation with video switching. The VHC4053 is useful for switching
both positive and negative supplies. This feature allows for beyond 30 MHz. The following diagram illustrates
switching an AC waveform that is centered around zero switching two audio channels from 2 sources and 2 video
volts with no coupling capacitors. With a +/– 3.3 volt supply, channels simultaneously. The signal levels may be +/– 2.5
video signals can be switched, while preserving the dc volts.
component of its signal. The +/– 3.3 volt supply allows for
±2.5 Volts +3.3 Volts ±2.5 Volts
A, B VHC
4053
Stereo Audio C, D
E, F
Video
DC DC
VEE, –3.3 Volts

CTRL
Application 3: Select between one of eight sources to decode up to 8 inputs to be connected to a single (expensive)
for a Dolby Digital or DTS Decoder. A stereo receiver will decoder. The de–multiplexer is low cost, and adds minimum
likely have a single audio decoder, but will need to switch loss and distortion to the circuit. The frequency that it needs
between several possible inputs– optical and coaxial. The to handle is in the 10 MHz range.
MC74LVX8051 will allow the designer to switch between
VCC, 5.0 Volts
Optical Input
LVXT Dolby–Digital/DTS
Coaxial Input
8051 Decoder
Inputs 3–8
TTL–Level Control
Control
Note: DTS and Dolby Digital are trademarks of their respective companies
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Data Sheets
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MC14016B
Quad Analog Switch/

Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS

P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The http://onsemi.com
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation. MARKING
• Diode Protection on All Inputs DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc 14
PDIP–14
• Linearized Transfer Characteristics P SUFFIX MC14016BCP
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical CASE 646 AWLYYWW
• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved 1

transfer characteristic design causes more parasitic coupling 14
capacitance than CD4016) SOIC–14
• For Lower RON, Use The HC4016 High–Speed CMOS Device or D SUFFIX
14016B
AWLYWW
The MC14066B CASE 751A
• This Device Has Inputs and Outputs Which Do Not Have ESD 1
Protection. Antistatic Precautions Must Be Taken. 14

SOEIAJ–14
F SUFFIX MC14016B
CASE 965 AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
1
Symbol Parameter Value Unit
A = Assembly Location
VDD DC Supply Voltage Range – 0.5 to +18.0 V WL or L = Wafer Lot
YY or Y = Year
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V
WW or W = Work Week
(DC or Transient)
Iin Input Current (DC or Transient) ± 10 mA
per Control Pin
ORDERING INFORMATION
ISW Switch Through Current ± 25 mA
Device Package Shipping
PD Power Dissipation, 500 mW
per Package (Note 3.) MC14016BCP PDIP–14 2000/Box
TA Ambient Temperature Range – 55 to +125 °C MC14016BD SOIC–14 55/Rail
Tstg Storage Temperature Range – 65 to +150 °C
MC14016BDR2 SOIC–14 2500/Tape & Reel
TL Lead Temperature 260 °C
(8–Second Soldering) MC14016BF SOEIAJ–14 See Note 1.
2. Maximum Ratings are those values beyond which damage to the device MC14016BFEL SOEIAJ–14 See Note 1.
may occur.
3. Temperature Derating: MC14016BFR1 SOEIAJ–14 See Note 1.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
1. For ordering information on the EIAJ version of
This device contains protection circuitry to guard against damage due to high the SOIC packages, please contact your local
static voltages or electric fields. However, precautions must be taken to avoid ON Semiconductor representative.
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
 Semiconductor Components Industries, LLC, 2000 8 Publication Order Number:

March, 2000 – Rev. 3 MC14016B/D
MC14016B
PIN ASSIGNMENT
IN 1 1 14 VDD
OUT 1 2 13 CONTROL 1
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3
BLOCK DIAGRAM
13
CONTROL 1 2
1 OUT 1
IN 1
5
CONTROL 2 3
4 OUT 2
IN 2
6
CONTROL 3 9
OUT 3
8
IN 3
12
CONTROL 4 10
OUT 4
11
IN 4
VDD = PIN 14
VSS = PIN 7
Control Switch
0 = VSS Off
1 = VDD On
LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT
CONTROL
LOGIC DIAGRAM RESTRICTIONS IN

VSS ≤ Vin ≤ VDD
VSS ≤ Vout ≤ VDD
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MC14016B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Î ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ VDD
– 55_C 25_C 125_C
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Figure Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage 1 VIL 5.0 — — — 1.5 0.9 — — Vdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Control Input 10 — — — 1.5 0.9 — —
15 — — — 1.5 0.9 — —
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH 5.0 — — 3.0 2.0 — — — Vdc
ÎÎ ÎÎ
10 — — 8.0 6.0 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — 13 11 — — —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Control — Iin 15 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Input Capacitance — Cin pF
Control — — — — 5.0 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Switch Input — — — — 5.0 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Switch Output — — — — 5.0 — — —
Feed Through — — — — 0.2 — — —
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Per Package) (5.) ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
2,3 IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
“ON” Resistance 4,5,6 RON — — Ohms
(VC = VDD, RL = 10 kΩ) — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = + 5.0 Vdc) — 600 — 300 660 — 840
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = – 5.0 Vdc) VSS = – 5.0 Vdc — 600 — 300 660 — 840
(Vin = ± 0.25 Vdc) 5.0 — 600 — 280 660 — 840
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Vin = + 7.5 Vdc)
ÎÎÎ ÎÎ
ÎÎÎ
(Vin = ± 0.25 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5 Vdc) VSS = – 7.5 Vdc
7.5
—
—
—
360
360
360
—
—
—
240
240
180
400
400
400
—
—
—
520
520
520
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Vin = + 10 Vdc)
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— 600 — 260 660 — 840
ÎÎ ÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc — 600 — 310 660 — 840
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 5.6 Vdc) 10 — 600 — 310 660 — 840
(Vin = + 15 Vdc) — 360 — 260 400 — 520
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc
ÎÎÎ
ÎÎÎ
— 360 — 260 400 — 520
ÎÎ ÎÎ
(Vin = + 9.3 Vdc) 15 — 360 — 300 400 — 520
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
∆ “ON” Resistance — ∆RON Ohms
Between any 2 circuits in a common
ÎÎÎ
package
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ ÎÎ
(VC = VDD)
(Vin = ± 5.0 Vdc, VSS = – 5.0 Vdc) 5.0 — — — 15 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = ± 7.5 Vdc, VSS = – 7.5 Vdc) 7.5 — — — 10 — — —
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input/Output Leakage Current
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— — µAdc
ÎÎ ÎÎ
(VC = VSS)
(Vin = + 7.5, Vout = – 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5, Vout = + 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. For voltage drops across the switch (∆V switch) > 600 mV ( > 300 mV at high temperature), excessive V DD current may be drawn; i.e., the
current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.
http://onsemi.com
10
MC14016B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
VDD
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Characteristic Figure Symbol Vdc Min Typ (7.) Max Unit
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Propagation Delay Time (VSS = 0 Vdc) 7 tPLH, 5.0 — 15 45 ns
Vin to Vout tPHL 10 — 7.0 15
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VDD, RL = 10 kΩ) 15 — 6.0 12
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Control to Output 8 tPHZ, ns
v
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Vin 10 Vdc, RL = 10 kΩ) tPLZ, 5.0 — 34 90
tPZH, 10 — 20 45
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
tPZL 15 — 15 35
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Crosstalk, Control to Output (VSS = 0 Vdc) 9 — 5.0 — 30 — mV
(VC = VDD, Rin = 10 kΩ, Rout = 10 kΩ, 10 — 50 —
ÎÎÎ
f = 1.0 kHz)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Crosstalk between any two switches (VSS = 0 Vdc) — —
15
5.0
—
—
100
– 80
—
— dB
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 1.0 kΩ, f = 1.0 MHz,
+ V
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
crosstalk 20 log10 out1)
Vout2
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Noise Voltage (VSS = 0 Vdc)
ÎÎÎÎ
(VC = VDD, f = 100 Hz)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
10,11 — 5.0
10
15
—
—
—
24
25
30
—
—
—
nV/√Cycle
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(VC = VDD, f = 100 kHz)
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
5.0
10
—
—
12
12
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
15 — 15 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion (VSS = – 5.0 Vdc) — — 5.0 — 0.16 — %
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
RL = 10 kΩ, f = 1.0 kHz)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Insertion Loss (VC = VDD, Vin = 1.77 Vdc, 12 — 5.0 dB
VSS = – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)
+Iloss
ÎÎÎ
(RL = 1.0 kΩ)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
V
ÎÎÎÎ ÎÎÎÎ
20 log10 out)
ÎÎÎ
ÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
—
—
2.3
0.2
—
—
ÎÎÎ
(RL = 10 kΩ)
ÎÎÎ
(RL = 100 kΩ)
(RL = 1.0 MΩ)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
—
—
0.1
0.05
—
—
ÎÎÎ
ÎÎÎ ÎÎÎÎ
Bandwidth (– 3.0 dB)
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VDD, Vin = 1.77 Vdc, VSS = – 5.0 Vdc,
12,13 BW 5.0 MHz
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
RMS centered @ 0.0 Vdc)
(RL = 1.0 kΩ) — 54 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 10 kΩ) — 40 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 100 kΩ) — 38 —
(RL = 1.0 MΩ) — 37 —
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VSS = – 5.0 Vdc)
+
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vout
ÎÎÎÎ
OFF Channel Feedthrough Attenuation
ÎÎÎ
ÎÎÎÎ
— — 5.0 kHz
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VSS, 20 log10 –50 dB)
Vin — 1250 —
(RL = 1.0 kΩ)
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
— 140 —
(RL = 10 kΩ)
— 18 —
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 100 kΩ)
— 2.0 —
(RL = 1.0 MΩ)
6. The formulas given are for typical characteristics only at 25_C.
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11
MC14016B
VC IS
Vin Vout
VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = ±10 µA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
10,000
VDD = 15 Vdc 10 Vdc
PD , POWER DISSIPATION (µW)

VDD TA = 25°C
5.0 Vdc
1000
ID
100
VDD Vout
TO ALL
10 k 10
PULSE 4 CIRCUITS CONTROL
GENERATOR INPUT
fc
VSS Vin 1.0

PD = VDD x ID 5.0 k 10 k 100 k 1.0 M 10 M 50 M
fc, FREQUENCY (Hz)
Figure 2. Quiescent Power Dissipation Figure 3. Typical Power Dissipation per Circuit
Test Circuit (1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE
700 700
RL = 10 kΩ VSS = 0 Vdc
600 TA = 25°C 600 RL = 10 kΩ
R ON, “ON” RESISTANCE (OHMS)
R ON, “ON” RESISTANCE (OHMS)
TA = 25°C
500 500
400 VC = VDD = 5.0 Vdc 400

VSS = – 5.0 Vdc VC = VDD = 10 Vdc
300 300
200 200 VC = VDD = 15 Vdc

VC = VDD = 7.5 Vdc
100 VSS = – 7.5 Vdc 100
0 0
– 10 – 8.0 – 4.0 0 4.0 8.0 10 0 2.0 6.0 10 14 18 20
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)
Figure 4. VSS = – 5.0 V and – 7.5 V Figure 5. VSS = 0 V
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12
MC14016B
Vout
RL CL
Vin
Vout 20 ns 20 ns
RL VDD
Vin 90%
VC 50% 10%
VSS
tPLH tPHL
Vout 50%
Vin
Figure 6. RON Characteristics Figure 7. Propagation Delay Test Circuit

Test Circuit and Waveforms
Vout
VC RL CL
Vin VX
20 ns
VDD Vout
90%
VC 50%
10% VC 10 k 15 pF
VSS
tPZH tPHZ
Vin = VDD
90% Vx = VSS
Vout 10% Vin
tPZL tPLZ
90% 1k
Vout Vin = VSS
10%
Vx = VDD
Figure 8. Turn–On Delay Time Test Circuit Figure 9. Crosstalk Test Circuit
and Waveforms
35
30
VDD = 15 Vdc
NOISE VOLTAGE (nV/ CYCLE)
25
10 Vdc
20
5.0 Vdc
15
OUT QUAN–TECH 10
MODEL
VC = VDD
2283
5.0
IN OR EQUIV
0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)
Figure 10. Noise Voltage Test Circuit Figure 11. Typical Noise Characteristics
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13
MC14016B
2.0
RL = 1 MΩ AND 100 kΩ
0
TYPICAL INSERTION LOSS (dB)
10 kΩ
– 2.0
1.0 kΩ
– 4.0 – 3.0 dB (RL = 1.0 MΩ )
Vout
– 6.0 – 3.0 dB (RL = 10 kΩ ) RL
VC
– 3.0 dB (RL = 1.0 kΩ )
– 8.0
– 10 + 2.5 Vdc
Vin 0.0 Vdc
– 12 – 2.5 Vdc
10 k 100 k 1.0 M 10 M 100 M
fin, INPUT FREQUENCY (Hz)
Figure 12. Typical Insertion Loss/Bandwidth Figure 13. Frequency Response Test Circuit
Characteristics
ON SWITCH
CONTROL
SECTION
OF IC
LOAD
V
SOURCE
Figure 14. ∆V Across Switch
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14
MC14016B
APPLICATIONS INFORMATION
Figure A illustrates use of the Analog Switch. The 0–to–5 The example shows a 5 V p–p signal which allows no
V Digital Control signal is used to directly control a 5 V p–p margin at either peak. If voltage transients above V DD
analog signal. and/or below VSS are anticipated on the analog channels,
The digital control logic levels are determined by V DD external diodes (Dx) are recommended as shown in Figure
and V SS. The V DD voltage is the logic high voltage; the V SS B. These diodes should be small signal types able to absorb
voltage is logic low. For the example, V DD = + 5 V logic high the maximum anticipated current surges during clipping.
at the control inputs; V SS = GND = 0 V logic low. The absolute maximum potential difference between
The maximum analog signal level is determined by VDD V DD and VSS is 18.0 V. Most parameters are specified up to
and V SS. The analog voltage must not swing higher than 15 V which is the recommended maximum difference
V DD or lower than V SS. between V DD and V SS.
+5 V
VDD VSS
+ 5.0 V
+5 V 5 Vp–p SWITCH
ANALOG SIGNAL IN
SWITCH 5 Vp–p
+ 2.5 V
OUT ANALOG SIGNAL
EXTERNAL
CMOS 0–TO–5 V DIGITAL
GND
DIGITAL CONTROL SIGNALS MC14016B
CIRCUITRY
Figure A. Application Example
VDD VDD
Dx Dx
SWITCH SWITCH
IN OUT
Dx Dx
VSS VSS
Figure B. External Germanium or Schottky Clipping Diodes
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15
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally–controlled analog switches. The MC14051B effectively http://onsemi.com
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
MARKING
impedance and very low OFF leakage current. Control of analog
DIAGRAMS
signals up to the complete supply voltage range can be achieved.
16
• Triple Diode Protection on Control Inputs PDIP–16
• Switch Function is Break Before Make P SUFFIX MC140XXBCP
AWLYYWW
•
CASE 648
Supply Voltage Range = 3.0 Vdc to 18 Vdc
1
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be VSS v 16
• Linearized Transfer Characteristics SOIC–16
140XXB
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical D SUFFIX AWLYWW
CASE 751B
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053 1
• For 4PDT Switch, See MC14551B
• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed 16
CMOS Devices TSSOP–16 14
DT SUFFIX 0XXB
MAXIMUM RATINGS (Note 1.) CASE 948F ALYW
1
VDD DC Supply Voltage (Referenced – 0.5 to +18.0 V
to VEE, VSS ≥ VEE) 16
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V SOEIAJ–16
(DC or Transient) (Referen– F SUFFIX MC140XXB
ced to VSS for Control Inputs CASE 966 AWLYWW
and VEE for Switch I/O)
1
Iin Input Current (DC or Transient) ± 10 mA
per Control Pin
ISW Switch Through Current ± 25 mA XX = Specific Device Code
PD Power Dissipation, 500 mW WL or L = Wafer Lot
per Package (Note 2.) YY or Y = Year
WW or W = Work Week
TA Ambient Temperature Range – 55 to +125 °C
TL Lead Temperature 260 °C
(8–Second Soldering) ORDERING INFORMATION
1. Maximum Ratings are those values beyond which damage to the device See detailed ordering and shipping information in the package
may occur. dimensions section on page 24 of this data sheet.
2. Temperature Derating:
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
VDD.
either VSS, VEE or VDD). Unused outputs must be left open.

March, 2000 – Rev. 3 MC14051B/D
MC14051B, MC14052B, MC14053B
MC14051B MC14052B MC14053B

8–Channel Analog Dual 4–Channel Analog Triple 2–Channel Analog
Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer
6 INHIBIT 6 INHIBIT 6 INHIBIT

11 A CONTROLS 10 A 11 A X 14
CONTROLS X 13 CONTROLS
10 B 9 B 10 B
9 C 12 X0 9 C
13 X0 14 X1 12 X0 Y 15 COMMONS
COMMONS
14 X1 15 X2 13 X1 OUT/IN
X 3 OUT/IN
15 X2 SWITCHES 11 X3 SWITCHES 2 Y0
COMMON
SWITCHES 12 X3 IN/OUT 1 Y0 IN/OUT 1 Y1
OUT/IN Y 3 Z 4
IN/OUT 1 X4 5 Y1 5 Z0
5 X5 2 Y2 3 Z1
2 X6 4 Y3
4 X7
VDD = PIN 16 VDD = PIN 16 VDD = PIN 16

VSS = PIN 8 VSS = PIN 8 VSS = PIN 8
VEE = PIN 7 VEE = PIN 7 VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.
PIN ASSIGMENT
MC14051B MC14052B MC14053B
X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD
X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y
X 3 14 X1 Y 3 14 X1 Z1 3 14 X
X7 4 13 X0 Y3 4 13 X Z 4 13 X1
X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0
INH 6 11 A INH 6 11 X3 INH 6 11 A
VEE 7 10 B VEE 7 10 A VEE 7 10 B
VSS 8 9 C VSS 8 9 B VSS 8 9 C
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17
MC14051B, MC14052B, MC14053B
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
– 55_C 25_C 125_C
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Characteristic Symbol VDD Test Conditions Min Max Min Typ (3.) Max Min Max Unit
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎ
Power Supply VoltageÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VDDÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
ÎÎ
— VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18 3.0 18 V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Range
µA
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: — 5.0 — 0.005 5.0 — 150
Package 10 Vin = VSS or VDD, — 10 — 0.010 10 — 300
v
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 Switch I/O: VEE VI/O — 20 — 0.015 20 — 600
v VDD, and ∆Vswitch
ÎÎÎÎÎÎÎÎ
ÎÎ v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ 500 mV (4.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ
ID(AV)
5.0 TA = 25_C only (The
(0.07 µA/kHz) f + IDD
µA
ÎÎ ÎÎ
(Dynamic Plus 10 channel component,
Typical (0.20 µA/kHz) f + IDD
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Quiescent, Per Package 15 (Vin – Vout)/Ron, is
not included.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
Low–Level Input Voltage
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
ÎÎÎ
VIL
ÎÎÎÎÎ
5.0
10
15
Ron = per spec,
Ioff = per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
High–Level Input Voltage
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
10
15
Ioff = per spec 7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — 1.0 µA
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Recommended VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD VPP
Peak–to–Peak Voltage
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Into or Out of the Switch
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Recommended Static or ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Dynamic Voltage Across
the Switch (4.) (Figure 5)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Output Offset Voltage
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VOO
ÎÎ — Vin = 0 V, No Load — — — 10 — — — µV
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ON Resistance v
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Ron 5.0 ∆Vswitch 500 mV (4.) — 800 — 250 1050 — 1200 Ω
ÎÎ ÎÎ ÎÎ
10 Vin = VIL or VIH — 400 — 120 500 — 520
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 (Control), and Vin = — 220 — 80 280 — 300
0 to VDD (Switch)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
∆ON Resistance Between
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
∆Ron 5.0 — 70 — 25 70 — 135 Ω
ÎÎ ÎÎ ÎÎ
Any Two Channels in the 10 — 50 — 10 50 — 95
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Same Package 15 — 45 — 10 45 — 65
± 100 ± 0.05 ± 100 ± 1000
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — — — nA
Current (Figure 10) (Control) Channel to
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Channel or Any One
Channel
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Capacitance, Switch I/O
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
CI/O — Inhibit = VDD — — — 10 — — — pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Capacitance, Common O/I
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
CO/I
ÎÎÎ
ÎÎÎ
— Inhibit = VDD pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
(MC14051B)
(MC14052B)
(MC14053B)
—
—
—
—
—
—
—
—
—
60
32
17
—
—
—
—
—
—
—
—
—
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
Capacitance, Feedthrough
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
CI/O
ÎÎÎ
ÎÎÎ
— Pins Not Adjacent — — — 0.15 — — — pF
ÎÎ
(Channel Off)
ÎÎ ÎÎ — Pins Adjacent — — — 0.47 — —
3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
—
4. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
http://onsemi.com
18
MC14051B, MC14052B, MC14053B
ÎÎÎÎÎv
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (5.) (CL = 50 pF, TA = 25_C) (VEE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VSS unless otherwise indicated)
VDD – VEE Typ (6.)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc All Types Max Unit
Propagation Delay Times (Figure 6) tPLH, tPHL ns
MC14051
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Switch Input to Switch Output (RL = 10 kΩ)
ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 35 90
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns 10 15 40
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 12 30
MC14052 ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns
ÎÎÎ
5.0
10
15
30
12
10
75
30
25
ÎÎÎÎÎ
MC14053
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns 5.0 25 65
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns 10 8.0 20
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns 15 6.0 15
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Inhibit to Output (RL = 10 kΩ, VEE = VSS)
ÎÎÎÎÎ
ÎÎÎ
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
tPHZ, tPLZ,
tPZH, tPZL
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MC14051B 5.0 350 700
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10 170 340
15 140 280
ÎÎÎÎÎ
MC14052B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
15
300
155
125
600
310
250
ns
ÎÎÎÎÎ
MC14053B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
275
140
550
280
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 110 220
Control Input to Output (RL = 10 kΩ, VEE = VSS) tPLH, tPHL ns
MC14051B
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
15
360
160
120
720
320
240
ÎÎÎÎÎ
MC14052B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
5.0
10
325
130
650
260
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
15 90 180
MC14053B 5.0 300 600 ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
10
15
120
80
240
160
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Second Harmonic Distortion — 10 0.07 — %
(RL = 10KΩ, f = 1 kHz) Vin = 5 VPP
ÎÎÎÎÎ
Bandwidth (Figure 7)
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF
20 Log (Vout/Vin) = – 3 dB)
BW 10 17 — MHz
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
Off Channel Feedthrough Attenuation (Figure 7)
ÎÎÎÎÎ
ÎÎÎ
RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p
fin = 4.5 MHz — MC14051B
— 10 – 50 — dB
ÎÎÎÎÎ
fin = 30 MHz — MC14052B
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
fin = 55 MHz — MC14053B
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Channel Separation (Figure 8) — 10 – 50 — dB
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
fin = 3.0 MHz
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Crosstalk, Control Input to Common O/I (Figure 9) — 10 75 — mV
(R1 = 1 kΩ, RL = 10 kΩ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
http://onsemi.com
19
MC14051B, MC14052B, MC14053B
VDD VDD V
DD
IN/OUT OUT/IN
VEE
VDD
LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL
CONTROL
VEE
Figure 1. Switch Circuit Schematic
TRUTH TABLE 16 VDD

Control Inputs
INH 6 BINARY TO 1–OF–8
Select ON Switches A 11 LEVEL
DECODER WITH
Inhibit C* B A MC14051B MC14052B MC14053B B 10 CONVERTER
C 9 INHIBIT
0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 0 1 X1 Y1 X1 Z0 Y0 X1 8 VSS 7 VEE
0 0 1 0 X2 Y2 X2 Z0 Y1 X0 X0 13
0 0 1 1 X3 Y3 X3 Z0 Y1 X1 X1 14
0 1 0 0 X4 Z1 Y0 X0 X2 15
0 1 0 1 X5 Z1 Y0 X1 X3 12 3 X
0 1 1 0 X6 Z1 Y1 X0 X4 1
0 1 1 1 X7 Z1 Y1 X1 X5 5
1 x x x None None None X6 2
*Not applicable for MC14052 X7 4
x = Don’t Care
Figure 2. MC14051B Functional Diagram
16 VDD
16 VDD
INH 6 BINARY TO 1–OF–4
LEVEL
A 10 DECODER WITH INH 6 BINARY TO 1–OF–2
CONVERTER A 11 LEVEL
B 9 INHIBIT DECODER WITH
B 10 CONVERTER
C 9 INHIBIT
8 VSS 7 VEE
X0 12 8 VSS 7 VEE
X1 14
13 X
X2 15 X0 12
14 X
X3 11 X1 13
Y0 1 Y0 2
15 Y
Y1 5 Y1 1
3 Y
Y2 2 Z0 5
4 Z
Y3 4 Z1 3
Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram
http://onsemi.com
20
MC14051B, MC14052B, MC14053B
TEST CIRCUITS
ON SWITCH
CONTROL A
PULSE
SECTION B
GENERATOR
OF IC C
LOAD Vout
V CL
INH RL
SOURCE
VDD VEE VEE VDD
Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output
A, B, and C inputs used to turn ON

or OFF
the switch under test. RL
A
B A
C B ON
Vout
C
VSS INH RL CL = 50 pF
INH OFF
Vout
Vin RL CL = 50 pF
VDD – VEE
2 VDD – VEE Vin
2
Figure 7. Bandwidth and Off–Channel Figure 8. Channel Separation

Feedthrough Attenuation (Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST

VDD
VEE
A CONTROL
B SECTION OTHER
C CHANNEL(S)
Vout OF IC VEE
INH RL CL = 50 pF VDD
R1
VEE
COMMON
VDD
Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage

Common O/I
NOTE: See also Figures 7 and 8 in the MC14016B

data sheet.
http://onsemi.com
21
MC14051B, MC14052B, MC14053B
VDD KEITHLEY 160

DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X–Y
PLOTTER
VEE = VSS
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS

350 350
300 300
R ON , “ON” RESISTANCE (OHMS)

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V
700 350
TA = 25°C
600 300
RON , “ON” RESISTANCE (OHMS)
500 250 VDD = 2.5 V
400 200
300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 14. VDD = 2.5 V, VEE = – 2.5 V Figure 15. Comparison at 25°C, VDD = – VEE
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22
MC14051B, MC14052B, MC14053B
Figure A illustrates use of the on–chip level converter peak. If voltage transients above V DD and/or below V EE are
detailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control anticipated on the analog channels, external diodes (Dx) are
signal is used to directly control a 9 V p–p analog signal. recommended as shown in Figure B. These diodes should be
The digital control logic levels are determined by V DD small signal types able to absorb the maximum anticipated
and V SS. The V DD voltage is the logic high voltage; the V SS current surges during clipping.
voltage is logic low. For the example, V DD = + 5 V = logic The absolute maximum potential difference between
high at the control inputs; VSS = GND = 0 V = logic low. V DD and V EE is 18.0 V. Most parameters are specified up to
The maximum analog signal level is determined by V DD 15 V which is the recommended maximum difference
and V EE. The V DD voltage determines the maximum between V DD and V EE.
recommended peak above V SS. The V EE voltage Balanced supplies are not required. However, V SS must
determines the maximum swing below V SS. For the be greater than or equal to VEE. For example, V DD = + 10
example, V DD – V SS = 5 V maximum swing above V SS ; V, V SS = + 5 V, and V EE – 3 V is acceptable. See the Table
V SS – V EE = 5 V maximum swing below VSS. The example below.
shows a ± 4.5 V signal which allows a 1/2 volt margin at each
+5 V –5 V
VDD VSS VEE
+ 4.5 V
ANALOG SIGNAL I/O COMMON 9 Vp–p
GND
MC14051B O/I ANALOG SIGNAL
MC14052B
EXTERNAL MC14053B
CMOS – 4.5 V
DIGITAL
CIRCUITRY 0–TO–5 V DIGITAL INHIBIT,
CONTROL SIGNALS A, B, C
VDD VDD
DX DX
ANALOG COMMON
I/O O/I
DX DX
VEE VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ Control Inputs
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
VDD
ÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
In Volts
VSS
ÎÎÎÎÎÎÎÎÎ
In Volts
VEE
In Volts
Logic High/Logic Low
In Volts
Maximum Analog Signal Range
In Volts
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+8 0 –8 + 8/0 + 8 to – 8 = 16 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+5 0 – 12 + 5/0 + 5 to – 12 = 17 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+5 0 0 + 5/0 + 5 to 0 = 5 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
+5
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
0 –5 + 5/0 + 5 to – 5 = 10 Vp–p
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
+ 10
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
+5 –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p
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23
MC14051B, MC14052B, MC14053B
ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMATION:

Device Package Shipping MC14053BCP PDIP–16 2000 Units per Box
MC14051BCP PDIP–16 2000 Units per Box MC14053BD SOIC–16 48 Units per Rail
MC14051BD SOIC–16 48 Units per Rail MC14053BDR2 SOIC–16 2500 Units / Tape & Reel
MC14051BDR2 SOIC–16 2500 Units / Tape & Reel MC14053BDT TSSOP–16 96 Units per Rail
MC14051BDT TSSOP–16 96 Units per Rail MC14053BDTEL TSSOP–16 2000 Units / Tape & Reel
MC14051BDTEL TSSOP–16 2000 Units / Tape & Reel MC14053BDTR2 TSSOP–16 2500 Units / Tape & Reel
MC14051BDTR2 TSSOP–16 2500 Units / Tape & Reel MC14053BF SOEIAJ–16 See Note 7.
MC14051BF SOEIAJ–16 See Note 7. MC14053BFEL SOEIAJ–16 See Note 7.
MC14051BFEL SOEIAJ–16 See Note 7. 7. For ordering information on the EIAJ version of the SOIC
packages, please contact your local ON Semiconductor rep-
resentative.
MC14052BCP PDIP–16 2000 Units per Box
MC14052BD SOIC–16 48 Units per Rail
MC14052BDR2 SOIC–16 2500 Units / Tape & Reel
MC14052BDT TSSOP–16 96 Units per Rail
MC14052BDTR2 TSSOP–16 2500 Units / Tape & Reel
MC14052BF SOEIAJ–16 See Note 7.
MC14052BFEL SOEIAJ–16 See Note 7.
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24
MC14066B
Quad Analog Switch/Quad

Multiplexer
The MC14066B consists of four independent switches capable of

controlling either digital or analog signals. This quad bilateral switch
is useful in signal gating, chopper, modulator, demodulator and
CMOS logic implementation. http://onsemi.com
The MC14066B is designed to be pin–for–pin compatible with the
MC14016B, but has much lower ON resistance. Input voltage swings MARKING
as large as the full supply voltage can be controlled via each DIAGRAMS
independent control input. 14
PDIP–14
• Triple Diode Protection on All Control Inputs P SUFFIX MC14066BCP
• Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 646 AWLYYWW
• Linearized Transfer Characteristics 1
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical 14
• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B

SOIC–14
D SUFFIX
14066B
•
AWLYWW
For Lower RON, Use The HC4066 High–Speed CMOS Device CASE 751A
1
14
TSSOP–14 14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) DT SUFFIX 066B
CASE 948G ALYW
VDD DC Supply Voltage Range – 0.5 to +18.0 V 1
14
(DC or Transient) SOEIAJ–14
F SUFFIX MC14066B
Iin Input Current (DC or Transient) ± 10 mA CASE 965 AWLYWW
per Control Pin
1
ISW Switch Through Current ± 25 mA
PD Power Dissipation, 500 mW WL or L = Wafer Lot
per Package (Note 3.) YY or Y = Year
TA Ambient Temperature Range – 55 to +125 °C WW or W = Work Week

TL Lead Temperature 260 °C ORDERING INFORMATION
(8–Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device
may occur. MC14066BCP PDIP–14 2000/Box
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC14066BD SOIC–14 55/Rail
This device contains protection circuitry to guard against damage due to high MC14066BDR2 SOIC–14 2500/Tape & Reel
static voltages or electric fields. However, precautions must be taken to avoid 96/Rail
MC14066BDT TSSOP–14
VDD.
MC14066BDTEL TSSOP–14 2000/Tape & Reel
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14066BDTR2 TSSOP–14 2500/Tape & Reel
MC14066BFEL SOEIAJ–14 See Note 1.

the SOIC packages, please contact your local
ON Semiconductor representative.

March, 2000 – Rev. 3 MC14066B/D
MC14066B
PIN ASSIGNMENT
IN 1 1 14 VDD
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3
BLOCK DIAGRAM LOGIC DIAGRAM AND TRUTH TABLE

13 (1/4 OF DEVICE SHOWN)
CONTROL 1 2
1 OUT 1
IN/OUT OUT/IN
IN 1
5
CONTROL 2 3 CONTROL
4 OUT 2
IN 2 Control Switch Logic Diagram Restrictions
6 0 = VSS OFF VSS ≤ Vin ≤ VDD
CONTROL 3
9 VSS ≤ Vout ≤ VDD
OUT 3 1 = VDD ON
8
IN 3
12
CONTROL 4 10
11 OUT 4
IN 4 VDD = PIN 14
VSS = PIN 7
CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
VDD VDD VDD
VSS
VDD
VDD VDD VDD
CMOS
INPUT 300 Ω
VSS VSS
http://onsemi.com
26
MC14066B
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
– 55_C 25_C 125_C
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Power Supply Voltage
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VDD ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎ
— 3.0 18 3.0 — 18 3.0 18 V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Range
µA
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: — 0.25 — 0.005 0.25 — 7.5
Package 10 Vin = VSS or VDD, — 0.5 — 0.010 0.5 — 15
v
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 Switch I/O: VSS VI/O — 1.0 — 0.015 1.0 — 30
v
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
VDD, and
v ∆Vswitch 500 mV (5.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ
ID(AV)
5.0 TA = 25_C only The
µA
ÎÎ ÎÎ
(Dynamic Plus Quiescent, 10 channel component,
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Per Package 15 (Vin – Vout)/Ron, is
not included.)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
CONTROL INPUTS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
Low–Level Input Voltage
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎ
VIL
ÎÎÎ
ÎÎÎÎÎ
5.0
10
15
Ron = per spec,
Ioff = per spec
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
VIH
ÎÎÎ
ÎÎÎÎÎ 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
10
15
Ioff = per spec 7.0
11
—
—
7.0
11
5.50
8.25
—
—
7.0
11
—
—
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µA
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
SWITCHES IN AND OUT (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Recommended Peak–to– VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD Vp–p
Peak Voltage Into or Out
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
of the Switch
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Output Offset Voltage
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VOO
ÎÎ — Vin = 0 V, No Load — — — 10 — — — µV
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ON Resistance v
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Ron
ÎÎÎ
ÎÎÎÎÎ 5.0 ∆Vswitch 500 mV (5.), — 800 — 250 1050 — 1200 Ω
ÎÎ ÎÎ ÎÎ
10 Vin = VIL or VIH — 400 — 120 500 — 520
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
15 (Control), and Vin = — 220 — 80 280 — 300
0 to VDD (Switch)
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
∆ON Resistance Between
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
∆Ron
ÎÎÎ
ÎÎÎÎÎ 5.0 — 70 — 25 70 — 135 Ω
ÎÎ ÎÎ ÎÎ
Any Two Channels 10 — 50 — 10 50 — 95
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
in the Same Package 15 — 45 — 10 45 — 65
±100 ± 0.05 ±100 ± 1000
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — — — nA
ÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Channel or Any One
Channel
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Capacitance, Switch I/O
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
CI/O
ÎÎ — Switch Off — — — 10 15 — — pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
(Switch Off) ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
CI/O
ÎÎÎ ÎÎ
ÎÎÎÎÎ
—
—
— — — 0.47 — — — pF
5. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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27
MC14066B
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C unless otherwise noted.)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Typ (7.) Max Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Times VSS = 0 Vdc tPLH,tPHL ns
Input to Output (RL = 10 kΩ)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns 5.0 — 20 40
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns 10 — 10 20
tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns 15 — 7.0 15
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Control to Output (RL = 1 kΩ) (Figure 2)
ÎÎÎÎ
ÎÎÎ
Output “1” to High Impedance
tPHZ
5.0 — 40 80
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 — 35 70
15 — 30 60
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Output “0” to High Impedance
ÎÎÎÎ
ÎÎÎ
tPLZ 5.0
10
15
—
—
—
40
35
30
80
70
60
ns
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
High Impedance to Output “1” tPZH 5.0
10
—
—
60
20
120
40
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 — 15 30
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
High Impedance to Output “0” tPZL 5.0 — 60 120 ns
10 — 20 40
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion ÎÎÎ
ÎÎÎÎ
ÎÎÎ VSS = – 5 Vdc —
15
5.0
—
—
15
0.1
30
— %
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,
RL = 10 kΩ, f = 1.0 kHz)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Bandwidth (Switch ON) (Figure 3)
ÎÎÎÎ
ÎÎÎ
VSS = – 5 Vdc
(RL = 1 kΩ, 20 Log (Vout/Vin) = – 3 dB, CL = 50 pF,
— 5.0 — 65 — MHz
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin = 5 Vp–p)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc — 5.0 — – 50 — dB
(Vin = 5 Vp–p, RL = 1 kΩ, fin = 1.0 MHz) (Figure 3)
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
Channel Separation (Figure 4)
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Vin = 5 Vp–p, RL = 1 kΩ, fin = 8.0 MHz)
VSS = – 5 Vdc — 5.0 — – 50 — dB
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Switch A ON, Switch B OFF)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Crosstalk, Control Input to Signal Output (Figure 5) mVp–p
VSS = – 5 Vdc — 5.0 — 300 —
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(R1 = 1 kΩ, RL = 10 kΩ, Control tTLH = tTHL = 20 ns)
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28
MC14066B
TEST CIRCUITS
Vout
VC
RL CL
ON SWITCH
Vin Vx
CONTROL 20 ns
SECTION VDD
90%
OF IC VC 50%
10%
tPZH VSS
tPHZ
LOAD 90%
V Vout Vin = VDD
10%
tPZL tPLZ Vx = VSS
90%
Vout Vin = VSS
SOURCE 10% Vx = VDD
Figure 1. ∆V Across Switch Figure 2. Turn–On Delay Time Test Circuit

and Waveforms
VDD – VSS
VC = VDD FOR BANDWIDTH TEST 2
VC = VSS FOR FEEDTHROUGH TEST
VDD – VSS Vin

2
RL CL
VDD
Vin Vout
RL CL
VC
RL CL
VSS
VDD VSS
Figure 3. Bandwidth and Figure 4. Channel Separation

Feedthrough Attenuation

VDD
Vin
A
Vout VSS
1k CONTROL
RL CL = 50 pF SECTION
10 k OF IC
VSS
VC = – 5.0 V TO + 5.0 V SWING VDD
Figure 5. Crosstalk, Figure 6. Off Channel Leakage

Control to Output
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29
MC14066B
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X–Y
PLOTTER
VSS
350 350
300 300

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 8. VDD = 7.5 V, VSS = – 7.5 V Figure 9. VDD = 5.0 V, VSS = – 5.0 V
700 350
TA = 25°C
600 300
RON , “ON” RESISTANCE (OHMS)
500 250 VDD = 2.5 V
400 200
300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 10. VDD = 2.5 V, VSS = – 2.5 V Figure 11. Comparison at 25°C, VDD = – VSS
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30
MC14066B
Figure A illustrates use of the Analog Switch. The 0– V DD and/or below V SS are anticipated on the analog
to–5 volt digital control signal is used to directly control a channels, external diodes (Dx) are recommended as shown
5 volt peak–to–peak analog signal. in Figure B. These diodes should be small signal types able
The digital control logic levels are determined by V DD to absorb the maximum anticipated current surges during
and V SS. The V DD voltage is the logic high voltage, the V SS clipping.
high at the control inputs; VSS = GND = 0 V = logic low. V DD and V SS is 18.0 volts. Most parameters are specified up
The maximum analog signal level is determined by V DD to 15 volts which is the recommended maximum difference
and VSS. The analog voltage must not swing higher than between V DD and V SS.
V DD or lower than V SS.
The example shows a 5 volt peak–to–peak signal which
allows no margin at either peak. If voltage transients above
+5 V
VDD VSS
+ 5.0 V
5 Vp–p SWITCH
ANALOG SIGNAL IN SWITCH 5 Vp–p
+ 2.5 V
+5 V OUT ANALOG SIGNAL
GND
EXTERNAL 0–TO–5 V DIGITAL MC14066B
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY
VDD VDD
DX DX
SWITCH SWITCH
IN OUT
DX DX
VSS VSS
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31
MC14067B
Analog Multiplexers /
Demultiplexers
The MC14067 multiplexer/demultiplexer is a digitally controlled

analog switch featuring low ON resistance and very low leakage
current. This device can be used in either digital or analog
applications. http://onsemi.com
The MC14067 is a 16–channel multiplexer/demultiplexer with an
inhibit and four binary control inputs A, B, C, and D. These control MARKING
inputs select 1–of–16 channels by turning ON the appropriate analog DIAGRAMS
switch (see MC14067 truth table.) 24
• Low OFF Leakage Current

PDIP–24
P SUFFIX MC14067BCP
• Matched Channel Resistance CASE 709 AWLYYWW
• Low Quiescent Power Consumption 1

• Low Crosstalk Between Channels
24
• Wide Operating Voltage Range: 3 to 18 V SOIC–24
• Low Noise DW SUFFIX
14067B
AWLYYWW
• Pin for Pin Replacement for CD4067B CASE 751E
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
WL or L = Wafer Lot
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) YY or Y = Year
WW or W = Work Week
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
VDD DC Supply Voltage Range – 0.5 to + 18.0 V
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V ORDERING INFORMATION
(DC or Transient)
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
± 10
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Iin Input Current (DC or Transient), mA
per Control Pin MC14067BCP PDIP–24 15/Rail
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Isw Switch Through Current ± 25 mA MC14067BDW SOIC–24 30/Rail
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
PD Power Dissipation, 500 mW MC14067BDWR2 SOIC–24 1000/Tape & Reel
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
per Package (Note 2.)
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
TA Ambient Temperature Range – 55 to + 125 _C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
Tstg Storage Temperature Range – 65 to + 150 _C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
TL Lead Temperature 260 _C
may occur.
to the range VSS v(Vin or Vout) v
VDD.

March, 2000 – Rev. 3 MC14067B/D
MC14067B
MC14067 TRUTH TABLE

Control Inputs
Selected
A B C D Inh Channel
X X X X 1 None
0 0 0 0 0 X0
1 0 0 0 0 X1
0 1 0 0 0 X2
1 1 0 0 0 X3
0 0 1 0 0 X4
1 0 1 0 0 X5
0 1 1 0 0 X6
1 1 1 0 0 X7
0 0 0 1 0 X8
1 0 0 1 0 X9
0 1 0 1 0 X10
1 1 0 1 0 X11
0 0 1 1 0 X12
1 0 1 1 0 X13
0 1 1 1 0 X14
1 1 1 1 0 X15
MC14067B
PIN ASSIGNMENT
X 1 24 VDD
X7 2 23 X8
X6 3 22 X9
X5 4 21 X10
X4 5 20 X11
X3 6 19 X12
X2 7 18 X13
X1 8 17 X14
X0 9 16 X15
A 10 15 INHIBIT
B 11 14 C
VSS 12 13 D
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33
MC14067B
MC14067B
16–Channel Analog
Multiplexer/Demultiplexer
15 INHIBIT
10 A
CONTROLS 11 B
14 C
13 D
9 X0
8 X1
7 X2
6 X3
5 X4
COMMON
4 X5 X 1
OUT/IN
3 X6
SWITCHES 2 X7
IN/OUT 23 X8
22 X9
21 X10 VDD = PIN 24
20 X11 VSS = PIN 12
19 X12
18 X13
17 X14
16 X15
MC14067 FUNCTIONAL DIAGRAM
INHIBIT
CONTROL A
B 1–OF–16 DECODER
INPUTS C
D
X0
X1
X2
X3
X4
X5
X6
X X7 X
IN/OUT X8
X9 OUT/IN
X10
X11
X12
X13
X14
X15
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34
MC14067B
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎ
Î
ÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎ
– 55°C 25_C 125_C
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Power Supply Voltage VDD — 3.0 18 3.0 — 18 3.0 18 V
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Range
µA
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: Vin = — 5.0 — 0.005 5.0 — 150
Package 10 VSS or VDD, — 10 — 0.010 10 — 300
v v
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
15 Switch I/O: VSS VI/O — 20 — 0.015 20 — 600
VDD, and
ÎÎÎÎÎÎÎÎ
ÎÎÎ
v
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ∆Vswitch 500 mV (4.)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ID(AV)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ 5.0 TA = 25_C only (The

µA
ÎÎ
Quiescent, 15 (Vin – Vout)/Ron, is
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Per Package not included.)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Low–Level Input Voltage VIL 5.0 Ron = per spec, — 1.5 — 2.25 1.5 — 1.5 V
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
10 Ioff = per spec — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
VIH
ÎÎÎÎÎ
ÎÎ
5.0
10
Ron = per spec,
Ioff = per spec
3.5
7.0
—
—
3.5
7.0
2.75
5.50
—
—
3.5
7.0
—
—
V
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
15 11 — 11 8.25 — 11 —
± 0.1 ± 0.00001 ± 0.1 µA
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Input Leakage Current Iin 15 Vin = 0 or VDD — — — 1.0
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Out of the Switch
ÎÎÎ
ÎÎÎ
Peak Voltage Into or
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Dynamic Voltage
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Across the Switch (4.)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
(Figure 1)
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
v
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ON Resistance Ron 5.0 ∆Vswitch 500 mV (4.), — 800 — 250 1050 — 1300 Ω
10 Vin = VIL or VIH — 400 — 120 500 — 550
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
15 (Control), and Vin — 220 — 80 280 — 320
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
0 to VDD (Switch)
∆ON Resistance Between ∆Ron Ω
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
5.0 — 70 — 25 70 — 135
Any Two Channels 10 — 50 — 10 50 — 95
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ±100 — ± 1000 nA
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Channel or Any One
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Channel
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 10 — — — pF
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
Capacitance, Common O/I CO/I — Inhibit = VDD pF
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎ
(MC14067B)
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎ
100
ÎÎÎ
—
ÎÎÎ
—
ÎÎÎ
—
(MC14097B) — — — 60 — — —
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
CI/O
ÎÎÎ
— Pins Not Adjacent — — — 0.47 — — — pF
ÎÎ
(Channel Off) — Pins Adjacent
4. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.
the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
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35
MC14067B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
VDD – VSS
Typ (5.)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Max Unit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Propagation Delay Times tPLH, tPHL ns
Channel Input–to–Channel Output (RL = 200 kΩ)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14067B (Figure 3) 5.0 35 90
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 15 40
15 12 30
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Control Input–to–Channel Output
ÎÎÎÎ
ÎÎÎ
Channel Turn–On Time (RL = 10 kΩ)
tPZH, tPZL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14067B (Figure 4) 5.0 240 600
10 115 290
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
15 75 190
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Channel Turn–Off Time (RL = 300 kΩ) tPHZ, tPLZ ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
MC14067B
(Figure 4) 5.0 250 625
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
10 120 300
15 75 190
ÎÎÎÎÎ
MC14067B ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Any Pair of Address Inputs to Output
ÎÎÎÎ
ÎÎÎ
tPLH, tPHL ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.0 280 700
10 115 290
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion ÎÎÎ
ÎÎÎÎ
ÎÎÎ —
15
10
85
0.3
215
— %
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ON Channel Bandwidth BW MHz
[RL = 1 kΩ, Vin = 1/2 (VDD – VSS) p–p(sine–wave)]
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
20 Log10 (Vout/Vin) = – 3 dB
ÎÎÎÎ
ÎÎÎ
Off Channel Feedthrough Attenuation
MC14067B (Figure 5)
—
10
10
15
– 40
—
— dB
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p(sine–wave)]
fin = 20 MHz – MC14067B (Figure 5)
ÎÎÎÎÎ
Channel Separation
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
[RL = 1 kΩ, Vin = 1/2 (VDD–VSS) p–p (sine–wave)]
— 10 – 40 — dB
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 20 MHz (Figure 6)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Crosstalk, Control Inputs–to–Common O/I — 10 30 — mV
(R1 = 1 kΩ, RL = 10 kΩ,
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
Control tr = tf = 20 ns, Inhibit = VSS) (Figure 7)
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36
MC14067B

ON SWITCH VDD
A VSS
CONTROL
SECTION CONTROL
OF IC SECTION OTHER
OF IC CHANNEL(S) VSS
LOAD
V VDD
SOURCE
VSS
VDD
Figure 1. ∆V Across Switch Figure 2. Off Channel Leakage
VC
PULSE A
B
GENERATOR C
VDD Vout
D
A CL = 50 pF
B INH RL
C
D Vout Vin VX
INH RL CL = 50 pF VDD VSS VSS VDD
Vin 20 ns 20 ns
90%
VC 50%
20 ns 20 ns 10%
VDD
90%
Vin 50% 90% Vin = VDD
10% Vout
VSS 50% VX = VSS
tPLH tPHL
tPZH, tPZL tPHZ, tPLZ
Vout 50%
Vout 50% Vin = VSS
10% VX = VDD
Figure 3. Propagation Delay Test Circuit Figure 4. Turn–On and Delay Turn–Off
and Waveforms Vin to Vout Test Circuit and Waveforms
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37
MC14067B
VDD
A, B, and C inputs used to turn ON or OFF RL
the switch under test. A
B ON
C
A D
B
C INH OFF
D Vout Vout
INH RL CL = 50 pF
RL CL = 50 pF
Vin Vin

Feedthrough Attenuation (Adjacent Channels Used for Setup)
A
VC B
C
D Vout
INH RL CL = 50 pF
R1
Figure 7. Crosstalk, Control to Common O/I
VA A
VB B
C
D
INH VDD
VDD CL
Vout
KEITHLEY 160
DIGITAL
MULTIMETER
VA 50%
10 k
VDD
1 kΩ
RANGE X–Y VB 50%
PLOTTER
VSS tPHL tPLH
Vout 50%
Figure 8. Channel Resistance (RON) Test Circuit Figure 9. Propagation Delay, Any Pair of
Address Inputs to Output
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38
MC14067B
350 350
300 300

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 10. VDD = 7.5 V, VSS = – 7.5 V Figure 11. VDD = 5.0 V, VSS = – 5.0 V
700 350
TA = 25°C
600 RON , “ON” RESISTANCE (OHMS) 300
500 250 VDD = 2.5 V
400 200
300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Figure 12. VDD = 2.5 V, VSS = – 2.5 V Figure 13. Comparison at 25°C, VDD = – VSS
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39
MC14067B
Figure A illustrates use of the Analog signal which allows no margin at either peak. If voltage
Multiplexer/Demultiplexer. The 0–to–5 volt Digital Control transients above V DD and/or below V SS are anticipated on
signal is used to directly control a 5 Vp–p analog signal. the analog channels, external diodes (Dx) are recommended
The digital control logic levels are determined by VDD as shown in Figure B. These diodes should be small signal
and VSS. The VDD voltage is the logic high voltage; the VSS types able to absorb the maximum anticipated current surges
voltage is logic low. For the example. VDD = + 5 V = logic during clipping.
high at the control inputs; VSS = GND = 0 V = logic low. The absolute maximum potential difference between VDD
The maximum analog signal level is determined by V DD and VSS is 18.0 volts. Most parameters are specified up to
and V SS. The analog voltage must swing neither higher than 15 V which is the recommended maximum difference
V DD nor lower than V SS. The example shows a 5 V p–p between VDD and VSS.
+5 V
VDD VSS
+ 5.0 V
5 Vp–p SWITCH
ANALOG SIGNAL I/O COMMON 5 Vp–p
+ 2.5 V
+5 V O/I ANALOG SIGNAL
GND
MC14067B
EXTERNAL 0–TO–5 V DIGITAL
CMOS
CONTROL SIGNALS
DIGITAL
CIRCUITRY
VDD VDD
DX DX
SWITCH COMMON
I/O O/I
DX DX
VSS VSS
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40
MC14512B
8-Channel Data Selector

The MC14512B is an 8–channel data selector constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
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sequence generation.
• Diode Protection on All Inputs
• Single Supply Operation MARKING
DIAGRAMS
• 3–State Output (Logic “1”, Logic “0”, High Impedance)
16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc PDIP–16
• Capable of Driving Two Low–power TTL Loads or One Low–power P SUFFIX MC14512BCP
AWLYYWW
Schottky TTL Load Over the Rated Temperature Range CASE 648
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note NO TAG) SOIC–16
14512B
D SUFFIX AWLYWW
CASE 751B
VDD DC Supply Voltage Range – 0.5 to +18.0 V 1
(DC or Transient) 16
Iin, Iout Input or Output Current ± 10 mA SOEIAJ–16
(DC or Transient) per Pin F SUFFIX MC14512B
CASE 966 AWLYWW
PD Power Dissipation, 500 mW
per Package (Note NO TAG) 1
TA Ambient Temperature Range – 55 to +125 °C
WL or L = Wafer Lot
TL Lead Temperature 260 °C YY or Y = Year
(8–Second Soldering) WW or W = Work Week
may occur.
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C ORDERING INFORMATION
This device contains protection circuitry to guard against damage due to high Device Package Shipping
applications of any voltage higher than maximum rated voltages to this MC14512BCP PDIP–16 2000/Box
VDD.
MC14512BD SOIC–16 48/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14512BDR2 SOIC–16 2500/Tape & Reel
MC14512BFL1 SOEIAJ–16 See Note 1.
MC14512BFR1 SOEIAJ–16 See Note 1.
MC14512BFR2 SOEIAJ–16 See Note 1.

the SOIC packages, please contact your local

March, 2000 – Rev. 3 MC14512B/D
MC14512B
TRUTH TABLE
C B A Inhibit Disable Z
0 0 0 0 0 X0
0 0 1 0 0 X1
0 1 0 0 0 X2
0 1 1 0 0 X3
1 0 0 0 0 X4
1 0 1 0 0 X5
1 1 0 0 0 X6
1 1 1 0 0 X7
X X X 1 0 0
X X X X 1 High
Impedance
X = Don’t Care
PIN ASSIGNMENT
X0 1 16 VDD
X1 2 15 DIS
X2 3 14 Z
X3 4 13 C
X4 5 12 B
X5 6 11 A
X6 7 10 INH
VSS 8 9 X7
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42
MC14512B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current (5.) (6.) IT 5.0 IT = (0.8 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.6 µA/kHz) f + IDD
Per Package) 15 IT = (2.4 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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43
MC14512B
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C, See Figure 1)

All Types
Characteristic Symbol VDD Typ (8.) Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
Propagation Delay Time (Figure 2) tPLH ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
Propagation Delay Time (Figure 2) tPHL ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
3–State Output Delay Times (Figure 3) tPHZ, tPLZ, 5.0 60 150 ns
“1” or “0” to High Z, and tPZH, tPZL 10 35 100
High Z to “1” or “0” 15 30 75
ID VDD
DISABLE
INHIBIT Z
A CL
B
C
X0
X1
PULSE X2
Vin 50% GENERATOR
50% X3
DUTY X4
CYCLE X5
X6
X7
VSS
Figure 1. Power Dissipation Test Circuit and Waveform
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44
MC14512B
VDD
20 ns 20 ns
90% VDD
DISABLE DATA 50%
INHIBIT Z 10% VSS
A tPLH tPHL
CL 90% VOH
B 50%
C Z 10%
VOL
X0 tTLH tTHL
PULSE X1
GENERATOR TEST CONDITIONS:
X2 INHIBIT = VSS
X3 A, B, C = VSS
X4
X5 20 ns 20 ns
X6 INHIBIT, VDD
90%
X7 A, B, OR C 50%
10% VSS
tPHL tPLH
VSS Parameter Test Conditions 90% VOH
50%
Inhibit to Z A, B, C = VSS, XO = VDD Z 10% VOL
A, B, C to Z Inh = VSS, XO = VDD tTHL tTLH
Figure 2. AC Test Circuit and Waveforms
VDD
PULSE 20 ns
VDD 20 ns
GENERATOR VDD
DISABLE 90%
VDD 50%
INHIBIT Z DISABLE 10%
CL VSS
A INPUT
B 1k S1 tPZL
S3 tPLZ
C VOH
90%
X0 S2 OUTPUT 10% ≈ 2.5 V @ VDD = 5 V,
VOL
S4 X1 10 V, AND 15 V
tPHZ tPZH
X2 ≈ 2 V @ VDD = 5 V
X3 VSS OUTPUT VOH ≈ 6 V @ VDD = 10 V
90%
VSS X4 10% ≈ 10 V @ VDD = 15 V
VOL
X5
X6 Switch Positions for 3–State Test
X7 Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
VSS
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open
Figure 3. 3–State AC Test Circuit and Waveform
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45
MC14512B
LOGIC DIAGRAM
13
C
12
B 15
11 DISABLE
A
1 10 DATA
X0 SELECTED
BUS
INHIBIT DEVICE
2 VDD IOD
X1
MC14512B
3 IL
X2
14 LOAD
Z ITL
4
X3 MC14512B
5
X4
ITL
6 MC14512B
X5
7 VSS
X6
9
X7 1 1
OUT
IN IN OUT
2 2
TRANSMISSION
GATE
3–STATE MODE OF OPERATION
Output terminals of several MC14512B 8–Bit Data (including fanout to other device inputs), and can be
Selectors can be connected to a single date bus as shown. calculated by:
One MC14512B is selected by the 3–state control, and the IOD – IL
remaining devices are disabled into a high–impedance “off” N= +1
ITL
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive N must be calculated for both high and low logic state of the
current, IOD, 3–state or disable output leakage current, ITL, bus line.
and the load current, IL, required to drive the bus line
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46
MC14551B
Quad 2-Channel Analog

The MC14551B is a digitally–controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved. http://onsemi.com
• Triple Diode Protection on All Control Inputs

MARKING
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
DIAGRAMS
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be VSS v PDIP–16
16
• Linearized Transfer Characteristics P SUFFIX MC14551BCP

AWLYYWW
• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical CASE 648
• For Low RON, Use The HC4051, HC4052, or HC4053 High–Speed

1
CMOS Devices 16
• Switch Function is Break Before Make SOIC–16
14551B
D SUFFIX AWLYWW
CASE 751B
1
MAXIMUM RATINGS (2.) 16
Symbol Parameter Value Unit SOEIAJ–16

F SUFFIX MC14551B
VDD DC Supply Voltage Range – 0.5 to + 18.0 V CASE 966 AWLYWW
(Referenced to VEE, VSS ≥ VEE)
1
Vin, Vout Input or Output Voltage (DC or – 0.5 to VDD + 0.5 V
Transient) (Referenced to VSS for A = Assembly Location
Control Input & VEE for Switch I/O) WL or L = Wafer Lot
Iin Input Current (DC or Transient), ± 10 mA YY or Y = Year
per Control Pin WW or W = Work Week
Isw Switch Through Current ± 25 mA

PD Power Dissipation, per Package (3.) 500 mW ORDERING INFORMATION
TA Ambient Temperature Range – 55 to + 125 _C Device Package Shipping
Tstg Storage Temperature Range – 65 to + 150 _C MC14551BCP PDIP–16 2000/Box
TL Lead Temperature 260 _C MC14551BD SOIC–16 48/Rail
MC14551BDR2 SOIC–16 2500/Tape & Reel
may occur. MC14551BF SOEIAJ–16 See Note 1.
3. Temperature Derating: 1. For ordering information on the EIAJ version of
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C the SOIC packages, please contact your local
v v
to the range VSS (Vin or Vout) VDD for control inputs and VEE ≤ (Vin or Vout) ≤
VDD for Switch I/O.
either VSS, VEE or VDD). Unused outputs must be left open.

March, 2000 – Rev. 3 MC14551B/D
MC14551B
PIN ASSIGNMENT
W1 1 16 VDD
X0 2 15 W0
X1 3 14 W
X 4 13 Z
Y 5 12 Z1
Y0 6 11 Z0
VEE 7 10 Y1
VSS 8 9 CONTROL
9 CONTROL
W 14
15 W0
1 W1 X 4
2 X0 COMMONS
SWITCHES 3 X1 OUT/IN
IN/OUT 6 Y0 Y 5
10 Y1
11 Z0 Z 13
12 Z1
VDD = Pin 16 Control ON

VSS = Pin 8 0 W0 X0 Y0 Z0
VEE = Pin 7
1 W1 X1 Y1 Z1
NOTE: Control Input referenced to VSS, Analog Inputs and

Outputs reference to VEE. VEE must be VSS. v
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48
MC14551B
Characteristic Symbol VDD Test Conditions

– 55_C
Min Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit

Power Supply Voltage VDD — VDD – 3.0 ≥ VSS ≥ 3.0 18 3.0 — 18 3.0 18 V
Range VEE
Quiescent Current Per IDD 5.0 Control Inputs: Vin = — 5.0 — 0.005 5.0 — 150 µA
Package 10 VSS or VDD, — 10 — 0.010 10 — 300
15 Switch I/O: VEE v VI/O — 20 — 0.015 20 — 600
v VDD, and ∆Vswitch
v 500 mV (5.)
Total Supply Current ID(AV) 5.0 TA = 25_C only (The µA
Quiescent, Per Package) 15 (Vin – Vout)/Ron, is
not included.)
CONTROL INPUT (Voltages Referenced to VSS)
Low–Level Input Voltage VIL 5.0 Ron = per spec, — 1.5 — 2.25 1.5 — 1.5 V
10 Ioff = per spec — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
High–Level Input Voltage VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —
15 11 — 11 8.25 — 11 —
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µA
SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE)
Peak Voltage Into or Out
of the Switch
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
ON Resistance Ron 5.0 v
∆Vswitch 500 mV (5.), — 800 — 250 1050 — 1200 Ω
10 Vin = VIL or VIH — 400 — 120 500 — 520
15 (Control), and Vin = 220 — 80 280 — 300
0 to VDD (Switch)
∆ON Resistance Between ∆Ron 5.0 — 70 — 25 70 — 135 Ω
Any Two Channels 10 — 50 — 10 50 — 95
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ± 100 — ± 1000 nA
Channel or Any One
Channel
Capacitance, Switch I/O CI/O — Switch Off — — — 10 — — — pF
Capacitance, Common O/I CO/I — — — — 17 — — — pF
Capacitance, Feedthrough CI/O — Pins Not Adjacent — — — 0.15 — — — pF
(Channel Off) — Pins Adjacent — — — 0.47 — — —
5. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the
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49
MC14551B
v
ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25_C, VEE
Characteristic Symbol
VSS)
VDD – VEE
Vdc Min Typ (6.) Max Unit
Propagation Delay Times tPLH, tPHL ns
Switch Input to Switch Output (RL = 10 kΩ)
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 — 35 90
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns 10 — 15 40
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 — 12 30
Control Input to Output (RL = 10 kΩ) tPLH, tPHL ns
VEE = VSS (Figure 4) 5.0 — 350 875
10 — 140 350
15 — 100 250
Second Harmonic Distortion — 10 — 0.07 — %
RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p
Bandwidth (Figure 5) BW 10 — 17 — MHz
RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p,
20 Log (Vout / Vin) = – 3 dB, CL = 50 pF
Off Channel Feedthrough Attenuation, Figure 5 — 10 — – 50 — dB
fin = 55 MHz
Channel Separation (Figure 6) — 10 — – 50 — dB
fin = 3 MHz
Crosstalk, Control Input to Common O/I, Figure 7 — 10 — 75 — mV
R1 = 1 kΩ, RL = 10 kΩ,
Control tr = tf = 20 ns
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50
MC14551B
VDD
VDD VDD
IN/OUT OUT/IN
VEE
VDD
LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL
CONTROL
VEE
Figure 1. Switch Circuit Schematic
16 VDD
CONTROL 9 LEVEL
CONTROL
CONVERTER
8 VSS 7 VEE
W0 15
14 W
W1 1
X0 2
4 X
X1 3
Y0 6
5 Y
Y1 10
Z0 11
13 Z
Z1 12
Figure 2. MC14551B Functional Diagram
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51
MC14551B
TEST CIRCUITS
ON SWITCH
CONTROL
PULSE
SECTION
GENERATOR
OF IC CONTROL Vout
LOAD
V RL CL
SOURCE
VDD VEE VEE VDD
Figure 3. ∆V Across Switch Figure 4. Propagation Delay Times,

Control to Output
Control input used to turn ON or OFF

the switch under test.
RL
ON
CONTROL Vout CONTROL
RL CL = 50 pF OFF
Vout
RL CL = 50 pF
Vin
VDD – VEE VDD – VEE Vin
2 2

Feedthrough Attenuation (Adjacent Channels Used for Setup)

VDD
VEE
CONTROL
SECTION OTHER
CONTROL Vout
OF IC CHANNEL(S) VEE
RL CL = 50 pF VDD
R1
VEE
VDD
Figure 7. Crosstalk, Control Input Figure 8. Off Channel Leakage

to Common O/I
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X/Y
PLOTTER
VEE = VSS
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MC14551B

350 350
300 300
RON, “ON” RESISTANCE (OHMS)

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C
50 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10
Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V
700 350
TA = 25°C
600 300
500 250 VDD = 2.5 V
400 200
300 150
5.0 V
TA = 125°C
200 100 7.5 V
25°C
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10
Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V Figure 13. Comparison at 25_C, VDD @ – VEE
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53
MC14551B
Figure A illustrates use of the on–chip level converter margin at each peak. If voltage transients above VDD and/or
detailed in Figure 2. The 0–to–5 volt Digital Control signal below V EE are anticipated on the analog channels, external
is used to directly control a 9 Vp–p analog signal. diodes (Dx) are recommended as shown in Figure B. These
The digital control logic levels are determined by V DD diodes should be small signal types able to absorb the
and V SS. The V DD voltage is the logic high voltage; the V SS maximum anticipated current surges during clipping.
high at the control inputs; VSS = GND = 0 V = logic low. V DD and V EE is 18.0 volts. Most parameters are specified
The maximum analog signal level is determined by V DD up to 15 volts which is the recommended maximum
and V EE. The V DD voltage determines the maximum difference between VDD and V EE.
recommended peak above V SS. The V EE voltage Balanced supplies are not required. However, V SS must
determines the maximum swing below V SS. For the be greater than or equal to V EE. For example, V DD =
example, V DD – V SS = 5 volt maximum swing above V SS; + 10 volts, V SS = + 5 volts, and V EE = – 3 volts is acceptable.
VSS – VEE = 5 volt maximum swing below VSS. The See the table below.
example shows a ± 4.5 volt signal which allows a 1/2 volt
+5 V –5 V
VDD VSS VEE

+ 4.5 V
ANALOG SIGNAL I/O 9 Vp–p
COMMON
GND
O/I ANALOG SIGNAL
EXTERNAL MC14551B
CMOS 0–TO–5 V DIGITAL
CONTROL – 4.5 V
DIGITAL CONTROL SIGNAL
CIRCUITRY
VDD VDD
Dx Dx
SWITCH COMMON
I/O O/I
Dx Dx
VEE VEE
Figure B. External Schottky or Germanium Clipping Diodes
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
POSSIBLE SUPPLY CONNECTIONS
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ
VDD ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
VSS VEE
Control Inputs
Logic High/Logic Low Maximum Analog Signal Range
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
In Volts In Volts In Volts In Volts In Volts
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
+8 0 –8 + 8/0 + 8 to – 8 = 16 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
+5 0 – 12 + 5/0 + 5 to – 12 = 17 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
+5 0 0 + 5/0 + 5 to 0 = 5 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+5
ÎÎÎÎÎÎÎ
0 –5 + 5/0 + 5 to – 5 = 10 Vp–p
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+ 10
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p
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54
MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Demultiplexers
High–Performance Silicon–Gate CMOS http://onsemi.com
MARKING
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize DIAGRAMS
silicon–gate CMOS technology to achieve fast propagation delays,
16
low ON resistances, and low OFF leakage currents. These analog
PDIP–16
multiplexers/demultiplexers control analog voltages that may vary N SUFFIX HC405xAN
across the complete power supply range (from VCC to VEE). 16 AWLYYWW
CASE 648
The HC4051A, HC4052A and HC4053A are identical in pinout to 1
1
the metal–gate MC14051AB, MC14052AB and MC14053AB. The 16
Channel–Select inputs determine which one of the Analog SO–16
Inputs/Outputs is to be connected, by means of an analog switch, to the HC405xAD
D SUFFIX
16 AWLYYWW
Common Output/Input. When the Enable pin is HIGH, all analog CASE 751B
1
switches are turned off. 1
The Channel–Select and Enable inputs are compatible with standard 16
CMOS outputs; with pullup resistors they are compatible with LSTTL SO–16 WIDE
outputs. HC405xA
16 DW SUFFIX
AWLYWW
These devices have been designed so that the ON resistance (Ron) is CASE 751G
more linear over input voltage than Ron of metal–gate CMOS analog 1 1
switches. 16
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A. TSSOP–16 HC40
5xA
• Fast Switching and Propagation Speeds 16 DT SUFFIX
CASE 948F ALYW
• Low Crosstalk Between Switches 1
1
• Diode Protection on All Inputs/Outputs 16
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V SOEIAJ–16
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V 16
F SUFFIX 74HC405xA
ALYW
• Improved Linearity and Lower ON Resistance Than Metal–Gate 1
CASE 966
Counterparts 1
• Low Noise A = Assembly Location
• In Compliance With the Requirements of JEDEC Standard No. 7A WL = Wafer Lot
YY = Year
• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates WW = Work Week
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
See detailed ordering and shipping information in the package
dimensions section on page 67 of this data sheet.

March, 2000 – Rev. 1 MC74HC4051A/D
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE – MC74HC4051A

LOGIC DIAGRAM Control Inputs
MC74HC4051A Select
Single–Pole, 8–Position Plus Common Off Enable C B A ON Channels
13
L L L L X0
X0 L L L H X1
14
X1 L L H L X2
15 3 COMMON L L H H X3
X2 X
ANALOG 12 OUTPUT/ L H L L X4
INPUTS/ X3 MULTIPLEXER/ INPUT L H L H X5
OUTPUTS X4 1 DEMULTIPLEXER
L H H L X6
5
X5 L H H H X7
2 H X X X NONE
X6
4
X7 X = Don’t Care
11
A
CHANNEL 10
SELECT B Pinout: MC74HC4051A (Top View)
INPUTS 9 VCC X2 X1 X0 X3 A B C
C
6
ENABLE 16 15 14 13 12 11 10 9
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
1 2 3 4 5 6 7 8
X4 X6 X X7 X5 Enable VEE GND

MC74HC4052A
Select
Double–Pole, 4–Position Plus Common Off
Enable B A ON Channels
12
X0 L L L Y0 X0
14
X1 13 L L H Y1 X1
15 X SWITCH X
X2 L H L Y2 X2
11 L H H Y3 X3
X3
ANALOG COMMON H X X NONE
INPUTS/OUTPUTS 1 OUTPUTS/INPUTS
Y0 X = Don’t Care
5 3
Y1 Y SWITCH Y
2
Y2
4
Y3 Pinout: MC74HC4052A (Top View)
10
CHANNEL-SELECT A VCC X2 X1 X X0 X3 A B
9 PIN 16 = VCC
INPUTS B
PIN 7 = VEE 16 15 14 13 12 11 10 9
PIN 8 = GND
6
ENABLE
1 2 3 4 5 6 7 8
Y0 Y2 Y Y3 Y1 Enable VEE GND
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56

Control Inputs
LOGIC DIAGRAM
MC74HC4053A Select
Triple Single–Pole, Double–Position Plus Common Off Enable C B A ON Channels
L L L L Z0 Y0 X0
12 L L L H Z0 Y0 X1
X0 14
13 X SWITCH X L L H L Z0 Y1 X0
X1 L L H H Z0 Y1 X1
L H L L Z1 Y0 X0
2 L H L H Z1 Y0 X1
Y0 15 COMMON
ANALOG 1 Y SWITCH Y L H H L Z1 Y1 X0
INPUTS/OUTPUTS Y1 OUTPUTS/INPUTS
L H H H Z1 Y1 X1
H X X X NONE
5
Z0 4
3 Z SWITCH Z X = Don’t Care
Z1
11
A
CHANNEL-SELECT 10 PIN 16 = VCC
INPUTS B
9 PIN 7 = VEE Pinout: MC74HC4053A (Top View)
C PIN 8 = GND
6 VCC Y X X1 X0 A B C
ENABLE
16 15 14 13 12 11 10 9
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
1 2 3 4 5 6 7 8
Y1 Y0 Z1 Z Z0 Enable VEE GND
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
MAXIMUM RATINGS*
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Value Unit This device contains protection
circuitry to guard against damage
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
(Referenced to VEE) – 0.5 to + 14.0 due to high static voltages or electric
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
fields. However, precautions must
VEE Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V be taken to avoid applications of any
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
voltage higher than maximum rated
VIS Analog Input Voltage VEE – 0.5 to V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
voltages to this high–impedance cir-
VCC + 0.5
cuit. For proper operation, Vin and
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vout should be constrained to the
v v
Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
range GND (Vin or Vout) VCC.
I DC Current, Into or Out of Any Pin ± 25 mA Unused inputs must always be
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW tied to an appropriate logic voltage
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
EIAJ/SOIC Package† 500 level (e.g., either GND or VCC).
TSSOP Package† 450 Unused outputs must be left open.
ÎÎÎÎ
Tstg
ÎÎÎÎÎ
ÎÎÎ
Storage Temperature Range – 65 to + 150 _C
ÎÎÎÎ
TL
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur.
260
_C
Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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57
ÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS
ÎÎ
ÎÎÎ
Parameter Min Max Unit
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Referenced to VEE) 2.0 12.0
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage, Output (Referenced to – 6.0 GND V
GND)
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
Vin
ÎÎÎÎÎ
ÎÎÎ
Analog Input Voltage
ÎÎ
ÎÎÎ
Digital Input Voltage (Referenced to GND)
VEE
GND
VCC
VCC
V
V
ÎÎÎÎ
VIO*
ÎÎÎÎ ÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Static or Dynamic Voltage Across Switch
ÎÎ
ÎÎÎ
Operating Temperature Range, All Package Types – 55
1.2
+ 125
V
_C
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Input Rise/Fall Time
ÎÎÎ
VCC = 2.0 V 0 1000 ns
ÎÎ
(Channel Select or Enable Inputs) VCC = 3.0 V 0 600
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Ron = Per Spec 2.0 1.50 1.50 1.50 V
Voltage, Channel–Select or 3.0 2.10 2.10 2.10
Enable Inputs 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Ron = Per Spec 2.0 0.5 0.5 0.5 V
Enable Inputs 4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
Iin Maximum Input Leakage Current, Vin = VCC or GND, 6.0 ± 0.1 ± 1.0 ± 1.0 µA
Channel–Select or Enable Inputs VEE = – 6.0 V
ICC Maximum Quiescent Supply Channel Select, Enable and µA
Current (per Package) VIS = VCC or GND; VEE = GND 6.0 1 10 20
VIO = 0 V VEE = – 6.0 6.0 4 40 80
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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DC CHARACTERISTICS — Analog Section

Guaranteed Limit
Symbol Parameter Condition VCC VEE –55 to 25°C ≤85°C ≤125°C Unit
Ron Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to 4.5 0.0 190 240 280 Ω
VEE; IS ≤ 2.0 mA 4.5 – 4.5 120 150 170
(Figures 1, 2) 6.0 – 6.0 100 125 140
Vin = VIL or VIH; VIS = VCC or 4.5 0.0 150 190 230
VEE (Endpoints); IS ≤ 2.0 mA 4.5 – 4.5 100 125 140
(Figures 1, 2) 6.0 – 6.0 80 100 115
∆Ron Maximum Difference in “ON” Vin = VIL or VIH; 4.5 0.0 30 35 40 Ω
Resistance Between Any Two VIS = 1/2 (VCC – VEE); 4.5 – 4.5 12 15 18
Channels in the Same Package IS ≤ 2.0 mA 6.0 – 6.0 10 12 14
Ioff Maximum Off–Channel Leakage Vin = VIL or VIH; µA
Current, Any One Channel VIO = VCC – VEE; 6.0 – 6.0 0.1 0.5 1.0
Switch Off (Figure 3)
Maximum Off–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0
Leakage Current, HC4052A VIO = VCC – VEE; 6.0 – 6.0 0.1 1.0 2.0
Common Channel HC4053A Switch Off (Figure 4) 6.0 – 6.0 0.1 1.0 2.0
Ion Maximum On–Channel HC4051A Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0 µA
Leakage Current, HC4052A Switch–to–Switch = 6.0 – 6.0 0.1 1.0 2.0
Channel–to–Channel HC4053A VCC – VEE; (Figure 5) 6.0 – 6.0 0.1 1.0 2.0
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Channel–Select to Analog Output 2.0 270 320 350 ns
tPHL (Figure 9) 3.0 90 110 125
4.5 59 79 85
6.0 45 65 75
tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 40 60 70 ns
tPHL (Figure 10) 3.0 25 30 32
4.5 12 15 18
6.0 10 13 15
tPLZ, Maximum Propagation Delay, Enable to Analog Output 2.0 160 200 220 ns
tPHZ (Figure 11) 3.0 70 95 110
4.5 48 63 76
6.0 39 55 63
tPZL, Maximum Propagation Delay, Enable to Analog Output 2.0 245 315 345 ns
tPZH (Figure 11) 3.0 115 145 155
4.5 49 69 83
6.0 39 58 67
Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF
CI/O Maximum Capacitance Analog I/O 35 35 35 pF
(All Switches Off) Common O/I: HC4051A 130 130 130
HC4052A 80 80 80
HC4053A 50 50 50
Feedthrough 1.0 1.0 1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D)
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Figure 13)* HC4051A 45 pF
HC4052A 80
HC4053A 45
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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59
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Limit*
VCC VEE
Symbol Parameter Condition V V 25°C Unit
BW Maximum On–Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage to ‘51 ‘52 ‘53 MHz
or Minimum
Mi i Frequency
F Response
R Obt i 0dBm
Obtain 0dB att VOS; Increase
I fin
2.25 –2.25 80 95 120
(Figure 6) Frequency Until dB Meter Reads –3dB;
4.50 –4.50 80 95 120
RL = 50Ω, CL = 10pF
6.00 –6.00 80 95 120
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
(Figure 7) Obtain 0dBm at VIS 4.50 –4.50 –50
fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –40
4.50 –4.50 –40
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –40
— Feedthrough Noise. Vin ≤ 1MHz Square Wave (tr = tf = 6ns); 2.25 –2.25 25 mVPP
Channel–Select Input to Common Adjust RL at Setup so that IS = 0A; 4.50 –4.50 105
I/O (Figure 8) Enable = GND RL = 600Ω, CL = 50pF 6.00 –6.00 135
2.25 –2.25 35
4.50 –4.50 145
RL = 10kΩ, CL = 10pF 6.00 –6.00 190
— Crosstalk Between Any Two fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
Switches (Figure 12) Obtain 0dBm at VIS 4.50 –4.50 –50
(Test does not apply to HC4051A) fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –60
4.50 –4.50 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –60
THD Total Harmonic Distortion fin = 1kHz, RL = 10kΩ, CL = 50pF %
(Figure 14) THD = THDmeasured – THDsource
VIS = 4.0VPP sine wave 2.25 –2.25 0.10
VIS = 8.0VPP sine wave 4.50 –4.50 0.08
VIS = 11.0VPP sine wave 6.00 –6.00 0.05
*Limits not tested. Determined by design and verified by qualification.
300 180
160
250
Ron , ON RESISTANCE (OHMS)
140
200 120
125°C 125°C
100
150
25°C 80
25°C
– 55°C
100 60
40 – 55°C
50
20
0 0
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 3.0 V
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60
120 105
100 90

75 125°C
80
125°C
60
60 25°C
25°C 45
– 55°C
40
– 55°C 30
20 15
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Figure 1c. Typical On Resistance, VCC – VEE = 4.5 V Figure 1d. Typical On Resistance, VCC – VEE = 6.0 V
80 60
70
50
60 Ron , ON RESISTANCE (OHMS) 125°C
40
50 25°C
125°C
40 30
– 55°C
30 25°C
20
20 – 55°C
10
10
0 0
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 –6.0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 6.0
Figure 1e. Typical On Resistance, VCC – VEE = 9.0 V Figure 1f. Typical On Resistance, VCC – VEE = 12.0 V
PLOTTER
PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER
SUPPLY
– + VCC
DEVICE
UNDER TEST
ANALOG IN COMMON OUT
GND VEE
Figure 2. On Resistance Test Set–Up
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61
VCC VCC
VCC VCC
VEE 16 VEE 16
ANALOG I/O
OFF OFF
VCC A VCC
NC OFF COMMON O/I OFF COMMON O/I
VIH 6 VIH 6
7 7
8 8
VEE VEE
Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up Common Channel, Test Set–Up
VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
VEE N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O
VIL 6 6
7 7
8 8
VEE VEE
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current, Figure 6. Maximum On Channel Bandwidth,

Channel to Channel, Test Set–Up Test Set–Up
VIS VCC VOS VCC

0.1µF 16 dB 16
RL
fin OFF METER ON/OFF COMMON O/I
TEST
RL CL* RL ANALOG I/O
POINT
OFF/ON RL CL*
RL
6 6
7 7 VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 6 ns
VEE VCC VEE
CHANNEL SELECT CHANNEL SELECT
VIL or VIH GND
*Includes all probe and jig capacitance *Includes all probe and jig capacitance
Figure 7. Off Channel Feedthrough Isolation, Figure 8. Feedthrough Noise, Channel Select to
Test Set–Up Common Out, Test Set–Up
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VCC
VCC
16
VCC
CHANNEL ON/OFF COMMON O/I
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL
6
ANALOG 7
OUT 50%
8
CHANNEL SELECT
Figure 9a. Propagation Delays, Channel Select Figure 9b. Propagation Delay, Test Set–Up Channel
to Analog Out Select to Analog Out
VCC
16
ANALOG I/O COMMON O/I
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
7
ANALOG 8
OUT 50%
Figure 10a. Propagation Delays, Analog In Figure 10b. Propagation Delay, Test Set–Up
to Analog Out Analog In to Analog Out
tf tr POSITION 1 WHEN TESTING tPHZ AND tPZH

VCC 1 POSITION 2 WHEN TESTING tPLZ AND tPZL
90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG 7
OUT 50% 8
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to Figure 11b. Propagation Delay, Test Set–Up
Analog Out Enable to Analog Out
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63
VCC
VIS A
VCC
16 16
RL VOS
fin ON ON/OFF COMMON O/I
ANALOG I/O NC
0.1µF OFF/ON
OFF
VEE RL CL* RL CL* VCC
RL 6
7
6 VEE 8 11
7
8 CHANNEL SELECT
Figure 12. Crosstalk Between Any Two Figure 13. Power Dissipation Capacitance,
Switches, Test Set–Up Test Set–Up
0
VIS
VCC VOS – 10 FUNDAMENTAL FREQUENCY
0.1µF 16 – 20
TO
fin ON DISTORTION – 30
RL METER
CL* – 40
dB
– 50
DEVICE
– 60
6 SOURCE
– 70
7
8 – 80
VEE – 90
– 100
1.0 2.0 3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion
The Channel Select and Enable control pins should be at outputs to VCC or GND through a low value resistor helps
VCC or GND logic levels. VCC being recognized as a logic minimize crosstalk and feedthrough noise that may be
high and GND being recognized as a logic low. In this picked up by an unused switch.
example: Although used here, balanced supplies are not a
VCC = +5V = logic high requirement. The only constraints on the power supplies are
GND = 0V = logic low that:
The maximum analog voltage swings are determined by VCC – GND = 2 to 6 volts
the supply voltages VCC and VEE. The positive peak analog VEE – GND = 0 to –6 volts
voltage should not exceed VCC. Similarly, the negative peak VCC – VEE = 2 to 12 volts
analog voltage should not go below VEE. In this example, and VEE ≤ GND
the difference between VCC and VEE is ten volts. Therefore, When voltage transients above VCC and/or below VEE are
using the configuration of Figure 15, a maximum analog anticipated on the analog channels, external Germanium or
signal of ten volts peak–to–peak can be controlled. Unused Schottky diodes (Dx) are recommended as shown in Figure
analog inputs/outputs may be left floating (i.e., not 16. These diodes should be able to absorb the maximum
connected). However, tying unused analog inputs and anticipated current surges during clipping.
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VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
–5V SIGNAL SIGNAL –5V
Dx Dx
VEE VEE
6 11 TO EXTERNAL CMOS
7 10 CIRCUITRY 0 to 5V 7
8 9 DIGITAL SIGNALS 8
–5V VEE
Figure 15. Application Example Figure 16. External Germanium or

Schottky Clipping Diodes
+5V +5V
+5V 16 +5V +5V 16 +5V

ANALOG ANALOG ANALOG ANALOG
ON/OFF ON/OFF
VEE SIGNAL SIGNAL VEE VEE SIGNAL SIGNAL VEE
+5V
*
R R R +5V
6 11 6 11
LSTTL/NMOS LSTTL/NMOS
7 10 7 10
CIRCUITRY CIRCUITRY
8 9 8 9
VEE VEE
* 2K ≤ R ≤ 10K HCT
BUFFER
a. Using Pull–Up Resistors b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11 LEVEL 13
A X0
SHIFTER
14
X1
10 LEVEL 15
B X2
SHIFTER
12
X3
9 LEVEL 1
C X4
SHIFTER
5
X5
6 LEVEL 2
ENABLE X6
SHIFTER
4
X7
3
X
Figure 18. Function Diagram, HC4051A
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10 LEVEL 12
A X0
SHIFTER
14
X1
9 LEVEL 15
B X2
SHIFTER
11
X3
13
X
6 LEVEL 1
ENABLE Y0
SHIFTER
5
Y1
2
Y2
4
Y3
3
Y
11 LEVEL 13
A X1
SHIFTER
12
X0
14
X
10 LEVEL 1
B Y1
SHIFTER
2
Y0
15
Y
9 LEVEL 3
C Z1
SHIFTER
5
Z0
4
Z
6 LEVEL
ENABLE
SHIFTER
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ORDERING & SHIPPING INFORMATION

MC74HC4051AN PDIP–16 500 Units / Unit Pak
MC74HC4051AD SOIC–16 48 Units / Rail
MC74HC4051ADR2 SOIC–16 2500 Units / Tape & Reel
MC74HC4051ADT TSSOP–16 96 Units / Rail
MC74HC4051ADTR2 TSSOP–16 2500 Units / Tape & Reel
MC74HC4051ADW SOIC WIDE 48 Units / Rail
MC74HC4051ADWR2 SOIC WIDE 1000 Units / Tape & Reel
MC74HC4051AF SOEIAJ–16 See Note 1.
MC74HC4051AFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
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67
MC74HC4066A
Advance Information
Quad Analog Switch/
High–Performance Silicon–Gate CMOS
The MC74HC4066A utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
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OFF–channel leakage current. This bilateral switch/
multiplexer/demultiplexer controls analog and digital voltages that MARKING
may vary across the full power–supply range (from VCC to GND). DIAGRAMS
The HC4066A is identical in pinout to the metal–gate CMOS 14
MC14016 and MC14066. Each device has four independent switches. PDIP–14
N SUFFIX HC4066AN
The device has been designed so that the ON resistances (RON) are CASE 646 AWLYYWW
much more linear over input voltage than RON of metal–gate CMOS
1
analog switches. 14
The ON/OFF control inputs are compatible with standard CMOS SOIC–14
HC4066AD
outputs; with pullup resistors, they are compatible with LSTTL outputs. D SUFFIX
AWLYWW
For analog switches with voltage–level translators, see the HC4316A. CASE 751A
• Fast Switching and Propagation Speeds 1

14
• High ON/OFF Output Voltage Ratio HC40
TSSOP–14
• Low Crosstalk Between Switches DT SUFFIX 66A
• Diode Protection on All Inputs/Outputs CASE 948G ALYW
• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts 1

14
• Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts
SOEIAJ–14
• Improved Linearity and Lower ON Resistance over Input Voltage F SUFFIX 74HC4066A
than the MC14016 or MC14066 CASE 965 AWLYWW
• Low Noise 1
• Chip Complexity: 44 FETs or 11 Equivalent Gates A = Assembly Location
LOGIC DIAGRAM WL or L = Wafer Lot
YY or Y = Year
XA 1 2 Y WW or W = Work Week
A
PIN ASSIGNMENT
A ON/OFF CONTROL 13
XA 1 14 VCC
4 3 Y A ON/OFF
XB B YA 2 13 CONTROL
YB 3 12 D ON/OFF
B ON/OFF CONTROL 5 CONTROL
ANALOG XB 4 11 XD
XC 8 9 Y OUTPUTS/INPUTS B ON/OFF
C CONTROL 5 10 YD
6 C ON/OFF 6 9 YC
C ON/OFF CONTROL CONTROL
GND 7 8 XC
XD 11 10 Y
D
D ON/OFF CONTROL 12 ORDERING INFORMATION

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD Device Package Shipping
PIN 14 = VCC
MC74HC4066AN PDIP–14 2000 / Box
PIN 7 = GND
MC74HC4066AD SOIC–14 55 / Rail
FUNCTION TABLE MC74HC4066ADR2 SOIC–14 2500 / Reel
On/Off Control State of MC74HC4066ADT TSSOP–14 96 / Rail
Input Analog Switch
MC74HC4066ADTR2 TSSOP–14 2500 / Reel
L Off
H On
1. For ordering information on the EIAJ version of the
This document contains information on a new product. Specifications and information
SOIC packages, please contact your local ON
herein are subject to change without notice.
Semiconductor representative.

MC74HC4066A
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
Parameter Value Unit This device contains protection
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 14.0 V circuitry to guard against damage
due to high static voltages or electric
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current Into or Out of Any Pin ± 25 mA voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW cuit. For proper operation, Vin and
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
EIAJ/SOIC Package† 500
TSSOP Package† 450 range GND (Vin or Vout) VCC.
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
Tstg Storage Temperature – 65 to + 150 _C tied to an appropriate logic voltage
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
level (e.g., either GND or VCC).
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Unused outputs must be left open.
(Plastic DIP, SOIC or TSSOP Package) 260
I/O pins must be connected to a
*Maximum Ratings are those values beyond which damage to the device may occur. properly terminated line or bus.
ÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage (Referenced to GND) GND VCC V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Referenced to GND) GND VCC V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIO* Static or Dynamic Voltage Across Switch — 1.2 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
tr, tf Input Rise and Fall Time, ON/OFF Control ns
Inputs (Figure 10) VCC = 2.0 V 0 1000
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
VCC = 3.0 V 0 600
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
VCC = 4.5 V 0 500
VCC = 9.0 V 0 400
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 12.0 V 0 250
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
exceeded.
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to
ÎÎÎÎ
Symbol
ÎÎÎÎ ÎÎÎÎÎÎÎÎ
VIH ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter
ÎÎÎ
Minimum High–Level Voltage
Test Conditions
Ron = Per Spec
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ON/OFF Control Inputs 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
9.0 6.3 6.3 6.3
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 8.4 8.4 8.4
VIL Maximum Low–Level Voltage Ron = Per Spec 2.0 0.5 0.5 0.5 V
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ON/OFF Control Inputs
ÎÎÎ
3.0
4.5
9.0
0.9
1.35
2.7
0.9
1.35
2.7
0.9
1.35
2.7
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 3.6 3.6 3.6
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 12.0 ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 2 20 40 µA
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current (per Package) VIO = 0 V 12.0 4 40
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
160
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69
MC74HC4066A
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions Unit
Ron Maximum “ON” Resistance Vin = VIH 2.0† — — — Ω
ÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VIS = VCC to GND
IS 2.0 mA (Figures 1, 2)
3.0†
4.5
9.0
—
120
70
—
160
85
—
200
100
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 70 85 100
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH 2.0 — — —
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIS = VCC or GND (Endpoints) 3.0 — — —
v IS 2.0 mA (Figures 1, 2) 4.5 70 85 100
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
9.0 50 60 80
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 30 60 80
∆Ron Ω
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Difference in “ON” Vin = VIH 2.0 — — —
Resistance Between Any Two VIS = 1/2 (VCC – GND) 4.5 20 25 30
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Channels in the Same Package IS 2.0 mA 9.0 15 20 25
12.0 15 20 25
ÎÎÎÎ
ÎÎÎÎ
Ioff
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Off–Channel Leakage
ÎÎÎ
Current, Any One Channel
Vin = VIL
VIO = VCC or GND
12.0 0.1 0.5 1.0 µA
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Ion Maximum On–Channel Leakage Vin = VIH 12.0 0.1 0.5 1.0 µA
Current, Any One Channel VIS = VCC or GND
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 4)
†At supply voltage (VCC) approaching 3 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
operation, it is recommended that these devices only be used to control digital signals.
(DL129/D).
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Unit
ÎÎÎÎÎ
tPHL
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figures 8 and 9)
ÎÎÎ
3.0
4.5
9.0
30
5
5
40
7
7
50
8
8
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
tPLZ, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, ON/OFF Control to Analog Output
12.0
2.0
5
80
7
90
8
110 ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHZ (Figures 10 and 11) 3.0 60 70 80
4.5 20 25 35
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
9.0 20 25 35
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
12.0 20 25 35
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, ON/OFF Control to Analog Output 2.0 80 90 100 ns
tPZH (Figures 10 and 1 1) 3.0 45 50 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 20 25 30
9.0 20 25 30
ÎÎÎÎÎ
ÎÎÎÎÎ C ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Capacitance ON/OFF Control Input
12.0
—
20
10
25
10
30
10 pF
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Control Input = GND
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Analog I/O — 35 35 35
Feedthrough — 1.0 1.0 1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pF
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70
MC74HC4066A
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Limit*
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
VCC 25_C
Symbol Parameter Test Conditions V 54/74HC Unit
ÎÎÎÎ
ÎÎÎÎ
BW
or ÎÎÎÎ
ÎÎÎ ÎÎÎ
Maximum On–Channel Bandwidth
ÎÎÎÎ
ÎÎÎ
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
4.5
9.0
150
160
MHz
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Minimum Frequency Response Increase fin Frequency Until dB Meter Reads – 3 dB 12.0 160
(Figure 5) RL = 50 Ω, CL = 10 pF
ÎÎÎÎ
ÎÎÎÎ
—

ÎÎÎ
(Figure 6) ÎÎÎÎ
ÎÎÎ ÎÎÎ
Off–Channel Feedthrough Isolation
ÎÎÎÎ
ÎÎÎ
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
4.5
9.0
– 50
– 50
dB
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
12.0 – 50
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
4.5 – 40
9.0 – 40
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
12.0 – 40
v
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
— Feedthrough Noise, Control to Vin 1 MHz Square Wave (tr = tf = 6 ns) 4.5 60 mVPP
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Switch Adjust RL at Setup so that IS = 0 A 9.0 130
(Figure 7) RL = 600 Ω, CL = 50 pF 12.0 200
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
RL = 10 kΩ, CL = 10 pF 4.5
9.0
12.0
30
65
100
ÎÎÎÎ
ÎÎÎÎ
—

Switches ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Crosstalk Between Any Two fin Sine Wave
4.5
9.0
– 70
– 70
dB
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 12) fin = 10 kHz, RL = 600 Ω, CL = 50 pF 12.0 – 70
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 80
9.0 – 80
ÎÎÎÎ
THD ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Total Harmonic Distortion fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
12.0 – 80
%
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 14) THD = THDMeasured – THDSource
VIS = 4.0 VPP sine wave 4.5 0.10
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
*Guaranteed limits not tested. Determined by design and verified by qualification.
9.0
12.0
0.06
0.04
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71
MC74HC4066A
TBD TBD
Figure 1a. Typical On Resistance, VCC = 2.0 V Figure 1b. Typical On Resistance, VCC = 4.5 V
TBD TBD
Figure 1c. Typical On Resistance, VCC = 6.0 V Figure 1d. Typical On Resistance, VCC = 9.0 V
PLOTTER
PROGRAMMABLE
TBD SUPPLY
– + VCC
DEVICE
UNDER TEST
GND
Figure 1e. Typical On Resistance, VCC = 12 V Figure 2. On Resistance Test Set–Up
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72
MC74HC4066A
VCC
VCC VCC
GND 14 VCC 14
A ON N/C
VCC A OFF GND
SELECTED VIL SELECTED VIH

CONTROL CONTROL
7 INPUT 7 INPUT
Figure 3. Maximum Off Channel Leakage Current, Figure 4. Maximum On Channel Leakage Current,
Any One Channel, Test Set–Up Test Set–Up
VCC VOS VIS VCC VOS

14 14
fin ON fin OFF
dB dB
0.1µF CL* 0.1µF CL*
METER RL METER
SELECTED
CONTROL
SELECTED VCC INPUT
CONTROL
7 INPUT 7
*Includes all probe and jig capacitance. *Includes all probe and jig capacitance.
Figure 5. Maximum On–Channel Bandwidth Figure 6. Off–Channel Feedthrough Isolation,

Test Set–Up Test Set–Up
VCC/2 VCC VCC/2
14
RL RL
VOS
OFF/ON IS
VCC
CL*
50%
SELECTED ANALOG IN
CONTROL GND
Vin ≤ 1 MHz 7 INPUT tPLH tPHL
tr = tf = 6 ns
VCC
GND CONTROL
50%
ANALOG OUT
*Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to Figure 8. Propagation Delays, Analog In to

Analog Out, Test Set–Up Analog Out
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73
MC74HC4066A
VCC tr tf
14 VCC
90%
ANALOG IN ANALOG OUT TEST CONTROL 50%
ON POINT 10% GND
CL*
tPZL tPLZ
HIGH
IMPEDANCE
SELECTED VCC 50%
10% VOL
CONTROL
7 ANALOG
INPUT tPZH tPHZ
OUT
90% VOH
50%
*Includes all probe and jig capacitance. HIGH
IMPEDANCE
Figure 9. Propagation Delay Test Set–Up Figure 10. Propagation Delay, ON/OFF Control
to Analog Out
POSITION 1 WHEN TESTING tPHZ AND tPZH VIS

POSITION 2 WHEN TESTING tPLZ AND tPZL VCC
1
14
RL VOS
2
VCC fin ON
VCC 14 1 kΩ 0.1 µF
1
TEST OFF
ON/OFF POINT
2 VCC OR GND
CL* RL CL* RL CL*
RL
SELECTED
SELECTED
CONTROL VCC/2 VCC/2
CONTROL
INPUT
INPUT
7
7
VCC/2
Figure 11. Propagation Delay Test Set–Up Figure 12. Crosstalk Between Any Two Switches,
Test Set–Up
VCC
A
VIS
14 VCC VOS
0.1 µF TO
N/C OFF/ON N/C fin ON DISTORTION
CL* METER
RL
SELECTED VCC/2
7 CONTROL SELECTED VCC
INPUT CONTROL
7
INPUT
ON/OFF CONTROL
Figure 13. Power Dissipation Capacitance Figure 14. Total Harmonic Distortion, Test Set–Up
Test Set–Up
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74
MC74HC4066A
0
– 10 FUNDAMENTAL FREQUENCY
– 20
– 30
– 40
dBm
– 50
DEVICE
– 60
SOURCE
– 70
– 80
– 90
1.0 2.0 3.0

FREQUENCY (kHz)
Figure 15. Plot, Harmonic Distortion
APPLICATION INFORMATION below, the difference between VCC and GND is twelve volts.
Therefore, using the configuration in Figure 16, a maximum
The ON/OFF Control pins should be at VCC or GND logic analog signal of twelve volts peak–to–peak can be
levels, VCC being recognized as logic high and GND being controlled.
recognized as a logic low. Unused analog inputs/outputs When voltage transients above VCC and/or below GND
may be left floating (not connected). However, it is are anticipated on the analog channels, external diodes (Dx)
advisable to tie unused analog inputs and outputs to VCC or are recommended as shown in Figure 17. These diodes
GND through a low value resistor. This minimizes crosstalk should be small signal, fast turn–on types able to absorb the
and feedthrough noise that may be picked–up by the unused maximum anticipated current surges during clipping. An
I/O pins. alternate method would be to replace the Dx diodes with
The maximum analog voltage swings are determined by Mosorbs (Mosorb is an acronym for high current surge
the supply voltages VCC and GND. The positive peak analog protectors). Mosorbs are fast turn–on devices ideally suited
voltage should not exceed VCC. Similarly, the negative peak for precise DC protection with no inherent wear out
analog voltage should not go below GND. In the example mechanism.
VCC VCC
VCC = 12 V
14 Dx 16 Dx
+ 12 V + 12 V
ANALOG I/O ANALOG O/I
ON ON
0V 0V
Dx Dx
SELECTED SELECTED
VCC
CONTROL CONTROL
OTHER CONTROL OTHER CONTROL
INPUT INPUT
INPUTS INPUTS
7 (VCC OR GND) 7 (VCC OR GND)
Figure 16. 12 V Application Figure 17. Transient Suppressor Application
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75
MC74HC4066A
+5 V +5 V
ANALOG 14 ANALOG ANALOG 14 ANALOG

SIGNALS SIGNALS SIGNALS SIGNALS
R* R* R* R* HC4066A HCT HC4066A

LSTTL/ LSTTL/ BUFFER
NMOS 5 NMOS 5
6 CONTROL 6 CONTROL
14 INPUTS 14 INPUTS
15 15
7 7
R* = 2 TO 10 kΩ
a. Using Pull-Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface
VDD = 5 V VCC = 5 TO 12 V
13 1 16 ANALOG 14 ANALOG
3 SIGNALS SIGNALS
5 HC4066A
7 MC14504 2 5
9 4 6 CONTROL
11 6 14 INPUTS
14 8 10 15 7
Figure 19. TTL/NMOS–to–CMOS Level Converter

Analog Signal Peak–to–Peak Greater than 5 V
(Also see HC4316A)
1 OF 4
CHANNEL 4
SWITCHES
1 OF 4
CHANNEL 3
SWITCHES
COMMON I/O
1 OF 4
CHANNEL 2
SWITCHES
–
1 OF 4 OUTPUT
CHANNEL 1 1 OF 4
SWITCHES INPUT + LF356 OR
SWITCHES
EQUIVALENT
0.01 µF
1 2 3 4
CONTROL INPUTS
Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier
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76
MC74HC4316A
Product Preview
Quad Analog Switch/
with Separate Analog and
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Digital Power Supplies
High–Performance Silicon–Gate CMOS MARKING
DIAGRAMS
The MC74HC4316A utilizes silicon–gate CMOS technology to 16
achieve fast propagation delays, low ON resistances, and low PDIP–16
OFF–channel leakage current. This bilateral switch/multiplexer/ P SUFFIX HC4316AN
CASE 648 AWLYYWW
demultiplexer controls analog and digital voltages that may vary
across the full analog power–supply range (from VCC to VEE). 1
The HC4316A is similar in function to the metal–gate CMOS 16
MC14016 and MC14066, and to the High–Speed CMOS HC4066A. SOIC–16
HC4316AD
Each device has four independent switches. The device control and D SUFFIX
AWLYWW
Enable inputs are compatible with standard CMOS outputs; with CASE 751B
pullup resistors, they are compatible with LSTTL outputs. The device 1
has been designed so that the ON resistances (RON) are much more 16
linear over input voltage than RON of metal–gate CMOS analog TSSOP–16 HC43
switches. Logic–level translators are provided so that the On/Off DT SUFFIX 16A
Control and Enable logic–level voltages need only be VCC and GND, CASE 948F ALYW
while the switch is passing signals ranging between VCC and VEE. 1
When the Enable pin (active–low) is high, all four analog switches are
16
turned off.
SOEIAJ–16
• Logic–Level Translator for On/Off Control and Enable Inputs F SUFFIX 74HC4316A
AWLYWW
• Fast Switching and Propagation Speeds CASE 966
• High ON/OFF Output Voltage Ratio 1
• Diode Protection on All Inputs/Outputs A = Assembly Location

• Analog Power–Supply Voltage Range (VCC – VEE) = 2.0 to 12.0
WL or L = Wafer Lot
YY or Y = Year
Volts WW or W = Work Week
• Digital (Control) Power–Supply Voltage Range (VCC – GND) = 2.0
to 6.0 Volts, Independent of VEE ORDERING INFORMATION
• Improved Linearity of ON Resistance Device Package Shipping
• Chip Complexity: 66 FETs or 16.5 Equivalent Gates MC74HC4316AN PDIP–16 2000 / Box
MC74HC4316AD SOIC–16 48 / Rail
PIN ASSIGNMENT
MC74HC4316ADR2 SOIC–16 2500 / Reel
XA 1 16 VCC
MC74HC4316ADT TSSOP–16 96 / Rail
YA 2 15 A ON/OFF
CONTROL MC74HC4316ADTR2 TSSOP–16 2500 / Reel
YB 3 14 D ON/OFF FUNCTION TABLE
CONTROL MC74HC4316AF SOEIAJ–14 See Note 1.
XD Inputs State of
XB 4 13 1. For ordering information on the EIAJ version of
B ON/OFF On/Off Analog
5 12 YD the SOIC packages, please contact your local
CONTROL Enable Control Switch ON Semiconductor representative.
C ON/OFF 6 11 YC L H On
CONTROL
L L Off
ENABLE 7 10 XC
H X Off
GND 8 9 VEE
X = don’t care
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.

MC74HC4316A
LOGIC DIAGRAM
1 ANALOG 2
XA YA
SWITCH
15
A ON/OFF CONTROL LEVEL
TRANSLATOR
4 ANALOG 3
XB YB
SWITCH
5 ANALOG
B ON/OFF CONTROL LEVEL
TRANSLATOR OUTPUTS/INPUTS
10 ANALOG 11
XC YC PIN 16 = VCC
SWITCH
6 PIN 8 = GND
C ON/OFF CONTROL LEVEL PIN 9 = VEE
TRANSLATOR GND ≥ VEE
13 ANALOG 12
XD YD
SWITCH
14
D ON/OFF CONTROL LEVEL
7 TRANSLATOR
ENABLE
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ Parameter Value Unit This device contains protection
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Ref. to GND) – 0.5 to + 7.0 V circuitry to guard against damage
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Ref. to VEE) – 0.5 to + 14.0 due to high static voltages or electric
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage (Ref. to GND) – 7.0 to + 0.5 V
be taken to avoid applications of any
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage VEE – 0.5 V voltage higher than maximum rated
to VCC + 0.5 voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Ref. to GND) – 0.5 to VCC + 0.5 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current Into or Out of Any Pin ± 25 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air Plastic DIP† 750 mW
tied to an appropriate logic voltage
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
EIAJ/SOIC Package† 500
TSSOP Package† 450 level (e.g., either GND or VCC).
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C I/O pins must be connected to a
ÎÎÎÎ
TL
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Plastic DIP, SOIC or TSSOP Package) 260
_C properly terminated line or bus.

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78
MC74HC4316A
ÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC Positive DC Supply Voltage (Ref. to GND) 2.0 6.0 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage (Ref. to GND) – 6.0 GND V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage VEE VCC V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Ref. to GND) GND VCC V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIO* Static or Dynamic Voltage Across Switch — 1.2 V
_C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Control or Enable Inputs) VCC = 3.0 V 0 600
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Figure 10) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
exceeded.
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIH Minimum High–Level Voltage, Ron = Per Spec 2.0 1.5 1.5 1.5 V
Control or Enable Inputs 3.0 2.1 2.1 2.1
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Voltage,
ÎÎÎ
Control or Enable Inputs
Ron = Per Spec 2.0
3.0
0.5
0.9
0.5
0.9
0.5
0.9
V
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Inputs
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Current, Control or Enable
Vin = VCC or GND
VEE = – 6.0 V
6.0 ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
Current (per Package)
Vin = VCC or GND
VIO = 0 V VEE = GND
VEE = – 6.0
6.0
6.0
2
4
20
40
40
160
µA
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79
MC74HC4316A
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VCC VEE – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V V 25_C 85_C 125_C Unit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Ron Maximum “ON” Resistance Vin = VIH 2.0* 0.0 — — — Ω
VIS = VCC to VEE 45 0.0 160 200 240
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
IS 2.0 mA (Figures 1, 2) 4.5 – 4.5 90 110 130
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 – 6.0 90 110 130
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH 2.0 0.0 — — —
VIS = VCC or VEE (Endpoints) 4.5 0.0 90 115 140
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
IS 2.0 mA (Figures 1, 2) 4.5 – 4.5 70 90 105
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 – 6.0 70 90 105
∆Ron Ω
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Difference in “ON” Vin = VIH 2.0 0.0 — — —
Resistance Between Any Two VIS = 1/2 (VCC – VEE) 4.5 0.0 20 25 30
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Channels in the Same Package IS 2.0 mA 4.5 – 4.5 15 20 25
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 – 6.0 15 20 25
µA
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Ioff Maximum Off–Channel Vin = VIL 6.0 – 6.0 0.1 0.5 1.0
Leakage Current, Any One VIO = VCC or VEE
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Channel Switch Off (Figure 3)
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Ion Maximum On–Channel Vin = VIH 6.0 – 6.0 0.1 0.5 1.0 µA
Leakage Current, Any One VIS = VCC or VEE
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Channel
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ (Figure 4)
*At supply voltage (VCC – VEE) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
(DL129/D).
ÎÎÎÎÎ
ÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
Symbol Parameter V 25_C 85_C 125_C Unit
ÎÎÎÎÎ
tPLH,
ÎÎÎÎÎ ÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Analog Input to Analog Output
ÎÎÎ
(Figures 8 and 9)
2.0
4.5
40
6
50
8
60
9
ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 5 7 8
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPLZ, Maximum Propagation Delay, Control or Enable to Analog Output 2.0 130 160 200 ns
tPHZ (Figures 10 and 11) 4.5 40 50 60
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
6.0 30 40 50
ÎÎÎÎÎ
tPZL,
ÎÎÎÎÎ ÎÎÎÎ
tPZH
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Propagation Delay, Control or Enable to Analog Output
ÎÎÎ
(Figures 10 and 11)
2.0
4.5
6.0
140
40
30
175
50
40
250
60
50
ns
ÎÎÎÎÎ
ÎÎÎÎÎ
C
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Capacitance
ÎÎÎ
ON/OFF Control
and Enable Inputs
— 10 10 10 pF
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Control Input = GND
Analog I/O
Feedthrough
—
—
35
1.0
35
1.0
35
1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

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80
MC74HC4316A
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VCC VEE Limit*
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V V 25_C Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
BW Maximum On–Channel Bandwidth or fin = 1 MHz Sine Wave 2.25 – 2.25 150 MHz
Minimum Frequency Response Adjust fin Voltage to Obtain 0 dBm at VOS 4.50 – 4.50 160
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 5) Increase fin Frequency Until dB Meter 6.00 – 6.00 160
RL = 50 Ω, CL = 10 pF
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Reads – 3 dB

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— Off–Channel Feedthrough Isolation fin Sine Wave 2.25 – 2.25 – 50 dB
(Figure 6) Adjust fin Voltage to Obtain 0 dBm at VIS 4.50 – 4.50 – 50
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
fin = 10 kHz, RL = 600 Ω, CL = 50 pF 6.00 – 6.00 – 50
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 2.25 – 2.25 – 40
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.50 – 4.50 – 40
6.00 – 6.00 – 40
ÎÎÎÎ
ÎÎÎÎ
—
v
ÎÎÎÎ
Switch ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Feedthrough Noise, Control to
ÎÎÎ
ÎÎÎ
Vin 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 Ω, CL = 50 pF
2.25
4.50
– 2.25
– 4.50
60
130
mVPP
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(Figure 7) 6.00 – 6.00 200
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
RL = 10 kΩ, CL = 10 pF 2.25 – 2.25 30
4.50 – 4.50 65
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.00 – 6.00 100

ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— Crosstalk Between Any Two fin Sine Wave 2.25 – 2.25 – 70 dB
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Switches Adjust fin Voltage to Obtain 0 dBm at VIS 4.50 – 4.50 – 70
(Figure 12) fin = 10 kHz, RL = 600 Ω, CL = 50 pF 6.00 – 6.00 – 70
ÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 80
– 80
– 80
ÎÎÎÎ
ÎÎÎÎ
THD
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Total Harmonic Distortion
(Figure 14)
fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
THD = THDMeasured – THDSource
%
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIS = 4.0 VPP sine wave 2.25 – 2.25 0.10
VIS = 8.0 VPP sine wave 4.50 – 4.50 0.06
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
VIS = 11.0 VPP sine wave 6.00 – 6.00 0.04
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81
MC74HC4316A
TBD TBD
Figure 1a. Typical On Resistance, Figure 1b. Typical On Resistance,

VCC – VEE = 2.0 V VCC – VEE = 4.5 V
TBD TBD
Figure 1c. Typical On Resistance, Figure 1d. Typical On Resistance,

VCC – VEE = 6.0 V VCC – VEE = 9.0 V
PLOTTER
PROGRAMMABLE
SUPPLY
TBD
– + VCC
DEVICE
UNDER TEST
GND VEE
Figure 1e. Typical On Resistance, Figure 2. On Resistance Test Set–Up

VCC – VEE = 12.0 V
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82
MC74HC4316A
VCC
VCC VCC
VEE 16 VCC 16
A ON N/C
VCC A OFF
O/I
VEE
VIL VIH
7 SELECTED 7 SELECTED
8 CONTROL 8 CONTROL
9 INPUT 9 INPUT
VEE VEE
VIS
VCC VCC VCC
16 RL 16
TO dB TO dB
fin ON fin OFF
METER METER
0.1 µF RL CL* 0.1 µF RL RL CL*
VCC
7 7
SELECTED SELECTED
8 8
CONTROL CONTROL
9 9
INPUT INPUT
VEE VEE

VCC
16
TEST
ON/OFF POINT VCC
RL
RL CL*
7 50%
8 ANALOG IN
9 SELECTED GND
CONTROL tPLH tPHL
VEE INPUT
CONTROL 50%
ANALOG OUT
Figure 7. Feedthrough Noise, Control to Analog Out, Figure 8. Propagation Delays, Analog In to
Test Set–Up Analog Out
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83
MC74HC4316A
VCC
16 tr tf
ANALOG I/O ANALOG O/I TEST ENABLE VCC
ON POINT 50%
50 pF* CONTROL GND
tPZL tPLZ
HIGH
7 SELECTED VCC IMPEDANCE
8 50%
CONTROL 10% VOL
9 ANALOG
INPUT tPZH tPHZ
OUT 90% VOH
50%
HIGH
*Includes all probe and jig capacitance. IMPEDANCE
to Analog Out
VIS
POSITION 1 WHEN TESTING tPHZ AND tPZH
1 POSITION 2 WHEN TESTING tPLZ AND tPZL
VCC
RL
2 fin 16
VCC RL
VCC 1 kΩ 0.1 µF ON
16
1 CL*
TEST ANALOG I/O
ON/OFF POINT
2
50 pF* TEST
OFF POINT
CONTROL RL CL*
OR 7
8 VCC
ENABLE
9 SELECTED
8 CONTROL
9 VEE INPUT
Test Set–Up (Adjacent Channels Used)
VCC
A
VIS
16 VCC VOS
10 µF 16
TO
N/C ON/OFF N/C fin ON DISTORTION
RL CL* METER
7
8 SELECTED
7
9 CONTROL SELECTED
8 VCC
INPUT CONTROL
VEE 9
INPUT
VEE
CONTROL
Test Set–Up
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84
MC74HC4316A
0
– 20
– 30
– 40
dBm
– 50
DEVICE
– 60
SOURCE
– 70
– 80
– 90
– 100
1.0 2.0 3.0
FREQUENCY (kHz)
The Enable and Control pins should be at VCC or GND Therefore, using the configuration in Figure 16, a maximum
logic levels, VCC being recognized as logic high and GND analog signal of twelve volts peak–to–peak can be
being recognized as a logic low. Unused analog controlled.
inputs/outputs may be left floating (not connected). When voltage transients above VCC and/or below VEE are
However, it is advisable to tie unused analog inputs and anticipated on the analog channels, external diodes (Dx) are
outputs to VCC or VEE through a low value resistor. This recommended as shown in Figure 17. These diodes should
minimizes crosstalk and feedthrough noise that may be be small signal, fast turn–on types able to absorb the
picked up by the unused I/O pins. maximum anticipated current surges during clipping. An
The maximum analog voltage swings are determined by alternate method would be to replace the Dx diodes with
the supply voltages VCC and VEE. The positive peak analog Mosorbs (Mosorb is an acronym for high current surge
voltage should not exceed VCC. Similarly, the negative peak protectors). Mosorbs are fast turn–on devices ideally suited
analog voltage should not go below VEE. In the example for precise dc protection with no inherent wear out
below, the difference between VCC and VEE is twelve volts. mechanism.
VCC VCC
VCC = 6 V
16 Dx 16 Dx
+6V +6V
ON ON
–6 V –6 V VCC
Dx SELECTED Dx
+6V SELECTED CONTROL VEE
CONTROL INPUT
VEE
INPUT
ENABLE CONTROL VEE ENABLE CONTROL
VEE INPUTS INPUTS
8 (VCC OR GND) (VCC OR GND)
–6 V
Figure 16. Figure 17. Transient Suppressor Application
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85
MC74HC4316A
VCC = 5 V +5 V

R* R* R* R* R*
HC4316A HCT HC4016A
VEE = 0 VEE = 0
BUFFER
TO – 6 V TO – 6 V
7 5
TTL ENABLE LSTTL/
5 AND NMOS 6 CONTROL
6 CONTROL 9 14 INPUTS 9
14 INPUTS
15 15
8 7
R* = 2 TO 10 kΩ
a. Using Pull–Up Resistors b. Using HCT Buffer
Figure 18. LSTTL/NMOS to HCMOS Interface
VCC = 12 V
12 V R1
POWER GND = 6 V
SUPPLY
R2
VEE = 0 V
R1 = R2
VCC
ANALOG ANALOG
INPUT R3 OUTPUT
SIGNAL 1 OF 4 SIGNAL 12 V
12 VPP
SWITCHES 0
C R4
R1 = R2
R3 = R4
VEE
Figure 19. Switching a 0–to–12 V Signal Using a

Single Power Supply (GND ≠ 0 V)
1 OF 4
CHANNEL 4
SWITCHES
1 OF 4
CHANNEL 3
SWITCHES
COMMON I/O
1 OF 4
CHANNEL 2
SWITCHES
–
1 OF 4 OUTPUT
CHANNEL 1 1 OF 4
SWITCHES
EQUIVALENT
0.01 µF
1 2 3 4
CONTROL INPUTS
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86
MC74HC4851A,
MC74HC4852A
Analog Multiplexers/
Demultiplexers with
Injection Current Effect
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Control
Automotive Customized MARKING
DIAGRAMS
These devices are pin compatible to standard HC405x and 16
MC1405xB analog mux/demux devices, but feature injection current PDIP–16
effect control. This makes them especially suited for usage in N SUFFIX HC485xAN
AWLYYWW
automotive applications where voltages in excess of normal logic CASE 648
voltage are common. 1
The injection current effect control allows signals at disabled analog 16
input channels to exceed the supply voltage range without affecting SOIC–16
HC485xAD
the signal of the enabled analog channel. This eliminates the need for D SUFFIX AWLYWW
external diode/ resistor networks typically used to keep the analog CASE 751B
channel signals within the supply voltage range. 1
The devices utilize low power silicon gate CMOS technology. The 16
Channel Select and Enable inputs are compatible with standard CMOS SOIC–16 WIDE
HC485xADW
outputs. DW SUFFIX AWLYWW
• Injection Current Cross–Coupling Less than 1mV/mA (See Figure 9) CASE 751G
• Pin Compatible to HC405X and MC1405XB Devices 1
• Power Supply Range (VCC – GND) = 2.0 to 6.0 V 16
• In Compliance With the Requirements of JEDEC Standard No. 7A TSSOP–16 HC48

DT SUFFIX
• Chip Complexity: 154 FETs or 36 Equivalent Gates CASE 948F
5xA
ALYW
1
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC74HC4851A, MC74HC4852A

Control Inputs
Select
13
X0 Enable C B A ON Channels
14
X1 L L L L X0
15
X2 L L L H X1
ANALOG 12 L L H L X2
INPUTS/ X3 MULTIPLEXER/ 3 COMMON
OUTPUTS X4 1 DEMULTIPLEXER X L L H H X3
OUTPUT/
5 INPUT L H L L X4
X5 L H L H X5
2
X6 L H H L X6
4
X7 L H H H X7
11 H X X X NONE
A
CHANNEL 10
SELECT B
INPUTS 9
C VCC X2 X1 X0 X3 A B C
6
ENABLE 16 15 14 13 12 11 10 9
PIN 16 = VCC
PIN 8 = GND
Figure 1. MC74HC4851A Logic Diagram

Single–Pole, 8–Position Plus Common Off
1 2 3 4 5 6 7 8
X4 X6 X X7 X5 Enable NC GND
Figure 2. MC74HC4851A 16–Lead Pinout (Top View)

Control Inputs
Select
12
X0 L L L Y0 X0
14
X1 13 L L H Y1 X1
15 X SWITCH X
X2 L H L Y2 X2
11 L H H Y3 X3
X3
Y0 X = Don’t Care
5 3
Y1 Y SWITCH Y
2
Y2
4
Y3 VCC X2 X1 X X0 X3 A B
10
CHANNEL-SELECT A 16 15 14 13 12 11 10 9
9 PIN 16 = VCC
INPUTS B
PIN 8 = GND
6
ENABLE
Figure 3. MC74HC4852A Logic Diagram

1 2 3 4 5 6 7 8
Y0 Y2 Y Y3 Y1 Enable NC GND
Figure 4. MC74HC4852A 16–Lead Pinout (Top View)
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88
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Any Pin) (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current, Into or Out of Any Pin ± 25 mA
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, Plastic DIP† 750 mW voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
SOIC Package† 500 cuit. For proper operation, Vin and
TSSOP Package† 450 Vout should be constrained to the
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C tied to an appropriate logic voltage
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Plastic DIP, SOIC or TSSOP Package 260 level (e.g., either GND or VCC).
SOIC Package: – 7 mW/_C from 65_ to 125_C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Symbol Parameter Min Max Unit
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin DC Input Voltage (Any Pin) (Referenced to GND) GND VCC V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIO* Static or Dynamic Voltage Across Switch 0.0 1.2 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature Range, All Package Types – 55 + 125 _C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise/Fall Time VCC = 2.0 V 0 1000 ns
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 6.0 V 0 400
Guaranteed Limit
VCC
Voltage, Channel–Select or Enable 3.0 2.10 2.10 2.10
Inputs 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
Voltage, Channel–Select or Enable 3.0 0.90 0.90 0.90
Inputs 4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA
on Digital Pins (Enable/A/B/C)
ICC Maximum Quiescent Supply Vin(digital) = VCC or GND 6.0 2 20 40 µA
Current (per Package) Vin(analog) = GND
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89
DC CHARACTERISTICS — Analog Section

Guaranteed Limit
Symbol Parameter Condition VCC –55 to 25°C ≤85°C ≤125°C Unit
Ron Maximum “ON” Resistance Vin = VIL or VIH;VIS = VCC to 2.0 1700 1750 1800 Ω
GND; IS ≤ 2.0 mA 3.0 1100 1200 1300
4.5 550 650 750
6.0 400 500 600
∆Ron Delta “ON” Resistance Vin = VIL or VIH; VIS = VCC/2 2.0 300 400 500 Ω
IS ≤ 2.0 mA 3.0 160 200 240
4.5 80 100 120
6.0 60 80 100
Ioff Maximum Off–Channel Leakage Vin = VCC or GND µA
Current, 6.0 ±0.1 ±0.5 ±1.0
Any One Channel ±0.2 ±2.0 ±4.0
Common Channel
Ion Maximum On–Channel Leakage Vin = VCC or GND µA
Channel–to–Channel 6.0 ±0.2 ±2.0 ±4.0

Symbol Parameter VCC –55 to 25°C ≤85°C ≤125°C Unit
tPHL, Maximum Propagation Delay, Analog Input to Analog Output 2.0 160 180 200 ns
tPLH 3.0 80 90 100
4.5 40 45 50
6.0 30 35 40
tPHL, tPHZ,PZH Maximum Propagation Delay, Enable or Channel–Select to 2.0 260 280 300 ns
tPLH, tPLZ,PZL Analog Output 3.0 160 180 200
4.5 80 90 100
6.0 60 70 80
Cin Maximum Input Capacitance Digital Pins 10 10 10 pF
(All Switches Off) Any Single Analog Pin 35 35 35
(All Switches Off) Common Analog Pin 130 130 130
CPD Power Dissipation Capacitance Typical 5.0 20 pF
INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5V, TA = –55°C to +125°C)

Symbol Parameter Typ Max Unit Condition
V∆out Maximum Shift of Output Voltage of Enabled Analog 0.1 1.0 mV Iin* ≤ 1mA, RS ≤ 3,9kΩ
Channel 1.0 5.0 Iin* ≤ 10mA, RS ≤ 3,9kΩ
0.5 2.0 Iin* ≤ 1mA, RS ≤ 20kΩ
5.0 20 Iin* ≤ 10mA, RS ≤ 20kΩ
* Iin = Total current injected into all disabled channels.
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90
1100 1100
1000 1000
900 900
R on , ON RESISTANCE (OHMS)
–55°C
800 800
+25°C
700 700
+125°C
600 600
500 500
–55°C
400 400
+25°C
300 300 +125°C
200 200
100 100
0 0
0.0 0.4 0.8 1.2 1.6 2.0 0.0 0.6 1.2 1.8 2.4 3.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
Figure 5. Typical On Resistance VCC = 2V Figure 6. Typical On Resistance VCC = 3V
660 440
600 400
540 360
480 320
–55°C
420 280
+25°C
360 –55°C 240
+125°C
300 200
+25°C
240 +125°C 160
180 120
120 80
60 40
0 0
0.0 0.9 1.8 2.7 3.6 4.5 0.0 1.2 2.4 3.6 4.8 6.0
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
Figure 7. Typical On Resistance VCC = 4.5V Figure 8. Typical On Resistance VCC = 6V
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91
VCC = 5V
Iin
Vin2 < VSS or VCC < Vin2

Any Disabled Channel
VSS < Vin1 < VCC

Enabled Channel Vout = Vin1 ±V∆out
RS
Figure 9. Injection Current Coupling Specification
5V 6V
5V VCC
VCC
HC4051A Microcontroller
Sensor
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry) Common Out A/D – Input
Figure 10. Actual Technology

Requires 32 passive components and one extra 6V regulator
to suppress injection current into a standard HC4051 multiplexer
5V VCC
VCC
HC4851A Microcontroller
Sensor
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry) Common Out A/D – Input
Figure 11. MC74HC4851A Solution

Solution by applying the HC4851A multiplexer
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92
PLOTTER
VCC
PROGRAMMABLE
POWER MINI COMPUTER DC ANALYZER VCC
VEE 16
SUPPLY
OFF
– + VCC VCC A
NC OFF COMMON O/I
DEVICE
UNDER TEST
VIH 6
8
GND
Figure 13. Maximum Off Channel Leakage Current,

Figure 12. On Resistance Test Any One Channel, Test Set–Up
Set–Up
VCC
VCC VCC VCC

VEE 16 A 16
ANALOG I/O
OFF ON
VCC VEE N/C
OFF OFF COMMON O/I
COMMON O/I
VCC ANALOG I/O
VIH 6 VIL 6
8 8
Common Channel, Test Set–Up Channel to Channel, Test Set–Up
VCC
VCC
16
VCC
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL
6
ANALOG
OUT 50%
8
CHANNEL SELECT
Figure 16. Propagation Delays, Channel Select Figure 17. Propagation Delay, Test Set–Up Channel
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93
VCC
16
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
ANALOG 8
OUT 50%
Figure 18. Propagation Delays, Analog In Figure 19. Propagation Delay, Test Set–Up

90%
ENABLE 50% 2
VCC
10%
GND VCC 10kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE ON/OFF TEST
ANALOG 50% 2 POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG
OUT 50% 8
HIGH
IMPEDANCE
Figure 20. Propagation Delays, Enable to Figure 21. Propagation Delay, Test Set–Up
VCC
A
VCC
16
ON/OFF COMMON O/I
ANALOG I/O NC
OFF/ON
6 VCC
8 11
CHANNEL SELECT
Figure 22. Power Dissipation Capacitance,

Test Set–Up
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94
Gate = VCC
Disabled Analog Mux Input (Disabled) Common Analog Output
Vin > VCC + 0.7V Vout > VCC
P+ P+
+
+
+
N – Substrate (on VCC potential)
Figure 23. Diagram of Bipolar Coupling Mechanism

Appears if Vin exceeds VCC, driving injection current into the substrate
INJECTION 13
11 CURRENT X0
A CONTROL
INJECTION 14
CURRENT X1
CONTROL
10 INJECTION
B 15
CURRENT X2
CONTROL
INJECTION 12
CURRENT X3
CONTROL
9 INJECTION
C 1
CURRENT X4
CONTROL
INJECTION 5
CURRENT X5
CONTROL
INJECTION 2
6 CURRENT X6
ENABLE CONTROL
INJECTION 4
CURRENT X7
CONTROL
INJECTION 3
CURRENT X
CONTROL
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95
INJECTION 13
10 CURRENT X0
A CONTROL
INJECTION 14
CURRENT X1
CONTROL
9 INJECTION 15
B
CURRENT X2
CONTROL
INJECTION 12
CURRENT X3
CONTROL
INJECTION 13
CURRENT X
CONTROL
6 INJECTION
ENABLE 1
CURRENT Y0
CONTROL
INJECTION 5
CURRENT Y1
CONTROL
INJECTION 2
CURRENT Y2
CONTROL
INJECTION 4
CURRENT Y3
CONTROL
INJECTION 3
CURRENT Y
CONTROL

MC74HC4851ADW SOIC–16 WIDE 48 Units / Rail
MC74HC4851ADWR2 SOIC–16 WIDE 1000 Units / Tape & Reel
MC74HC4852ADW SOIC–16 WIDE 48 Units / Rail
MC74HC4852ADWR2 SOIC–16 WIDE 1000 Units / Tape & Reel
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96
MC74VHC4051,
MC74VHC4052,
MC74VHC4053
Demultiplexers
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The MC74VHC4051, MC74VHC4052 and MC74VHC4053 utilize
silicon–gate CMOS technology to achieve fast propagation delays, MARKING
low ON resistances, and low OFF leakage currents. These analog DIAGRAMS
multiplexers/demultiplexers control analog voltages that may vary
16
across the complete power supply range (from VCC to VEE).
SO–16
The VHC4051, VHC4052 and VHC4053 are identical in pinout to D SUFFIX VHC405x
the high–speed HC4051A, HC4052A and HC4053A, and the 16 CASE 751B AWLYWW
metal–gate MC14051B, MC14052B and MC14053B. The 1
1
Channel–Select inputs determine which one of the Analog
16
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog TSSOP–16 VHC
switches are turned off. 16 DT SUFFIX 405x
The Channel–Select and Enable inputs are compatible with standard CASE 948F ALYW
1
CMOS outputs; with pullup resistors they are compatible with LSTTL 1
outputs.
These devices have been designed so that the ON resistance (Ron) is A = Assembly Location
WL = Wafer Lot
more linear over input voltage than Ron of metal–gate CMOS analog YY = Year
switches. WW = Work Week
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs ORDERING INFORMATION
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V See detailed ordering and shipping information in the package
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
• Low Noise
• Chip Complexity: VHC4051 — 184 FETs or 46 Equivalent Gates
VHC4052 — 168 FETs or 42 Equivalent Gates
VHC4053 — 156 FETs or 39 Equivalent Gates

March, 2000 – Rev. 3 MC74VHC4051/D
MC74VHC4051, MC74VHC4052, MC74VHC4053
LOGIC DIAGRAM FUNCTION TABLE – MC74VHC4051

MC74VHC4051 Control Inputs
Single–Pole, 8–Position Plus Common Off Select
Enable C B A ON Channels
13
X0 L L L L X0
14
X1 L L L H X1
15
X2 3 COMMON L L H L X2
ANALOG 12 X L L H H X3
MULTIPLEXER/ OUTPUT/
INPUTS/ X3
OUTPUTS X4 1 DEMULTIPLEXER INPUT L H L L X4
5 L H L H X5
X5 L H H L X6
2
X6 L H H H X7
4 H X X X NONE
X7
11
A X = Don’t Care
CHANNEL 10
SELECT B
INPUTS C
9 Pinout: MC74VHC4051 (Top View)
6 VCC X2 X1 X0 X3 A B C
ENABLE
PIN 16 = VCC 16 15 14 13 12 11 10 9
PIN 7 = VEE
PIN 8 = GND
1 2 3 4 5 6 7 8
FUNCTION TABLE – MC74VHC4052

MC74VHC4052
Select
12
X0 L L L Y0 X0
14
X1 13 L L H Y1 X1
15 X SWITCH X
X2 L H L Y2 X2
11 L H H Y3 X3
X3
Y0 X = Don’t Care
5 3
Y1 Y SWITCH Y
2
Y2
4
Y3 Pinout: MC74VHC4052 (Top View)
10
CHANNEL-SELECT A VCC X2 X1 X X0 X3 A B
9 PIN 16 = VCC
INPUTS B
PIN 7 = VEE 16 15 14 13 12 11 10 9
PIN 8 = GND
6
ENABLE
1 2 3 4 5 6 7 8
Y0 Y2 Y Y3 Y1 Enable VEE GND
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FUNCTION TABLE – MC74VHC4053

Control Inputs
LOGIC DIAGRAM
MC74VHC4053 Select
Triple Single–Pole, Double–Position Plus Common Off Enable C B A ON Channels
L L L L Z0 Y0 X0
12 L L L H Z0 Y0 X1
X0 14
13 X SWITCH X L L H L Z0 Y1 X0
X1 L L H H Z0 Y1 X1
L H L L Z1 Y0 X0
2 L H L H Z1 Y0 X1
Y0 15 COMMON
ANALOG 1 Y SWITCH Y L H H L Z1 Y1 X0
L H H H Z1 Y1 X1
H X X X NONE
5
Z0 4
3 Z SWITCH Z X = Don’t Care
Z1
11
A
INPUTS B
9 PIN 7 = VEE Pinout: MC74VHC4053 (Top View)
C PIN 8 = GND
6 VCC Y X X1 X0 A B C
ENABLE
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
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ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Referenced to VEE) – 0.5 to + 14.0
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V be taken to avoid applications of any
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC + 0.5
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, SOIC Package† 500 mW tied to an appropriate logic voltage
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ TSSOP Package† 450 level (e.g., either GND or V CC ).
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
TL
ÎÎÎÎÎ
ÎÎÎ
260

_C
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ Parameter Min Max Unit
ÎÎÎÎ
VCC
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Positive DC Supply Voltage
ÎÎ
ÎÎÎ
(Referenced to GND)
(Referenced to VEE)
2.0
2.0
6.0
12.0
V
ÎÎÎÎ
VEE
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎ
GND) ÎÎÎ
Negative DC Supply Voltage, Output (Referenced to
ÎÎ
ÎÎÎ
– 6.0 GND V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage VEE VCC V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Vin Digital Input Voltage (Referenced to GND) GND VCC V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIO* Static or Dynamic Voltage Across Switch 1.2 V
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TA Operating Temperature Range, All Package Types – 55 + 125 _C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
tr, tf Input Rise/Fall Time VCC = 2.0 V 0 1000 ns
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC = 4.5 V 0 500
ÎÎ
VCC = 6.0 V 0 400
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100
Guaranteed Limit
VCC
Enable Inputs 4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
Enable Inputs 4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
Channel–Select or Enable Inputs VEE = – 6.0 V
ICC Maximum Quiescent Supply Channel Select, Enable and µA
Current (per Package) VIS = VCC or GND; VEE = GND 6.0 1 10 40
VIO = 0 V VEE = – 6.0 6.0 4 40 80
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS Analog Section
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
v ÎÎ VCC VEE – 55 to
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
Symbol Parameter Test Conditions V V 25_C 85_C 125_C Unit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
Ron Maximum “ON” Resistance Vin = VIL or VIH 3.0 0.0 200 240 320 Ω
VIS = VCC to VEE 4.5 0.0 160 200 280
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ IS 2.0 mA (Figures 1, 2) 4.5 – 4.5 120 150 170
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
6.0 – 6.0 100 125 140
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
Vin = VIL or VIH 3.0 0.0 150 180 230
VIS = VCC or VEE 4.5 0.0 110 140 190
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Endpoints) 4.5 – 4.5 90 120 140
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
IS 2.0 mA (Figures 1, 2) 6.0 – 6.0 80 100 115
∆Ron Maximum Difference in “ON” Vin = VIL or VIH 3.0 0.0 40 50 80 Ω
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎ
Resistance Between Any Two
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎÎÎ
Channels in the Same Package
VIS = 1/2 (VCC – VEE)
IS 2.0 mA
4.5
4.5
6.0
0.0
– 4.5
– 6.0
20
10
10
25
15
12
40
18
14
Ioff Maximum Off–Channel Leakage Vin = VIL or VIH; µA
Current, Any One Channel VIO = VCC – VEE; 6.0 – 6.0 0.1 0.5 1.0
Maximum Off–Channel VHC4051 Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0
Leakage Current, VHC4052 VIO = VCC – VEE; 6.0 – 6.0 0.1 1.0 2.0
Common Channel VHC4053 Switch Off (Figure 4) 6.0 – 6.0 0.1 1.0 2.0
Ion Maximum On–Channel VHC4051 Vin = VIL or VIH; 6.0 – 6.0 0.2 2.0 4.0 µA
Leakage Current, VHC4052 Switch–to–Switch = 6.0 – 6.0 0.1 1.0 2.0
Channel–to–Channel VHC4053 VCC – VEE; (Figure 5) 6.0 – 6.0 0.1 1.0 2.0
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Guaranteed Limit
VCC
tPHL (Figure 9) 3.0 90 110 125
4.5 59 79 85
6.0 45 65 75
tPHL (Figure 10) 3.0 25 30 32
4.5 12 15 18
6.0 10 13 15
tPHZ (Figure 11) 3.0 70 95 110
4.5 48 63 76
6.0 39 55 63
tPZH (Figure 11) 3.0 115 145 155
4.5 49 69 83
6.0 39 58 67
(All Switches Off) Common O/I: VHC4051 130 130 130
VHC4052 80 80 80
VHC4053 50 50 50
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Figure 13)* VHC4051 45 pF
VHC4052 80
VHC4053 45
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC .
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102

Limit*
VCC VEE
Symbol Parameter Condition V V 25°C Unit
BW Maximum On–Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage to ‘51 ‘52 ‘53 MHz
or Minimum
Mi i Frequency
F Response
R Obt i 0dBm
Obtain 0dB att VOS; Increase
I fin
2.25 –2.25 80 95 120
(Figure 6) Frequency Until dB Meter Reads –3dB;
4.50 –4.50 80 95 120
RL = 50Ω, CL = 10pF
6.00 –6.00 80 95 120
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
(Figure 7) Obtain 0dBm at VIS 4.50 –4.50 –50
fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –40
4.50 –4.50 –40
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –40
— Feedthrough Noise. Vin ≤ 1MHz Square Wave (tr = tf = 6ns); 2.25 –2.25 25 mVPP
Channel–Select Input to Common Adjust RL at Setup so that IS = 0A; 4.50 –4.50 105
I/O (Figure 8) Enable = GND RL = 600Ω, CL = 50pF 6.00 –6.00 135
2.25 –2.25 35
4.50 –4.50 145
RL = 10kΩ, CL = 10pF 6.00 –6.00 190
— Crosstalk Between Any Two fin = Sine Wave; Adjust fin Voltage to 2.25 –2.25 –50 dB
Switches (Figure 12) Obtain 0dBm at VIS 4.50 –4.50 –50
(Test does not apply to VHC4051) fin = 10kHz, RL = 600Ω, CL = 50pF 6.00 –6.00 –50
2.25 –2.25 –60
4.50 –4.50 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 6.00 –6.00 –60
VIS = 4.0VPP sine wave 2.25 –2.25 0.10
VIS = 8.0VPP sine wave 4.50 –4.50 0.08
VIS = 11.0VPP sine wave 6.00 –6.00 0.05
300 180
160
250
140
200 120
125°C 125°C
100
150
25°C 80
25°C
– 55°C
100 60
40 – 55°C
50
20
0 0
0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 3.0 V
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103
120 105
100 90

75 125°C
80
125°C
60
60 25°C
25°C 45
– 55°C
40
– 55°C 30
20 15
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Figure 1c. Typical On Resistance, VCC – VEE = 4.5 V Figure 1d. Typical On Resistance, VCC – VEE = 6.0 V
80 60
70
50

125°C
60
40
50 25°C
125°C
40 30
– 55°C
30 25°C
20
20 – 55°C
10
10
0 0
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 –6.0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 6.0
Figure 1e. Typical On Resistance, VCC – VEE = 9.0 V Figure 1f. Typical On Resistance, VCC – VEE = 12.0 V
PLOTTER
PROGRAMMABLE
SUPPLY
– + VCC
DEVICE
UNDER TEST
GND VEE
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104
VCC VCC
VCC VCC
VEE 16 VEE 16
ANALOG I/O
OFF OFF
VCC A VCC
VIH 6 VIH 6
7 7
8 8
VEE VEE
VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
VEE N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O
VIL 6 6
7 7
8 8
VEE VEE

VIS VCC VOS VCC

0.1µF 16 dB 16
RL
TEST
POINT
OFF/ON RL CL*
RL
6 6
7 7 VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 6 ns
VEE VCC VEE
VIL or VIH GND
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105
VCC
VCC
16
VCC
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL
6
ANALOG 7
OUT 50%
8
CHANNEL SELECT
VCC
16
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
7
ANALOG 8
OUT 50%

90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG 7
OUT 50% 8
HIGH
IMPEDANCE
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VCC
VIS A
VCC
16 16
RL VOS
ANALOG I/O NC
0.1µF OFF/ON
OFF
VEE RL CL* RL CL* VCC
RL 6
7
6 VEE 8 11
7
8 CHANNEL SELECT
0
VIS
0.1µF 16 – 20
TO
RL METER
CL* – 40
dB
– 50
DEVICE
– 60
6 SOURCE
– 70
7
8 – 80
VEE – 90
– 100
1.0 2.0 3.125
FREQUENCY (kHz)
The Channel Select and Enable control pins should be at outputs to VCC or GND through a low value resistor helps
VCC or GND logic levels. VCC being recognized as a logic minimize crosstalk and feedthrough noise that may be
high and GND being recognized as a logic low. In this picked up by an unused switch.
example: Although used here, balanced supplies are not a
VCC = +5V = logic high requirement. The only constraints on the power supplies are
GND = 0V = logic low that:
The maximum analog voltage swings are determined by VCC – GND = 2 to 6 volts
the supply voltages VCC and VEE. The positive peak analog VEE – GND = 0 to –6 volts
voltage should not exceed VCC. Similarly, the negative peak VCC – VEE = 2 to 12 volts
analog voltage should not go below VEE. In this example, and VEE ≤ GND
the difference between VCC and VEE is ten volts. Therefore, When voltage transients above VCC and/or below VEE are
using the configuration of Figure 15, a maximum analog anticipated on the analog channels, external Germanium or
signal of ten volts peak–to–peak can be controlled. Unused Schottky diodes (Dx) are recommended as shown in Figure
analog inputs/outputs may be left floating (i.e., not 16. These diodes should be able to absorb the maximum
connected). However, tying unused analog inputs and anticipated current surges during clipping.
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107
VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
–5V SIGNAL SIGNAL –5V
Dx Dx
VEE VEE
7 10 CIRCUITRY 0 to 5V 7
–5V VEE

+5V +5V
+5V 16 +5V +5V 16 +5V

ON/OFF ON/OFF
VEE SIGNAL SIGNAL VEE VEE SIGNAL SIGNAL VEE
+5V
*
R R R +5V
6 11 6 11
7 10 7 10
CIRCUITRY CIRCUITRY
8 9 8 9
VEE VEE
* 2K ≤ R ≤ 10K HCT
BUFFER
11 LEVEL 13
A X0
SHIFTER
14
X1
10 LEVEL 15
B X2
SHIFTER
12
X3
9 LEVEL 1
C X4
SHIFTER
5
X5
6 LEVEL 2
ENABLE X6
SHIFTER
4
X7
3
X
Figure 18. Function Diagram, VHC4051
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10 LEVEL 12
A X0
SHIFTER
14
X1
9 LEVEL 15
B X2
SHIFTER
11
X3
13
X
6 LEVEL 1
ENABLE Y0
SHIFTER
5
Y1
2
Y2
4
Y3
3
Y
11 LEVEL 13
A X1
SHIFTER
12
X0
14
X
10 LEVEL 1
B Y1
SHIFTER
2
Y0
15
Y
9 LEVEL 3
C Z1
SHIFTER
5
Z0
4
Z
6 LEVEL
ENABLE
SHIFTER
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MC74VHC4051D SOIC–16 48 Units / Rail
MC74VHC4051DR2 SOIC–16 2500 Units / Tape & Reel
MC74VHC4051DT TSSOP–16 96 Units / Rail
MC74VHC4051DTR2 TSSOP–16 2500 Units / Tape & Reel
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MC74VHC1G66
Advance Information
Analog Switch
The MC74VHC1G66 is an advanced high speed CMOS bilateral
analog switch fabricated with silicon gate CMOS technology. It
achieves high speed propagation delays and low ON resistances while
maintaining CMOS low power dissipation. This bilateral switch http://onsemi.com
controls analog and digital voltages that may vary across the full
power–supply range (from VCC to GND).
The MC74VHC1G66 is compatible in function to a single gate of
the High Speed CMOS MC74VHC4066 and the metal–gate CMOS
MC14066. The device has been designed so that the ON resistances
(RON) are much lower and more linear over input voltage than RON of
the metal–gate CMOS or High Speed CMOS analog switches. SC–88A / SOT–353
DF SUFFIX
The ON/OFF control inputs are compatible with standard CMOS
CASE 419A
outputs; with pull–up resistors, it is compatible with LSTTL outputs.
• High Speed: tPD = TBD (Typ) at VCC = 5 V
MARKING DIAGRAM
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• Diode Protection Provided on Inputs and Outputs
• Improved Linearity and Lower ON Resistance over Input Voltage V9d
than the MC14066 or the HC4066
• Pin and Function Compatible with Other Standard Logic Families Pin 1
• Latchup Performance Exceeds 300 mA d = Date Code
• ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V
• Chip Complexity: 11 FETs or 3 Equivalent Gates PIN ASSIGNMENT
1 IN/OUT XA
2 OUT/IN YA
IN/OUT XA 1 5 VCC 3 GND
4 ON/OFF CONTROL
5 VCC
OUT/IN YA 2
GND 3 4 ON/OFF CONTROL

5–Lead SOT–353 Pinout (Top View)
LOGIC SYMBOL FUNCTION TABLE
ON/OFF CONTROL X1 On/Off Control Input State of Analog Switch

U U
IN/OUT XA 1 1 OUT/IN YA L Off
H On


November, 1999 – Rev. 1 MC74VHC1G66/D
MC74VHC1G66
ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit
DC Supply Voltage VCC –0.5 to +7.0 V
Digital Input Voltage VIN –0.5 to VCC +0.5 V
Analog Output Voltage VIS –0.5 to VCC + 0.5 V
Digital Input Diode Current IIK –20 mA
DC Supply Current, VCC and GND ICC +25 mA
Power dissipation in still air, SC–88A † PD 200 mW
Lead temperature, 1 mm from case for 10 s TL 260 °C
Storage temperature Tstg –65 to +150 °C
†Derating — SC–88A Package: –3 mW/_C from 65_ to 125_C

Characteristics Symbol Min Max Unit
DC Supply Voltage VCC 4.5 5.5 V
Digital Input Voltage VIN GND VCC V
Analog Input Voltage VIS GND VCC V
Static or Dynamic Voltage Across Switch VIO* 1.2 V
Operating Temperature Range TA –55 +85 °C
Input Rise and Fall Time tr , tf ns/V
ON/OFF Control Input VCC = 3.3V ± 0.3V 0 100
VCC = 5.0V ± 0.5V 0 20
* For voltage drops across the switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e. the current out of the switch may
contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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MC74VHC1G66
DC ELECTRICAL CHARACTERISTICS
VCC TA = 25°C TA ≤ 85°C TA ≤ 125°C
Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit
VIH Minimum High–Level RON = Per Spec 2.0 1.5 1.5 1.5 V
Input Voltage 3.0 2.1 2.1 2.1
ON/OFF Control Input 4.5 3.15 3.15 3.15
5.5 3.85 3.85 3.85
VIL Maximum Low–Level RON = Per Spec 2.0 0.5 0.5 0.5 V
5.5 1.65 1.65 1.65
IIN Maximum Input VIN = VCC or GND 0 to ±0.1 ±1.0 ±1.0 µA
Leakage Current 5.5
ON/OFF Control Input
ICC Maximum Quiescent VIN = VCC or GND 5.5 2.0 20 40 µA
Supply Current VIO = 0V
RON Maximum ”ON” VIN = VIH 3.0 30 50 70 100 W
Resistance VIS = VCC or GND 4.5 20 30 40 50
|IIS| ≤ 10mA (Figure 1) 5.5 15 20 35 45
Endpoints 3.0 25 50 65 90 W
VIN = VIH 4.5 12 20 26 40
VIS = VCC or GND 5.5 8 15 23 32
|IIS| ≤ 10mA (Figure 1)
IOFF Maximum Off–Channel VIN = VIL 5.5 0.1 0.5 1.0 µA
Leakage Current VIS = VCC or GND
ION Maximum On–Channel VIN = VIH 5.5 0.1 0.5 1.0 µA
Leakage VIS = VCC or GND
Current Switch On (Figure 3)
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr/tf = 3.0ns)
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎ
TA = 25°C TA ≤ 85°C TA ≤ 125°C
VCC
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
tPLH, Maximum Propogation YA = Open 2.0 1 5 6 7 ns
tPHL Delay, 3.0 0 2 3 4
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
W
ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Input X to Y
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎ
Figure 4 4.5
5.5
0
0
1
1
1
1
2
1
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
tPLZ, Maximum Propogation RL = 1000 2.0 15 35 46 57 ns
tPHZ Delay, 3.0 8 15 20 25
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ON/OFF Control to Figure 5 4.5 6 10 13 17
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
Analog Output 5.5 4 7 9 11
W
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
tPZL, Maximum Propogation RL = 1000 2.0 15 35 46 57 ns
tPZH Delay, 3.0 8 15 20 25
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
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ÎÎÎÎÎÎÎ
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CIN Maximum Input ON/OFF Control Input 0.0 3 10 10 10 pF
C
Capacitance
it
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Contol Input = GND 5.0
Analog I/O 4 10 10 10
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Feedthrough 4 10 10 10
Typical @ 25°C, VCC = 5.0V

CPD Power Dissipation Capacitance (Note NO TAG) 18 pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no–load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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MC74VHC1G66
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Limit
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Symbol Parameter Test Conditions VCC 25°C Unit
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BW Maximum On–Channel fin = 1 MHz Sine Wave 3.0 150 MHz
Bandwidth or Minimum Adjust fin voltage to obtain 0 dBm at VOS 4.5 175
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Frequency Response Increase fin = frequency until dB meter reads –3dB 5.5 200
W
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Figure 7 RL = 50 , CL = 10 pF
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ISOoff Off–Channel Feedthrough fin = Sine Wave 3.0 –50 dB
Isolation Adjust fin voltage to obtain 0 dBm at VIS 4.5 –50
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Figure 8 fin = 10 kHz, RL = 600 , CL = 50 pF 5.5 –50
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3.0 –40
fin = 1.0 kHz, RL = 50 , CL = 10 pF
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4.5 –40
5.5 –40
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NOISEfeed
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Switch
W
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Feedthrough Noise Control to
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Vin ≤ 1 MHz Square Wave (tr = tf = 2ns)
Adjust RL at setup so that Is = 0 A
3.0
4.5
45
60
mVPP
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Figure 9 RL = 600 , CL = 50 pF 5.5 130
W
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3.0 25
RL = 50 , CL = 10 pF
4.5 30
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5.5 60
W
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THD Total Harmonic Distortion fin = 1 kHz, RL = 10k , CL = 50 pF %
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Figure 10 THD = THDMeasured – THDSource
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MC74VHC1G66
PLOTTER
POWER DC PARAMETER
SUPPLY COMPUTER ANALYZER
– +
VCC
VCC VCC
1 5 1 5
2 2 VIL
VCC A
3 4 3 4
Figure 1. On Resistance Test Set–Up Figure 2. Maximum Off–Channel Leakage Current

Test Set–Up
VCC
VCC VCC
A 1 5 1 5
N/C 2 VIH TEST 2 VCC

POINT
3 4 3 4
Figure 3. Maximum On–Channel Leakage Current Figure 4. Propagation Delay Test Set–Up
Test Set–Up
Switch to Position 1 when testing tPLZ and tPZL

Switch to Position 2 when testing tPHZ and tPZH
VCC
TEST POINT
VCC
VCC A
1
1 5 N/C 1 5
2 RL
2 N/C 2
VCC 1
CL*
3 4 3 4
2
Figure 5. Propagation Delay Output Enable/Disable Figure 6. Power Dissipation Capacitance Test
Test Set–Up Set–Up
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MC74VHC1G66
VOS VIS VOS
VCC VCC
0.1 mF 0.1 mF
fin 1 5 fin 1 5
2 2
dB CL* dB CL*
3 4 RL 3 4
Meter Meter
Figure 7. Maximum On–Channel Bandwidth Figure 8. Off–Channel Feedthrough Isolation Test

To Distortion
Meter
(VCC)/2
(VCC)/2 VIS
VCC VCC
RL 0.1 mF
RL 1 5 RL fin 1 5
VOS V
IN
v 1 MHz VOS
t r + t + 2 ns
IS 2 2
f CL*
CL* VCC
3 4 3 4
GND
Figure 9. Feedthrough Noise, ON/OFF Control to Figure 10. Total Harmonic Distortion Test Set–Up
Analog Out, Test Set–Up
tr tf
90% VCC
Control
50% VCC
VCC 10%
XA
50% 50% VCC
tPZL tPLZ
tPLH tPHL High

50% VCC Impedance
VOH 10%
Analog Out VOL
YA 50% VCC VOH
VOL 90%
50% VCC
High
tPZH tPHZ Impedance
Figure 11. Propagation Delay,

Analog In to Analog Out Waveforms Figure 12. Propagation Delay, ON/OFF Control
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MC74VHC1G66
DEVICE ORDERING INFORMATION

Device Nomenclature
Temp Tape &
Circuit Range Device Package Reel Package Tape and Reel
Device Order Number Indicator Identifier Technology Function Suffix Suffix Type Size
SC–88A /
MC74VHC1G66DFT1 MC 74 VHC1G 66 DF T1 SOT–353 7–Inch/3000 Unit
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117
MC74VHC1GT66
Advance Information
Analog Switch
The MC74VHC1GT66 is an advanced high speed CMOS bilateral
analog switch fabricated with silicon gate CMOS technology. It
achieves high speed propagation delays and low ON resistances while
maintaining CMOS low power dissipation. This bilateral switch http://onsemi.com
controls analog and digital voltages that may vary across the full
power–supply range (from VCC to GND).
The MC74VHC1GT66 is compatible in function to a single gate of
the very High Speed CMOS MC74VHCT4066. The device has been
designed so that the ON resistances (RON) are much lower and more
linear over input voltage than RON of the metal–gate CMOS or High
Speed CMOS analog switches. SC–88A / SOT–353
DF SUFFIX
The ON/OFF Control input is compatible with TTL–type input
CASE 419A
thresholds allowing the device to be used as a logic–level translator
from 3.0V CMOS logic to 5.0V CMOS logic or from 1.8V CMOS
logic to 3.0V CMOS logic while operating at the high–voltage power MARKING DIAGRAM
supply. The input protection circuitry on this device allows
overvoltage tolerance on the input, which provides protection when
voltages of up to 7V are applied, regardless of the supply voltage. This VEd
allows the MC74VHC1GT66 to be used to interface 5V circuits to 3V
circuits. Pin 1
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C d = Date Code
• Diode Protection Provided on Inputs and Outputs
• Improved Linearity and Lower ON Resistance over Input Voltage PIN ASSIGNMENT
• Pin and Function Compatible with Other Standard Logic Families 1 IN/OUT XA
• Latchup Performance Exceeds 300 mA 2 OUT/IN YA
• ESD Performance: HBM > 2000 V; MM > 200 V, CDM > 1500 V 3 GND
4 ON/OFF CONTROL
5 VCC
IN/OUT XA 1 5 VCC
OUT/IN YA 2 ORDERING INFORMATION

GND 3 4 ON/OFF CONTROL
FUNCTION TABLE
5–Lead SOT–353 Pinout (Top View)
On/Off Control Input State of Analog Switch
L Off
LOGIC SYMBOL
H On
ON/OFF CONTROL X1
U U
IN/OUT XA 1 1 OUT/IN YA


November, 1999 – Rev. 2 MC74VHC1GT66/D
MC74VHC1GT66
ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit
DC Supply Voltage VCC –0.5 to +7.0 V
Digital Input Voltage VIN –0.5 to VCC +0.5 V
Analog Output Voltage VIS –0.5 to VCC + 0.5 V
Digital Input Diode Current IIK –20 mA
DC Supply Current, VCC and GND ICC +25 mA
Power dissipation in still air, SC–88A † PD 200 mW
Lead temperature, 1 mm from case for 10 s TL 260 °C
Storage temperature Tstg –65 to +150 °C
†Derating — SC–88A Package: –3 mW/_C from 65_ to 125_C

Characteristics Symbol Min Max Unit
DC Supply Voltage VCC 4.5 5.5 V
Digital Input Voltage VIN GND VCC V
Analog Input Voltage VIS GND VCC V
Static or Dynamic Voltage Across Switch VIO* 1.2 V
Operating Temperature Range TA –55 +85 °C
Input Rise and Fall Time tr , tf ns/V
ON/OFF Control Input VCC = 3.3V ± 0.3V 0 100
VCC = 5.0V ± 0.5V 0 20
* For voltage drops across the switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e. the current out of the switch may
contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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MC74VHC1GT66
DC ELECTRICAL CHARACTERISTICS
VCC TA = 25°C TA ≤ 85°C TA ≤ 125°C
VIH Minimum High–Level RON = Per Spec V
5.5 2.0 2.0 2.0
VIL Maximum Low–Level RON = Per Spec V
Input Voltage 3.0 0.53 0.53 0.53
5.5 0.8 0.8 0.8
IIN Maximum Input VIN = VCC or GND 0 to ±0.1 ±1.0 ±1.0 µA
Leakage Current 5.5
ON/OFF Control Input
ICC Maximum Quiescent VIN = VCC or GND 5.5 2.0 20 40 µA
Supply Current VIO = 0V
ICCT Quiescent ON/OFF Control at 5.5 1.35 1.5 1.65 mA
Supply Current 3.4V
RON Maximum ”ON” VIN = VIH 3.0 30 50 70 100 W
Resistance VIS = VCC or GND 4.5 20 30 40 50
|IIS| ≤ 10mA (Figure 1) 5.5 15 20 35 45
Endpoints 3.0 25 50 65 90 W
VIN = VIH 4.5 12 20 26 40
VIS = VCC or GND 5.5 8 15 23 32
|IIS| ≤ 10mA (Figure 1)
IOFF Maximum Off–Channel VIN = VIL 5.5 0.1 0.5 1.0 µA
Leakage Current VIS = VCC or GND
ION Maximum On–Channel VIN = VIH 5.5 0.1 0.5 1.0 µA
Leakage VIS = VCC or GND
Current Switch On (Figure 3)
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AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr/tf = 3.0ns)
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TA = 25°C TA ≤ 85°C TA ≤ 125°C
VCC
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tPLH, Maximum YA = Open 2.0 1 5 6 7 ns
tPHL Propogation Delay, 3.0 0 2 3 4
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W
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Input X to Y
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Figure 4 4.5
5.5
0
0
1
1
1
1
2
1
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tPLZ, Maximum RL = 1000 2.0 15 35 46 57 ns
tPHZ Propogation Delay, 3.0 8 15 20 25
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tPZL, Maximum RL = 1000 2.0 15 35 46 57 ns
tPZH Propogation Delay, 3.0 8 15 20 25
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CIN Maximum Input ON/OFF Control Input 0.0 3 10 10 10 pF
C
Capacitance
it
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Contol Input = GND 5.0
Analog I/O 4 10 10 10
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Feedthrough 4 10 10 10
Typical @ 25°C, VCC = 5.0V

CPD Power Dissipation Capacitance (Note NO TAG) 18 pF
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120
MC74VHC1GT66
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Limit
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Symbol Parameter Test Conditions VCC 25°C Unit
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BW Maximum On–Channel fin = 1 MHz Sine Wave 3.0 150 MHz
Bandwidth or Minimum Adjust fin voltage to obtain 0 dBm at VOS 4.5 175
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Frequency Response Increase fin = frequency until dB meter reads –3dB 5.5 200
W
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Figure 7 RL = 50 , CL = 10 pF
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ISOoff Off–Channel Feedthrough fin = Sine Wave 3.0 –50 dB
Isolation Adjust fin voltage to obtain 0 dBm at VIS 4.5 –50
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W
Figure 8 fin = 10 kHz, RL = 600 , CL = 50 pF 5.5 –50
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W
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3.0 –40
fin = 1.0 kHz, RL = 50 , CL = 10 pF
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4.5 –40
5.5 –40
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NOISEfeed
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Switch
W
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Feedthrough Noise Control to
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Vin ≤ 1 MHz Square Wave (tr = tf = 2ns)
Adjust RL at setup so that Is = 0 A
3.0
4.5
45
60
mVPP
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Figure 9 RL = 600 , CL = 50 pF 5.5 130
W
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3.0 25
RL = 50 , CL = 10 pF
4.5 30
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5.5 60
W
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THD Total Harmonic Distortion fin = 1 kHz, RL = 10k , CL = 50 pF %
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Figure 10 THD = THDMeasured – THDSource
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121
MC74VHC1GT66
PLOTTER
POWER DC PARAMETER
SUPPLY COMPUTER ANALYZER
– +
VCC
VCC VCC
1 5 1 5
2 VIH 2 VIL
VCC A
3 4 3 4
Figure 1. On Resistance Test Set–Up Figure 2. Maximum Off–Channel Leakage Current

Test Set–Up
VCC
VCC VCC
A 1 5 1 5
N/C 2 VIH TEST 2 VIH

POINT
3 4 3 4
Figure 3. Maximum On–Channel Leakage Current Figure 4. Propagation Delay Test Set–Up
Test Set–Up
Switch to Position 1 when testing tPLZ and tPZL

Switch to Position 2 when testing tPHZ and tPZH
VCC
TEST POINT
VCC
VCC A
1
1 5 N/C 1 5
2 RL
2 N/C 2
VCC 1
CL*
3 4 3 4
2
Figure 5. Propagation Delay Output Enable/Disable Figure 6. Power Dissipation Capacitance Test
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122
MC74VHC1GT66
VOS VIS VOS
VCC VCC
0.1 mF 0.1 mF
fin 1 5 fin 1 5
2 VIH 2
dB CL* dB CL*
3 4 RL 3 4
Meter Meter
Figure 7. Maximum On–Channel Bandwidth Figure 8. Off–Channel Feedthrough Isolation Test

To Distortion
Meter
(VCC)/2
(VCC)/2 VIS
VCC VCC
RL 0.1 mF
RL 1 5 RL fin 1 5
VOS V
IN
v 1 MHz VOS
t r + t + 2 ns
IS 2 2 VIH
f CL*
CL* VIH
3 4 3 4
GND
Figure 9. Feedthrough Noise, ON/OFF Control to Figure 10. Total Harmonic Distortion Test Set–Up
Analog Out, Test Set–Up
tr tf
90% VIH
Control
50% VCC
VCC 10%
XA
50% 50% VCC
tPZL tPLZ
tPLH tPHL High

50% VCC Impedance
VOH 10%
Analog Out VOL
YA 50% VCC VOH
VOL 90%
50% VCC
High
tPZH tPHZ Impedance
Figure 11. Propagation Delay,

Analog In to Analog Out Waveforms Figure 12. Propagation Delay, ON/OFF Control
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123
MC74VHC1GT66
DEVICE ORDERING INFORMATION

Device Nomenclature
Temp Tape &
Circuit Range Device Package Reel Package Tape and Reel
Device Order Number Indicator Identifier Technology Function Suffix Suffix Type Size
SC–88A /
MC74VHC1GT66DFT1 MC 74 VHC1G T66 DF T1 SOT–353 7–Inch/3000 Unit
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124
MC74LVX4051
Product Preview
Analog Multiplexer /
Demultiplexer
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The MC74LVX4051 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The LVX4051 is similar in pinout to the LVX8051, HC4051A and 16–LEAD SOIC 16–LEAD TSSOP
D SUFFIX DT SUFFIX
the metal–gate MC14051B. The Channel–Select inputs determine
CASE 751B CASE 948F
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off. PIN CONNECTION AND
The Channel–Select and Enable inputs are compatible with standard MARKING DIAGRAM (Top View)
CMOS outputs; with pull–up resistors they are compatible with VCC X2 X1 X0 X3 A B C
LSTTL outputs. 16 15 14 13 12 11 10 9
This device has been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal–gate CMOS analog
switches.
•
1 2 3 4 5 6 7 8
Low Crosstalk Between Switches
X4 X6 X X7 X5 Enable VEE GND
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal–Gate ORDERING INFORMATION
Counterparts
•
Low Noise
LOGIC DIAGRAM MC74LVX4051D SOIC TBD
MC74LVX4051 MC74LVX4051DT TSSOP TBD
13
X0
14
X1
15
X2 3 COMMON
ANALOG 12 X FUNCTION TABLE – MC74LVX4051
INPUTS/ X3
OUTPUTS X4 1 DEMULTIPLEXER INPUT Control Inputs
5 Select
X5
2 Enable C B A ON Channels
X6
4 L L L L X0
X7
11 L L L H X1
A
CHANNEL 10 L L H L X2
SELECT B L L H H X3
INPUTS 9
C L H L L X4
6 L H L H X5
ENABLE
PIN 16 = VCC L H H L X6
PIN 8 = GND L H H H X7
PIN 7 = VEE H X X X NONE

X = Don’t Care

February, 2000 – Rev. 0 MC74LVX4051/D
MC74LVX4051
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MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VEE Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V circuitry to guard against damage
ÎÎÎÎ
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VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V fields. However, precautions must
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(Referenced to VEE) – 0.5 to + 7.0 be taken to avoid applications of any
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VIS Analog Input Voltage – 0.5 to VCC + 0.5 V
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Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V cuit. For proper operation, Vin and
v v
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PD Power Dissipation in Still Air, SOIC Package† 500 mW Unused inputs must always be
TSSOP Package† 450 tied to an appropriate logic voltage
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level (e.g., either GND or V CC ).
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TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C
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VEE Negative DC Supply Voltage (Referenced to GND) –6.6 GND V
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(Referenced to VEE) 2.0 6.6
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VIS
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Vin
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VEE
0
VCC
VCC
V
V
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VIO*
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TA
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Operating Temperature Range, All Package Types – 55
1.2
+ 85
V
_C
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tr, tf
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ns/V
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(Channel Select or Enable Inputs)
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VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
0
0
100
20
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may
exceeded.
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126
MC74LVX4052
Product Preview
Demultiplexer
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(from VCC to VEE).
The LVX4052 is similar in pinout to the high–speed HC4052A, and 16–LEAD SOIC 16–LEAD TSSOP
D SUFFIX DT SUFFIX
CASE 751B CASE 948F
CMOS outputs; with pull–up resistors they are compatible with VCC X2 X1 X X0 X3 A B
LSTTL outputs. 16 15 14 13 12 11 10 9
switches.
• Low Crosstalk Between Switches 1 2 3 4 5 6 7 8
• Diode Protection on All Inputs/Outputs Y0 Y2 Y Y3 Y1 Enable VEE GND

Counterparts
• Low Noise

MC74LVX4052 MC74LVX4052DT TSSOP TBD
12
X0
14
X1 13
15 X SWITCH X
X2 FUNCTION TABLE – MC74LVX4052
11
X3
ANALOG COMMON
INPUTS/OUTPUTS 1 OUTPUTS/INPUTS Control Inputs
Y0
5 3 Select
Y1 Y SWITCH Y
2 Enable B A ON Channels
Y2
4 L L L Y0 X0
Y3
10 L L H Y1 X1
CHANNEL-SELECT A
9 PIN 16 = VCC L H L Y2 X2
INPUTS B L H H Y3 X3
PIN 7 = VEE
PIN 8 = GND H X X NONE
6
ENABLE X = Don’t Care
NOTE: This device allows independent control of each switch. Channel–
Select Input A controls the X–Switch, Input B controls the Y–Switch

MC74LVX4052
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC + 0.5
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
TL
ÎÎÎÎÎ
ÎÎÎ
260

_C

ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎ
ÎÎÎ
Negative DC Supply Voltage (Referenced to GND) –6.6 GND V
ÎÎÎÎ
VCC
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Referenced to GND) 2.0 3.3 V
ÎÎÎÎ
VIS
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
(Referenced to VEE) 2.0
VEE
6.6
VCC V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎ
VIO*
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
0 VCC
1.2
V
V
ÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
Operating Temperature Range, All Package Types – 55 + 85 _C
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ns/V
ÎÎÎÎÎ
VCC = 3.3 V ± 0.3 V 0 100
ÎÎÎÎ
ÎÎ VCC = 5.0 V ± 0.5 V 0 20
exceeded.
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128
MC74LVX4053
Product Preview
Demultiplexer
http://onsemi.com
(from VCC to VEE).
The LVX4053 is similar in pinout to the LVX8053, HC4053A, and 16–LEAD SOIC 16–LEAD TSSOP
D SUFFIX DT SUFFIX
CASE 751B CASE 948F
CMOS outputs; with pull–up resistors they are compatible with VCC Y X X1 X0 A B C
LSTTL outputs. 16 15 14 13 12 11 10 9
switches.
• Low Crosstalk Between Switches 1 2 3 4 5 6 7 8
•
Diode Protection on All Inputs/Outputs
Counterparts
• Low Noise

Triple Single–Pole, Double–Position Plus Common Off MC74LVX4053DT TSSOP TBD
12
X0 14
13 X SWITCH X
X1
2 FUNCTION TABLE – MC74LVX4053

Y0 15 COMMON
ANALOG 1 Y SWITCH Y
INPUTS/OUTPUTS Y1 OUTPUTS/INPUTS Control Inputs
5 Select
Z0 4 Enable C B A ON Channels
3 Z SWITCH Z
Z1
L L L L Z0 Y0 X0
11
A L L L H Z0 Y0 X1
CHANNEL-SELECT 10 PIN 16 = VCC L L H L Z0 Y1 X0
INPUTS B
9 PIN 8 = GND L L H H Z0 Y1 X1
C PIN 7 = VEE
6 L H L L Z1 Y0 X0
ENABLE L H L H Z1 Y0 X1
NOTE: This device allows independent control of each switch. L H H L Z1 Y1 X0
Channel–Select Input A controls the X–Switch, Input B controls L H H H Z1 Y1 X1
the Y–Switch and Input C controls the Z–Switch H X X X NONE
This document contains information on a product under development. ON Semiconductor X = Don’t Care

MC74LVX4053
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VCC + 0.5
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
TL
ÎÎÎÎÎ
ÎÎÎ
260

_C

ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎ
VEE
ÎÎÎÎÎ
ÎÎÎ
Negative DC Supply Voltage (Referenced to GND) –6.6 GND V
ÎÎÎÎ
VCC
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Referenced to GND) 2.0 3.3 V
ÎÎÎÎ
VIS
ÎÎÎÎÎ
ÎÎ
ÎÎÎ
(Referenced to VEE) 2.0
VEE
6.6
VCC V
ÎÎÎÎ
ÎÎÎÎ
Vin
ÎÎÎ
VIO*
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
0 VCC
1.2
V
V
ÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ns/V
ÎÎÎÎÎ
VCC = 3.3 V ± 0.3 V 0 100
ÎÎÎÎ
ÎÎ VCC = 5.0 V ± 0.5 V 0 20
exceeded.
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130
MC74LVX4066
Quad Analog Switch/

http://onsemi.com
OFF–channel leakage current. This bilateral
switch/multiplexer/demultiplexer controls analog and digital voltages
that may vary across the full power–supply range (from VCC to GND).
The LVX4066 is identical in pinout to the metal–gate CMOS
MC14066 and the high–speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
resistances (RON) are much more linear over input voltage than RON 14–LEAD SOIC 14–LEAD TSSOP
of metal–gate CMOS analog switches. D SUFFIX DT SUFFIX
CASE 751A CASE 948G
The ON/OFF control inputs are compatible with standard CMOS
outputs; with pull–up resistors, they are compatible with LSTTL
outputs. PIN CONNECTION AND
• Fast Switching and Propagation Speeds MARKING DIAGRAM (Top View)
• High ON/OFF Output Voltage Ratio
VCC
XA 1 14
A ON/OFF
• Diode Protection on All Inputs/Outputs YA 2 13 CONTROL
D ON/OFF
• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 6.0 Volts YB 3 12
CONTROL
• Analog Input Voltage Range (VCC – GND) = 2.0 to 6.0 Volts XB 4 11 XD
B ON/OFF
• Improved Linearity and Lower ON Resistance over Input Voltage CONTROL 5 10 YD
than the MC14016 or MC14066 C ON/OFF 6 9 YC
CONTROL
• Low Noise GND 7 8 XC
• Chip Complexity: 44 FETs or 11 Equivalent Gates
For detailed package marking information, see the Marking
LOGIC DIAGRAM Diagram section on page 140 of this data sheet.
1 2
XA YA
FUNCTION TABLE
13
A ON/OFF CONTROL On/Off Control State of
Input Analog Switch
4 3
XB YB
L Off
5 ANALOG H On
B ON/OFF CONTROL OUTPUTS/INPUTS
8 9
XC YC
6 ORDERING INFORMATION
C ON/OFF CONTROL
11 10 Device Package Shipping

XD YD
MC74LVX4066D SOIC 55 Units/Rail
12
D ON/OFF CONTROL ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD MC74LVX4066DR2 SOIC 2500 Units/Reel
PIN 14 = VCC
PIN 7 = GND MC74LVX4066DT TSSOP 96 Units/Rail
MC74LVX4066DTR2 TSSOP 2500 Units/Reel

March, 2000 – Rev. 2 MC74LVX4066/D
MC74LVX4066
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Iin DC Current Into or Out of ON/OFF Control Pins ± 20 mA voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Is DC Current Into or Out of Switch Pins ± 20 mA cuit. For proper operation, Vin and
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, SOIC Package† 500 mW range GND (Vin or Vout) VCC.
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TSSOP Package† 450 Unused inputs must always be
_C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150
TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
Vin
ÎÎÎÎÎ
ÎÎÎ
Analog Input Voltage (Referenced to GND)
ÎÎ
ÎÎÎ
GND
GND
VCC
VCC
V
V
ÎÎÎÎ
VIO*
ÎÎÎÎ ÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Operating Temperature, All Package Types
—
– 55
1.2
+ 85
V
_C
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
ÎÎÎ
Input Rise and Fall Time, ON/OFF Control
ÎÎÎÎÎ
ÎÎÎ
Inputs (Figure 10) VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
0
0
100
20
ns/V
exceeded.
ÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to
ÎÎÎÎ
Symbol
VIH ÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter
ÎÎÎ
Test Conditions
Ron = Per Spec
V
2.0
25_C
1.5
85_C
1.5
125_C
1.5
Unit
V
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Note 1) 4.5 3.15 3.15 3.15
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
5.5 3.85 3.85 3.85
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VIL Maximum Low–Level Voltage Ron = Per Spec 2.0 0.5 0.5 0.5 V
ÎÎÎÎ
(Note 1)
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
4.5
5.5
1.35
1.65
1.35
1.65
1.35
1.65
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 5.5V ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Quiescent Supply
ÎÎÎ
Current (per Package)
Vin = VCC or GND
VIO = 0 V
2. Specifications are for design target only. Not final specification limits.
5.5 4.0 40 160 µA
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132
MC74LVX4066
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VIS = VCC to GND
|IS| 10 mA (Figures 1, 2)
3.0
4.5
5.5
40
25
20
45
30
25
50
35
30
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH
VIS = VCC or GND (Endpoints)
2.0
3.0
—
30
—
35
—
40
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
|IS| 10 mA (Figures 1, 2) 4.5 25 30 35
5.5 20 25 30
ÎÎÎÎ
∆Ron
ÎÎÎÎÎÎÎÎÎÎv ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Difference in “ON”
Vin = VIH
VIS = 1/2 (VCC – GND)
IS 2.0 mA
3.0
4.5
5.5
15
10
10
20
12
12
25
15
15
Ω
ÎÎÎÎ
ÎÎÎÎ
Ioff
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL
VIO = VCC or GND
5.5 0.1 0.5 1.0 µA
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 4)
operation, it is recommended that these devices only be used to control digital signals (See Figure 1a).
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
ÎÎÎÎÎ
tPLH,
ÎÎÎÎÎ ÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
(Figures 8 and 9)
2.0
3.0
4.5
4.0
3.0
1.0
6.0
5.0
2.0
8.0
6.0
2.0
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
tPLZ, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
5.5
2.0
1.0
30
2.0
35
2.0
40 ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHZ (Figures 10 and 11) 3.0 20 25 30
4.5 15 18 22
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
5.5 15 18 20
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZH (Figures 10 and 1 1) 3.0 12 14 15
4.5 8.0 10 12
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
5.5 8.0 10 12
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
C Maximum Capacitance ON/OFF Control Input — 10 10 10 pF
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Control Input = GND
Analog I/O — 35 35 35
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ

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133
MC74LVX4066
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
VCC Limit*
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V 25_C Unit
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
BW Maximum On–Channel Bandwidth fin = 1 MHz Sine Wave 4.5 150 MHz
or Adjust fin Voltage to Obtain 0 dBm at VOS 5.5 160
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Minimum Frequency Response Increase fin Frequency Until dB Meter Reads – 3 dB
RL = 50 Ω, CL = 10 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 5)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
— Off–Channel Feedthrough Isolation fin Sine Wave 4.5 – 50 dB
(Figure 6) Adjust fin Voltage to Obtain 0 dBm at VIS 5.5 – 50
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 37
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.5 – 37
v
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 7) RL = 600 Ω, CL = 50 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
RL = 10 kΩ, CL = 10 pF 4.5 50
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.5 100

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
— Crosstalk Between Any Two fin Sine Wave 4.5 – 70 dB
Switches Adjust fin Voltage to Obtain 0 dBm at VIS 5.5 – 70
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 12) fin = 10 kHz, RL = 600 Ω, CL = 50 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 80
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.5 – 80
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
THD Total Harmonic Distortion fin = 1 kHz, RL = 10 kΩ, CL = 50 pF %
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
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134
MC74LVX4066
250 400
350
Is = 1mA –55°C
200
300
25°C
250
Ron (Ohms)
Ron (Ohms)
150
200
85°C
100 Is = 5mA
150
125°C
Is = 9mA 100
50
50
Is = 15mA 0
0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
Vin (Volts) Vin (Volts)
Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25°C Figure 1b. Typical On Resistance, VCC = 2.0 V
35 20
18
30
16
125°C
25
14 85°C
Ron (Ohms)
25°C
Ron (Ohms)
20 12
125°C –55°C
10
85°C
15
25°C 8
–55°C 6
10
4
5
2
0 0
0 1 2 3 4 0 1 2 3 4 5
18
PLOTTER
16
14 125°C
85°C PROGRAMMABLE
12
25°C POWER MINI COMPUTER DC ANALYZER
Ron (Ohms)
10 SUPPLY
–55°C
8 – + VCC
6 DEVICE
UNDER TEST
4
2
0
0 1 2 3 4 5 6
Vin (Volts) GND
Figure 1e. Typical On Resistance, VCC = 5.5 V Figure 2. On Resistance Test Set–Up
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135
MC74LVX4066
VCC
VCC VCC
GND 14 VCC 14
A ON N/C
VCC A OFF GND

CONTROL CONTROL
7 INPUT 7 INPUT
VCC VOS VIS VCC VOS

14 14
fin ON fin OFF
dB dB
METER RL METER
SELECTED
CONTROL
SELECTED VCC INPUT
CONTROL
7 INPUT 7

VCC/2 VCC VCC/2
14
RL RL
VOS
OFF/ON IS
VCC
CL*
50%
SELECTED ANALOG IN
CONTROL GND
tr = tf = 3 ns
VCC
GND CONTROL
50%
ANALOG OUT

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136
MC74LVX4066
VCC tr tf
14 VCC
90%
ON POINT 10% GND
CL*
tPZL tPLZ
HIGH
IMPEDANCE
SELECTED VCC 50%
10% VOL
CONTROL
7 ANALOG
INPUT tPZH tPHZ
OUT
90% VOH
50%
IMPEDANCE
to Analog Out

1
14
RL VOS
2
VCC fin ON
VCC 14 1 kΩ 0.1 µF
1
TEST OFF
ON/OFF POINT
2 VCC OR GND
CL* RL CL* RL CL*
RL
SELECTED
SELECTED
CONTROL VCC/2 VCC/2
CONTROL
INPUT
INPUT
7
7
VCC/2
Test Set–Up
VCC
A
VIS
14 VCC VOS
0.1 µF TO
CL* METER
RL
SELECTED VCC/2
7 CONTROL SELECTED VCC
INPUT CONTROL
7
INPUT
ON/OFF CONTROL
Test Set–Up
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137
MC74LVX4066
0
– 20
– 30
– 40
dBm
– 50
DEVICE
– 60
SOURCE
– 70
– 80
– 90
1.0 2.0 3.0

FREQUENCY (kHz)
APPLICATION INFORMATION
The ON/OFF Control pins should be at VCC or GND logic Therefore, using the configuration in Figure 16, a maximum
levels, VCC being recognized as logic high and GND being analog signal of six volts peak–to–peak can be controlled.
below, the difference between VCC and GND is six volts.
VCC VCC
VCC = 6.0 V
14 Dx 16 Dx
+ 6.0 V + 6.0 V
ON ON
0V 0V
Dx Dx
SELECTED SELECTED
VCC
CONTROL CONTROL
INPUT INPUT
INPUTS INPUTS
7 (VCC OR GND) 7 (VCC OR GND)
Figure 16. 6.0 V Application Figure 17. Transient Suppressor Application
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138
MC74LVX4066
+5 V +5 V

R* R* R* R* LVX4066 LVXT4066
LSTTL/ LSTTL/
NMOS 5 NMOS/ 5
ABT/
6 CONTROL ALS 6 CONTROL
14 INPUTS 14 INPUTS
15 15
7 7
R* = 2 TO 10 kΩ
a. Using Pull-Up Resistors b. Using LVXT4066

Figure 18. LSTTL/NMOS to CMOS Interface
VDD = 5 V VCC = 2.0 TO 7.0 V
13 1 16 ANALOG 14 ANALOG
3 SIGNALS SIGNALS
5 LVX4066
7 MC14504 2 5
9 4 6 CONTROL
11 6 14 INPUTS
14 8 10 15 7
Figure 19. TTL/NMOS–to–CMOS Level Converter

Analog Signal Peak–to–Peak Greater than 5 V
1 OF 4
CHANNEL 4
SWITCHES
1 OF 4
CHANNEL 3
SWITCHES
COMMON I/O
1 OF 4
CHANNEL 2
SWITCHES
–
1 OF 4 OUTPUT
CHANNEL 1 1 OF 4
SWITCHES
EQUIVALENT
0.01 µF
1 2 3 4
CONTROL INPUTS
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139
MC74LVX4066
MARKING DIAGRAMS
(Top View)
14 13 12 11 10 9 8 14 13 12 11 10 9 8
LVX4066 LVX
4066
AWLYWW*
ALYW*
1 2 3 4 5 6 7 1 2 3 4 5 6 7
14–LEAD SOIC 14–LEAD TSSOP

D SUFFIX DT SUFFIX
CASE 751A CASE 948G
*See Applications Note #AND8004/D for date code and traceability information.
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140
MC74LVXT4066
Quad Analog Switch/

The MC74LVXT4066 utilizes silicon–gate CMOS technology to
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OFF–channel leakage current. This bilateral
switch/multiplexer/demultiplexer controls analog and digital voltages
that may vary across the full power–supply range (from VCC to GND).
The LVXT4066 is identical in pinout to the metal–gate CMOS
MC14066 and the high–speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
resistances (RON) are much more linear over input voltage than RON 14–LEAD SOIC 14–LEAD TSSOP
of metal–gate CMOS analog switches. D SUFFIX DT SUFFIX
CASE 751A CASE 948G
The ON/OFF control inputs are compatible with standard LSTTL
outputs. The input protection circuitry on this device allows
overvoltage tolerance on the ON/OFF control inputs, allowing the PIN CONNECTION AND
device to be used as a logic–level translator from 3.0V CMOS logic to MARKING DIAGRAM (Top View)
5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic
while operating at the higher–voltage power supply.
XA 1 14 VCC
The MC74LVXT4066 input structure provides protection when voltages A ON/OFF
up to 7V are applied, regardless of the supply voltage. This allows the YA 2 13 CONTROL
MC74LVXT4066 to be used to interface 5V circuits to 3V circuits. YB 3 12 D ON/OFF
CONTROL
• Fast Switching and Propagation Speeds XB
B ON/OFF
4 11 XD
• High ON/OFF Output Voltage Ratio CONTROL 5 10 YD
• Low Crosstalk Between Switches C ON/OFF

CONTROL
6 9 YC
• Diode Protection on All Inputs/Outputs GND 7 8 XC

• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 6.0 Volts
• Analog Input Voltage Range (VCC – GND) = 2.0 to 6.0 Volts
Diagram section on page 150 of this data sheet.
• Improved Linearity and Lower ON Resistance over Input Voltage
than the MC14016 or MC14066
• Low Noise
FUNCTION TABLE
LOGIC DIAGRAM
On/Off Control State of
1 2 Input Analog Switch
XA YA
13 L Off
A ON/OFF CONTROL
H On
4 3
XB YB
5 ANALOG
B ON/OFF CONTROL
OUTPUTS/INPUTS
8 9
XC YC ORDERING INFORMATION
6
C ON/OFF CONTROL Device Package Shipping
11 10
XD YD MC74LVXT4066D SOIC 55 Units/Rail
12
D ON/OFF CONTROL MC74LVXT4066DR2 SOIC 2500 Units/Reel
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD MC74LVXT4066DT TSSOP 96 Units/Rail

PIN 14 = VCC
MC74LVXT4066DTR2 TSSOP 2500 Units/Reel
PIN 7 = GND

March, 2000 – Rev. 1 MC74LVXT4066/D
MC74LVXT4066
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current Into or Out of Any Pin –20 mA voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, SOIC Package† 500 mW cuit. For proper operation, Vin and
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TSSOP Package† 450
_C
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 Unused inputs must always be
TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C
*Maximum Ratings are those values beyond which damage to the device may occur. Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions. I/O pins must be connected to a
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C properly terminated line or bus.
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
Vin
ÎÎÎÎÎ
ÎÎÎ
Analog Input Voltage (Referenced to GND)
ÎÎ
ÎÎÎ
GND
GND
VCC
VCC
V
V
ÎÎÎÎ
VIO*
ÎÎÎÎ ÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎ
Operating Temperature, All Package Types
—
– 55
1.2
+ 85
V
_C
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎ
Input Rise and Fall Time, ON/OFF Control
ÎÎÎ ÎÎÎ
ns/V
ÎÎ
Inputs (Figure 10) VCC = 3.3 V ± 0.3 V 0 100
VCC = 5.0 V ± 0.5 V 0 20
exceeded.
ÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
VCC – 55 to
ÎÎÎÎ
Symbol
VIH ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
v
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Parameter
ÎÎÎ
Test Conditions
Ron = Per Spec
V
3.0
25_C
1.2
85_C
1.2
125_C
1.2
Unit
V
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Note 1) 5.5 2.0 2.0 2.0
ÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ
(Note 1)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Low–Level Voltage
ÎÎÎ
Ron = Per Spec 3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
ÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Maximum Input Leakage Current
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 5.5 4.0 40 160 µA
Current (per Package) VIO = 0 V
3. Specifications are for design target only. Not final specification limits.
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142
MC74LVXT4066
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
v v V 25_C 85_C 125_C
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VIS = VCC to GND
IS 2.0 mA (Figures 1, 2)
3.0
4.5
5.5
40
25
20
45
28
25
50
35
30
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIH
2.0
3.0
—
30
—
35
—
40
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
IS 2.0 mA (Figures 1, 2) 4.5 25 28 35
5.5 20 25 30
ÎÎÎÎ
∆Ron
ÎÎÎÎÎÎÎÎÎÎv ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Vin = VIH
IS 2.0 mA
3.0
4.5
5.5
15
10
10
20
12
12
25
15
15
Ω
ÎÎÎÎ
ÎÎÎÎ
Ioff
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL
VIO = VCC or GND
5.5 0.1 0.5 1.0 µA
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
(Figure 4)
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ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
VCC – 55 to
ÎÎÎÎÎ
tPLH,
ÎÎÎÎÎ ÎÎÎÎ
tPHL ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
(Figures 8 and 9)
2.0
3.0
4.5
4.0
3.0
1.0
6.0
5.0
2.0
8.0
6.0
2.0
ns
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎ
tPLZ, ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
5.5
2.0
1.0
30
2.0
35
2.0
40 ns
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPHZ (Figures 10 and 11) 3.0 20 25 30
4.5 15 18 22
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
5.5 15 18 20
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
tPZH (Figures 10 and 1 1) 3.0 12 14 15
4.5 8.0 10 12
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
5.5 8.0 10 12
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
C Maximum Capacitance ON/OFF Control Input — 10 10 10 pF
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
Control Input = GND
Analog I/O — 35 35 35
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ

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MC74LVXT4066
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
VCC Limit*
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V 25_C Unit
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
BW Maximum On–Channel Bandwidth fin = 1 MHz Sine Wave 4.5 150 MHz
or Minimum Frequency Response Adjust fin Voltage to Obtain 0 dBm at VOS 5.5 160
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 5) Increase fin Frequency Until dB Meter Reads – 3 dB
RL = 50 Ω, CL = 10 pF
ÎÎÎÎ
ÎÎÎÎ
—

(Figure 6)ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Off–Channel Feedthrough Isolation fin Sine Wave
4.5
5.5
– 50
– 50
dB
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 37
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.5 – 37
v
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 7) RL = 600 Ω, CL = 50 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
RL = 10 kΩ, CL = 10 pF 4.5 50
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.5 100

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
— Crosstalk Between Any Two fin Sine Wave 4.5 – 70 dB
Switches Adjust fin Voltage to Obtain 0 dBm at VIS 5.5 – 70
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Figure 12) fin = 10 kHz, RL = 600 Ω, CL = 50 pF
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF 4.5 – 80
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
5.5 – 80
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
THD Total Harmonic Distortion fin = 1 kHz, RL = 10 kΩ, CL = 50 pF %
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
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144
MC74LVXT4066
250 400
350
Is = 1mA –55°C
200
300
25°C
250
Ron (Ohms)
Ron (Ohms)
150
200
85°C
100 Is = 5mA
150
125°C
Is = 9mA 100
50
50
Is = 15mA 0
0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25°C Figure 1b. Typical On Resistance, VCC = 2.0 V
35 25
30
20
25
125°C
Ron (Ohms)
Ron (Ohms)
20 15
125°C 85°C
85°C 25°C
15
25°C 10 –55°C
–55°C
10
5
5
0 0
0 1 2 3 4 0 1 2 3 4 5
18
PLOTTER
16
14 125°C
85°C PROGRAMMABLE
12 25°C POWER MINI COMPUTER DC ANALYZER
Ron (Ohms)
10 SUPPLY
–55°C
8 – + VCC
DEVICE
6
UNDER TEST
4
2 ANALOG IN COMMON OUT

0
0 1 2 3 4 5 6
GND
Vin (Volts)
Figure 1e. Typical On Resistance, VCC = 5.5 V Figure 2. On Resistance Test Set–Up
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145
MC74LVXT4066
VCC
VCC VCC
GND 14 VCC 14
A ON N/C
VCC A OFF GND

CONTROL CONTROL
7 INPUT 7 INPUT
VCC VOS VIS VCC VOS

14 14
fin ON fin OFF
dB dB
METER RL METER
SELECTED
CONTROL
SELECTED VCC INPUT
CONTROL
7 INPUT 7

VCC/2 VCC VCC/2
14
RL RL
VOS
OFF/ON IS
VCC
CL*
50%
SELECTED ANALOG IN
CONTROL GND
tr = tf = 3 ns
VIH
VIL CONTROL
50%
ANALOG OUT

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146
MC74LVXT4066
VCC tr tf
14 VCC
90%
ON POINT 10% GND
CL*
tPZL tPLZ
HIGH
IMPEDANCE
SELECTED VIH 50%
10% VOL
CONTROL
7 ANALOG
INPUT tPZH tPHZ
OUT
90% VOH
50%
IMPEDANCE
to Analog Out

1
14
RL VOS
2
VCC fin ON
VCC 14 1 kΩ 0.1 µF
1
TEST OFF
ON/OFF POINT
2 VIH OR VIL
CL* RL CL* RL CL*
RL
VIH SELECTED
SELECTED
CONTROL VCC/2 VCC/2
VIL CONTROL
INPUT
INPUT
7
7
VCC/2
Test Set–Up
VCC
A
VIS
14 VCC VOS
0.1 µF TO
CL* METER
RL
SELECTED VCC/2
7 CONTROL SELECTED VIH
INPUT CONTROL
7
VIH INPUT
VIL ON/OFF CONTROL
Test Set–Up
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147
MC74LVXT4066
0
– 20
– 30
– 40
dBm
– 50
DEVICE
– 60
SOURCE
– 70
– 80
– 90
1.0 2.0 3.0

FREQUENCY (kHz)
APPLICATION INFORMATION
The ON/OFF Control pins should be at VIH or VIL logic Therefore, using the configuration in Figure 16, a maximum
levels, VIH being recognized as logic high and VIL being analog signal of six volts peak–to–peak can be controlled.
below, the difference between VCC and GND is six volts.
VCC VCC
VCC = 6.0 V
14 Dx 16 Dx
+ 6.0 V + 6.0 V
ON ON
0V 0V
Dx Dx
SELECTED SELECTED
VIH VIH
CONTROL CONTROL
INPUT INPUT
INPUTS INPUTS
7 (VIH OR VIL) 7 (VIH OR VIL)
Figure 16. 6.0 V Application Figure 17. Transient Suppressor Application
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148
MC74LVXT4066
+3 V +5 V
+3V 14 +3V 14
GND GND
LVXT4066 LVXT4066
LSTTL/
5 NMOS/ 5
1.8 – 2.5V ABT/
CIRCUITRY 6 CONTROL ALS 6 CONTROL
14 INPUTS 14 INPUTS
15 15
7 7
R* = 2 TO 10 kΩ
a. Low Voltage Logic Level Shifting Control b. Using LVXT4066

Figure 18. Low Voltage CMOS Interface
1 OF 4
CHANNEL 4
SWITCHES
1 OF 4
CHANNEL 3
SWITCHES
COMMON I/O
1 OF 4
CHANNEL 2
SWITCHES
–
1 OF 4 OUTPUT
CHANNEL 1 1 OF 4
SWITCHES
EQUIVALENT
0.01 µF
1 2 3 4
CONTROL INPUTS
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149
MC74LVXT4066
MARKING DIAGRAMS
(Top View)
14 13 12 11 10 9 8 14 13 12 11 10 9 8
LVXT4066 LVXT
4066
AWLYWW*
ALYW*
1 2 3 4 5 6 7 1 2 3 4 5 6 7

D SUFFIX DT SUFFIX
CASE 751A CASE 948G
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150
MC74LVX8051
Demultiplexer
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(from VCC to GND).
The LVX8051 is similar in pinout to the high–speed HC4051A and
which one of the Analog Inputs/Outputs is to be connected, by means 16–LEAD SOIC 16–LEAD TSSOP
of an analog switch, to the Common Output/Input. When the Enable D SUFFIX DT SUFFIX
CASE 751B CASE 948F
pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard PIN CONNECTION AND
CMOS outputs; with pull–up resistors they are compatible with MARKING DIAGRAM (Top View)
LSTTL outputs.
VCC X2 X1 X0 X3 A B C
16 15 14 13 12 11 10 9
switches.
• Diode Protection on All Inputs/Outputs 1 2 3 4 5 6 7 8
• Analog Power Supply Range (VCC – GND) = 2.0 to 6.0 V X4 X6 X X7 X5 Enable NC GND
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V For detailed package marking information, see the Marking
Counterparts
• Low Noise FUNCTION TABLE – MC74LVX8051
• In Compliance With the Requirements of JEDEC Standard No. 7A Control Inputs
• Chip Complexity: LVX8051 — 184 FETs or 46 Equivalent Gates Select
LOGIC DIAGRAM L L L L X0
MC74LVX8051 L L L H X1
L L H L X2
L L H H X3
L H L L X4
13
X0 L H L H X5
14 L H H L X6
X1
15 L H H H X7
X2 3 COMMON
ANALOG 12 X H X X X NONE
INPUTS/ X3
OUTPUTS X4 1 DEMULTIPLEXER INPUT X = Don’t Care
5
X5
2
X6 ORDERING INFORMATION
4
X7
11 Device Package Shipping
A
CHANNEL 10
SELECT B MC74LVX8051D SOIC 48 Units/Rail
INPUTS 9
C
6 MC74LVX8051DR2 SOIC 2500 Units/Reel
ENABLE
PIN 16 = VCC
MC74LVX8051DT TSSOP 96 Units/Rail
PIN 8 = GND
MC74LVX8051DTR2 TSSOP 2500 Units/Reel

MC74LVX8051
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
VIS Analog Input Voltage – 0.5 to VCC + 0.5 V fields. However, precautions must
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current, Into or Out of Any Pin ± 20 mA voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
PD Power Dissipation in Still Air, SOIC Package† 500 mW
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature Range – 65 to + 150 _C Unused inputs must always be
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C level (e.g., either GND or V CC ).
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
Symbol
ÎÎÎÎ
VCC
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
Parameter
Positive DC Supply Voltage (Referenced to GND)
Min
2.0
Max
6.0
Unit
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
0.0 VCC V
ÎÎÎÎ
Vin
VIO*
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
GND VCC
1.2
V
V
ÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ns/V
ÎÎ
VCC = 3.3 V ± 0.3 V 0 100
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 5.0 V ± 0.5 V 0 20
exceeded.
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MC74LVX8051
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND)

Guaranteed Limit
VCC
Enable Inputs 4.5 3.15 3.15 3.15
5.5 3.85 3.85 3.85
Enable Inputs 4.5 1.35 1.35 1.35
5.5 1.65 1.65 1.65
Iin Maximum Input Leakage Current, Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA
Channel–Select or Enable Inputs
ICC Maximum Quiescent Supply Channel Select, Enable and 5.5 4.0 40 160 µA
Current (per Package) VIS = VCC or GND;
VIO = 0 V
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Ron Maximum “ON” Resistance Vin = VIL or VIH 3.0 40 45 50 Ω
VIS = VCC to GND 4.5 30 32 37
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
|IS| 10.0 mA (Figures 1, 2)
Vin = VIL or VIH
5.5
3.0
25
30
28
35
30
40
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VIS = VCC or GND (Endpoints) 4.5 25 28 35
v |IS| 10.0 mA (Figures 1, 2) 5.5 20 25 30
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆Ron
v ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL or VIH
|IS| 10.0 mA
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
Ω
Ioff Maximum Off–Channel Leakage Vin = VIL or VIH; 5.5 0.1 0.5 1.0 µA
Current, Any One Channel VIO = VCC or GND;
Maximum Off–Channel Vin = VIL or VIH; 5.5 0.2 2.0 4.0
Leakage Current, VIO = VCC or GND;
Common Channel Switch Off (Figure 4)
Ion Maximum On–Channel Vin = VIL or VIH; 5.5 0.2 2.0 4.0 µA
Leakage Current, Switch–to–Switch =
Channel–to–Channel VCC or GND; (Figure 5)
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153
MC74LVX8051

Guaranteed Limit
VCC
tPHL (Figure 9) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPLH, Maximum Propagation Delay, Analog Input to Analog Output 2.0 4.0 6.0 8.0 ns
tPHL (Figure 10) 3.0 3.0 5.0 6.0
4.5 1.0 2.0 2.0
5.5 1.0 2.0 2.0
tPHZ (Figure 11) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPZH (Figure 11) 3.0 12 14 15
4.5 8.0 10 12
5.5 8.0 10 12
(All Switches Off) Common O/I 130 130 130
CPD Typical @ 25°C, VCC = 5.0 V pF
Power Dissipation Capacitance (Figure 13)* 45

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154
MC74LVX8051

Limit*
VCC
Symbol Parameter Condition V 25°C Unit
BW Maximum On–Channel Bandwidth fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain MHz
or Minimum
Mi i Frequency
F Response
R 0dB att VOS; IIncrease fin Frequency
0dBm F Until
U til dB
3.0 80
(Figure 6) Meter Reads –3dB;
4.5 80
RL = 50Ω, CL = 10pF
5.5 80
— Off–Channel Feedthrough Isolation fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm 3.0 –50 dB
(Figure 7) at VIS 4.5 –50
fin = 10kHz, RL = 600Ω, CL = 50pF 5.5 –50
3.0 –37
4.5 –37
fin = 1.0MHz, RL = 50Ω, CL = 10pF 5.5 –37
— Feedthrough Noise. Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL 3.0 25 mVPP
Channel–Select Input to Common at Setup so that IS = 0A; 4.5 105
I/O (Figure 8) Enable = GND RL = 600Ω, CL = 50pF 5.5 135
3.0 35
4.5 145
RL = 10kΩ, CL = 10pF 5.5 190
VIS = 2.0VPP sine wave 3.0 0.10
40
35
30
25 125°C
85°C
20 25°C
– 55°C
15
10
00 1.0 2.0 3.0 4.0

VIN, INPUT VOLTAGE (VOLTS)
Figure 1a. Typical On Resistance, VCC = 3.0 V
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155
MC74LVX8051
30 25
25 125°C

20
85°C
125°C
20 85°C 25°C
25°C 15 – 55°C
15 – 55°C
10
10
5 5
0 0
0 1.0 2.0 3.0 4.0 5.0 0 1.0 2.0 3.0 4.0 5.0 6.0
VIN, INPUT VOLTAGE (VOLTS) VIN, INPUT VOLTAGE (VOLTS)
Figure 1b. Typical On Resistance, VCC = 4.5 V Figure 1c. Typical On Resistance, VCC = 5.5 V
PLOTTER
PROGRAMMABLE
SUPPLY
– + VCC
DEVICE
UNDER TEST
GND GND
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156
MC74LVX8051
VCC VCC
VCC VCC
GND 16 GND 16
ANALOG I/O
OFF OFF
VCC A VCC
VIH 6 VIH 6
8 8
VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
GND N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O
VIL 6 6
8 8

VIS VCC VOS VCC

0.1µF 16 dB 16
RL
TEST
POINT
OFF/ON RL CL*
RL
6 6
VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 3 ns
VCC
VIL or VIH GND
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157
MC74LVX8051
VCC
VCC
16
VCC
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL
6
ANALOG
OUT 50%
8
CHANNEL SELECT
VCC
16
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
ANALOG 8
OUT 50%

90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG
OUT 50% 8
HIGH
IMPEDANCE
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158
MC74LVX8051
VCC
VIS A
VCC
16 16
RL VOS
ANALOG I/O NC
0.1µF OFF/ON
OFF
RL CL* RL CL* VCC
RL 6
6 8 11
8 CHANNEL SELECT
0
VIS
0.1µF 16 – 20
TO
RL METER
CL* – 40
dB
– 50
DEVICE
– 60
6 SOURCE
– 70
8 – 80
*Includes all probe and jig capacitance – 90

– 100
1.0 2.0 3.125
FREQUENCY (kHz)
The Channel Select and Enable control pins should be at connected). However, tying unused analog inputs and
VCC or GND logic levels. VCC being recognized as a logic outputs to VCC or GND through a low value resistor helps
high and GND being recognized as a logic low. In this minimize crosstalk and feedthrough noise that may be
example: picked up by an unused switch.
VCC = +5V = logic high Although used here, balanced supplies are not a
GND = 0V = logic low requirement. The only constraints on the power supplies are
The maximum analog voltage swing is determined by the that:
supply voltage VCC. The positive peak analog voltage VCC – GND = 2 to 6 volts
should not exceed VCC. Similarly, the negative peak analog When voltage transients above VCC and/or below GND
voltage should not go below GND. In this example, the are anticipated on the analog channels, external Germanium
difference between VCC and GND is five volts. Therefore, or Schottky diodes (Dx) are recommended as shown in
using the configuration of Figure 15, a maximum analog Figure 16. These diodes should be able to absorb the
signal of five volts peak–to–peak can be controlled. Unused maximum anticipated current surges during clipping.
analog inputs/outputs may be left floating (i.e., not
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MC74LVX8051
VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
0V SIGNAL SIGNAL 0V
Dx Dx
GND GND
10 CIRCUITRY 0 to 5V

+5V +5V
+5V 16 +5V +5V 16 +5V

ON/OFF ON/OFF
GND SIGNAL SIGNAL GND GND SIGNAL SIGNAL GND
+5V
*
R R R +5V
6 11 6 11
10 10
CIRCUITRY CIRCUITRY
8 9 8 9
* 2K ≤ R ≤ 10K VHCT1GT50
BUFFERS
11 LEVEL 13
A X0
SHIFTER
14
X1
10 LEVEL 15
B X2
SHIFTER
12
X3
9 LEVEL 1
C X4
SHIFTER
5
X5
6 LEVEL 2
ENABLE X6
SHIFTER
4
X7
3
X
Figure 18. Function Diagram, LVX8051
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160
MC74LVX8051
MARKING DIAGRAMS
(Top View)
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
LVX8051 LVX
8051
AWLYWW*
ALYW*
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

D SUFFIX DT SUFFIX
CASE 751B CASE 948F
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161
MC74LVXT8051
Demultiplexer
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(from VCC to GND).
The LVXT8051 is similar in pinout to the high–speed HC4051A
and the metal–gate MC14051B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected by means 16–LEAD SOIC 16–LEAD TSSOP
of an analog switch to the Common Output/Input. When the Enable D SUFFIX DT SUFFIX
CASE 751B CASE 948F
The Channel–Select and Enable inputs are compatible with PIN CONNECTION AND
TTL–type input thresholds. The input protection circuitry on this MARKING DIAGRAM (Top View)
device allows overvoltage tolerance on the input, allowing the device
VCC X2 X1 X0 X3 A B C
to be used as a logic–level translator from 3.0V CMOS logic to 5.0V
16 15 14 13 12 11 10 9
CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while
operating at the higher–voltage power supply.
The MC74LVXT8051 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74LVXT8051 to be used to interface 5V circuits to 3V circuits.
This device has been designed so that the ON resistance (Ron) is more 1 2 3 4 5 6 7 8
linear over input voltage than Ron of metal–gate CMOS analog switches. X4 X6 X X7 X5 Enable NC GND
• Fast Switching and Propagation Speeds Diagram section on page 172 of this data sheet.
• Diode Protection on All Inputs/Outputs
FUNCTION TABLE – MC74LVXT8051
Control Inputs
Select
• Improved Linearity and Lower ON Resistance Than Metal–Gate Enable C B A ON Channels
Counterparts L L L L X0
• Low Noise L L L H X1
• In Compliance With the Requirements of JEDEC Standard No. 7A L
L
L
L
H
H
L
H
X2
X3
L H L L X4
LOGIC DIAGRAM L H L H X5
MC74LVXT8051 L H H L X6
Single–Pole, 8–Position Plus Common Off L H H H X7
13
H X X X NONE
X0
14 X = Don’t Care
X1
15
X2 3 COMMON
ANALOG 12 X
MULTIPLEXER/ OUTPUT/ ORDERING INFORMATION
INPUTS/ X3
OUTPUTS X4 1 DEMULTIPLEXER INPUT
5 Device Package Shipping
X5
2
X6 MC74LVXT8051D SOIC 48 Units/Rail
4
X7
11 MC74LVXT8051DR2 SOIC 2500 Units/Reel
A
CHANNEL 10 MC74LVXT8051DT TSSOP 96 Units/Rail
SELECT B
INPUTS 9
C PIN 16 = VCC MC74LVXT8051DTR2 TSSOP 2500 Units/Reel
6 PIN 8 = GND
ENABLE

MC74LVXT8051
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current, Into or Out of Any Pin –20 mA voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
Symbol
ÎÎÎÎ
VCC
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
Parameter
Min
2.0
Max
6.0
Unit
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
0.0 VCC V
ÎÎÎÎ
Vin
VIO*
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
GND VCC
1.2
V
V
ÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ns/V
ÎÎ
VCC = 3.3 V ± 0.3 V 0 100
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 5.0 V ± 0.5 V 0 20
exceeded.
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163
MC74LVXT8051

Guaranteed Limit
VCC
Enable Inputs 5.5 2.0 2.0 2.0
Iin Maximum Input Leakage Current, Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA
ICC Maximum Quiescent Supply Channel Select, Enable and 5.5 4 40 160 µA
Current (per Package) VIS = VCC or GND; VIO = 0 V
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Guaranteed Limit
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VIS = VCC to GND 4.5 30 32 37
v |IS| 10.0 mA (Figures 1, 2) 5.5 25 28 30
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin = VIL or VIH
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆Ron
v
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL or VIH
|IS| 10.0 mA
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
Ω
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164
MC74LVXT8051

Guaranteed Limit
VCC
tPHL (Figure 9) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPHL (Figure 10) 3.0 3.0 5.0 6.0
4.5 1.0 2.0 2.0
5.5 1.0 2.0 2.0
tPHZ (Figure 11) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPZH (Figure 11) 3.0 12 14 15
4.5 8.0 10 12
5.5 8.0 10 12

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165
MC74LVXT8051

Limit*
VCC
or Minimum
Mi i Frequency
F Response
0dBm F Until
U til dB
3.0 80
4.5 80
RL = 50Ω, CL = 10pF
5.5 80
fin = 10kHz, RL = 600Ω, CL = 50pF 5.5 –50
3.0 –37
4.5 –37
fin = 1.0MHz, RL = 50Ω, CL = 10pF 5.5 –37
3.0 35
4.5 145
RL = 10kΩ, CL = 10pF 5.5 190
— Crosstalk Between Any Two fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm 3.0 –50 dB
Switches (Figure 12) at VIS 4.5 –50
fin = 10kHz, RL = 600Ω, CL = 50pF 5.5 –50
3.0 –60
4.5 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 5.5 –60
40
35
30
25 125°C
85°C
20
25°C
– 55°C
15
10
00 1.0 2.0 3.0 4.0

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166
MC74LVXT8051
30 25
25 125°C

20
85°C
125°C
20 85°C 25°C
25°C 15
– 55°C
15 – 55°C
10
10
5 5
0 0
0 1.0 2.0 3.0 4.0 5.0 0 1.0 2.0 3.0 4.0 5.0 6.0
PLOTTER
PROGRAMMABLE
SUPPLY
– + VCC
DEVICE
UNDER TEST
GND GND
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167
MC74LVXT8051
VCC VCC
VCC VCC
GND 16 GND 16
ANALOG I/O
OFF OFF
VCC A VCC
VIH 6 VIH 6
8 8
VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
GND N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O
VIL 6 6
8 8

VIS VCC VOS VCC

0.1µF 16 dB 16
RL
TEST
POINT
OFF/ON RL CL*
RL
6 6
VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 3 ns
VIH
VIL or VIH VIL
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168
MC74LVXT8051
VCC
VCC
16
VCC
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL
6
ANALOG
OUT 50%
8
CHANNEL SELECT
VCC
16
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
ANALOG 8
OUT 50%

90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ VIH
ENABLE
VIL 6
90% VOH
ANALOG
OUT 50% 8
HIGH
IMPEDANCE
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169
MC74LVXT8051
VCC
VIS A
VCC
16 16
RL VOS
ANALOG I/O NC
0.1µF OFF/ON
OFF
RL CL* RL CL* VCC
RL 6
6 8 11
8 CHANNEL SELECT
0
VIS
0.1µF 16 – 20
TO
RL METER
CL* – 40
dB
– 50
DEVICE
– 60
6 SOURCE
– 70
8 – 80

– 100
1.0 2.0 3.125
FREQUENCY (kHz)
supply voltage VCC. The positive peak analog voltage VCC – GND = 2 to 6 volts
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170
MC74LVXT8051
VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
0V SIGNAL SIGNAL 0V
Dx Dx
GND GND
6 11 TO EXTERNAL LSTTL COMPATIBLE

10 CIRCUITRY 0 to VIH

+3V +5V
+3V 16 +3V +5V 16 +5V

ON/OFF ON/OFF
GND SIGNAL SIGNAL GND GND SIGNAL SIGNAL GND
+5V
6 11 6 11
1.8V – 2.5V 1.8V – 2.5V
10 10
CIRCUITRY CIRCUITRY
8 9 8 9
MC74VHCT1GT50 BUFFERS
VCC = 3.0V
a. Low Voltage Logic Level Shifting Control b. 2–Stage Logic Level Shifting Control
Figure 17. Interfacing to Low Voltage CMOS Outputs
11 LEVEL 13
A X0
SHIFTER
14
X1
10 LEVEL 15
B X2
SHIFTER
12
X3
9 LEVEL 1
C X4
SHIFTER
5
X5
6 LEVEL 2
ENABLE X6
SHIFTER
4
X7
3
X
Figure 18. Function Diagram, LVXT8051
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171
MC74LVXT8051
MARKING DIAGRAMS
(Top View)
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
LVXT8051 LVXT
8051
AWLYWW*
ALYW*
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

D SUFFIX DT SUFFIX
CASE 751B CASE 948F
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172
MC74LVX8053
Demultiplexer
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(from VCC to GND).
The LVX8053 is similar in pinout to the high–speed HC4053A, and
which one of the Analog Inputs/Outputs is to be connected, by means 16–LEAD SOIC 16–LEAD TSSOP
of an analog switch, to the Common Output/Input. When the Enable D SUFFIX DT SUFFIX
CASE 751B CASE 948F
The Channel–Select and Enable inputs are compatible with standard PIN CONNECTION AND
CMOS outputs; with pull–up resistors they are compatible with MARKING DIAGRAM (Top View)
LSTTL outputs.
VCC Y X X1 X0 A B C
more linear over input voltage than Ron of metal–gate CMOS analog 16 15 14 13 12 11 10 9
switches.
• Diode Protection on All Inputs/Outputs 1 2 3 4 5 6 7 8
• Analog Power Supply Range (VCC – GND) = 2.0 to 6.0 V Y1 Y0 Z1 Z Z0 Enable NC GND
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V For detailed package marking information, see the Marking
Counterparts
FUNCTION TABLE – MC74LVX8053
• Low Noise
• In Compliance With the Requirements of JEDEC Standard No. 7A Control Inputs
• Chip Complexity: LVX8053 — 156 FETs or 39 Equivalent Gates Select

LOGIC DIAGRAM L L L L Z0 Y0 X0
Triple Single–Pole, Double–Position Plus Common Off L L L H Z0 Y0 X1
L L H L Z0 Y1 X0
12 L L H H Z0 Y1 X1
X0 14
13 X SWITCH X L H L L Z1 Y0 X0
X1 L H L H Z1 Y0 X1
L H H L Z1 Y1 X0
2 L H H H Z1 Y1 X1
Y0 15 COMMON
ANALOG 1 Y SWITCH Y H X X X NONE
X = Don’t Care
5
Z0 4
3 Z SWITCH Z
Z1 ORDERING INFORMATION
11
A Device Package Shipping
INPUTS B
9 PIN 8 = GND MC74LVX8053D SOIC 48 Units/Rail
C
6
ENABLE MC74LVX8053DR2 SOIC 2500 Units/Reel
MC74LVX8053DT TSSOP 96 Units/Rail
the Y–Switch and Input C controls the Z–Switch MC74LVX8053DTR2 TSSOP 2500 Units/Reel

MC74LVX8053
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current, Into or Out of Any Pin ± 20 mA voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
Symbol
ÎÎÎÎ
VCC
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
Parameter
Min
2.0
Max
6.0
Unit
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
0.0 VCC V
ÎÎÎÎ
Vin
VIO*
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
GND VCC
1.2
V
V
ÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ns/V
ÎÎ
VCC = 3.3 V ± 0.3 V 0 100
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 5.0 V ± 0.5 V 0 20
exceeded.
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174
MC74LVX8053

Guaranteed Limit
VCC
Enable Inputs 4.5 3.15 3.15 3.15
5.5 3.85 3.85 3.85
Enable Inputs 4.5 1.35 1.35 1.35
5.5 1.65 1.65 1.65
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
v ÎÎÎ
Guaranteed Limit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VCC – 55 to
Symbol v
Parameter Test Conditions V 25_C 85_C 125_C Unit
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Ron
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum “ON” Resistance
ÎÎÎ
Vin = VIL or VIH
VIS = VCC to GND
3.0
4.5
5.5
40
30
25
45
32
28
50
37
30
Ω
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin = VIL or VIH
3.0
4.5
30
25
35
28
40
35
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
|IS| 10.0 mA (Figures 1, 2) 5.5 20 25 30
∆Ron Ω
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Difference in “ON” Vin = VIL or VIH 3.0 15 20 25
Resistance Between Any Two VIS = 1/2 (VCC – GND) 4.5 8.0 12 15
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Channels in the Same Package |IS| 10.0 mA 5.5 8.0 12 15
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175
MC74LVX8053

Guaranteed Limit
VCC
tPHL (Figure 9) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPHL (Figure 10) 3.0 3.0 5.0 6.0
4.5 1.0 2.0 2.0
5.5 1.0 2.0 2.0
tPHZ (Figure 11) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPZH (Figure 11) 3.0 12 14 15
4.5 8.0 10 12
5.5 8.0 10 12

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176
MC74LVX8053

Limit*
VCC
or Minimum
Mi i Frequency
F Response
0dBm F Until
U til dB
3.0 120
4.5 120
RL = 50Ω, CL = 10pF
5.5 120
fin = 10kHz, RL = 600Ω, CL = 50pF 5.5 –50
3.0 –37
4.5 –37
fin = 1.0MHz, RL = 50Ω, CL = 10pF 5.5 –37
3.0 35
4.5 145
RL = 10kΩ, CL = 10pF 5.5 190
fin = 10kHz, RL = 600Ω, CL = 50pF 5.5 –50
3.0 –60
4.5 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 5.5 –60
45
40
35
30
125°C
25 85°C
25°C
20
– 55°C
15
10
5
00 1.0 2.0 3.0 4.0

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177
MC74LVX8053
30 30
25 25

125°C 125°C
85°C 85°C
20 25°C 20
25°C
15 – 55°C
15 – 55°C
10 10
5 5
0 0
0 1.0 2.0 3.0 4.0 5.0 0 1.0 2.0 3.0 4.0 5.0 6.0
PLOTTER
PROGRAMMABLE
SUPPLY
– + VCC
DEVICE
UNDER TEST
GND GND
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178
MC74LVX8053
VCC VCC
VCC VCC
GND 16 GND 16
ANALOG I/O
OFF OFF
VCC A VCC
VIH 6 VIH 6
8 8
VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
GND N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O
VIL 6 6
8 8

VIS VCC VOS VCC

0.1µF 16 dB 16
RL
TEST
POINT
OFF/ON RL CL*
RL
6 6
VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 3 ns
VCC
VIL or VIH GND
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179
MC74LVX8053
VCC
VCC
16
VCC
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL
6
ANALOG
OUT 50%
8
CHANNEL SELECT
VCC
16
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
ANALOG 8
OUT 50%

90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ
ENABLE
VOH 6
90%
ANALOG
OUT 50% 8
HIGH
IMPEDANCE
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180
MC74LVX8053
VCC
VIS A
VCC
16 16
RL VOS
ANALOG I/O NC
0.1µF OFF/ON
OFF
RL CL* RL CL* VCC
RL 6
6 8 11
8 CHANNEL SELECT
0
VIS
0.1µF 16 – 20
TO
RL METER
CL* – 40
dB
– 50
DEVICE
– 60
6 SOURCE
– 70
8 – 80

– 100
1.0 2.0 3.125
FREQUENCY (kHz)
supply voltages VCC. The positive peak analog voltage VCC – GND = 2 to 6 volts
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181
MC74LVX8053
VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
0V SIGNAL SIGNAL 0V
Dx Dx
VEE VEE
10 CIRCUITRY 0 to 5V

+5V +5V
+5V 16 +5V +5V 16 +5V

ON/OFF ON/OFF
SIGNAL SIGNAL SIGNAL SIGNAL
GND GND GND GND
+5V
*
R R R +5V
6 11 6 11
10 10
CIRCUITRY CIRCUITRY
8 9 8 9
* 2K ≤ R ≤ 10K VHC1GT50
BUFFERS
11 LEVEL 13
A X1
SHIFTER
12
X0
14
X
10 LEVEL 1
B Y1
SHIFTER
2
Y0
15
Y
9 LEVEL 3
C Z1
SHIFTER
5
Z0
4
Z
6 LEVEL
ENABLE
SHIFTER
Figure 18. Function Diagram, LVX8053
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182
MC74LVX8053
MARKING DIAGRAMS
(Top View)
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
LVX8053 LVX
8053
AWLYWW*
ALYW*
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

D SUFFIX DT SUFFIX
CASE 751B CASE 948F
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183
MC74LVXT8053
Demultiplexer
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(from VCC to GND).
The LVXT8053 is similar in pinout to the high–speed HC4053A,
and the metal–gate MC14053B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected by means 16–LEAD SOIC 16–LEAD TSSOP
of an analog switch to the Common Output/Input. When the Enable D SUFFIX DT SUFFIX
CASE 751B CASE 948F
The Channel–Select and Enable inputs are compatible with PIN CONNECTION AND
TTL–type input thresholds. The input protection circuitry on this MARKING DIAGRAM (Top View)
device allows overvoltage tolerance on the input, allowing the device VCC Y X X1 X0 A B C
to be used as a logic–level translator from 3.0V CMOS logic to 5.0V 16 15 14 13 12 11 10 9
CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while
operating at the higher–voltage power supply.
The MC74LVXT8053 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74LVXT8053 to be used to interface 5V circuits to 3V circuits.
1 2 3 4 5 6 7 8
This device has been designed so that the ON resistance (Ron) is more
Y1 Y0 Z1 Z Z0 Enable NC GND
linear over input voltage than Ron of metal–gate CMOS analog switches.
• Fast Switching and Propagation Speeds Diagram section on page 194 of this data sheet.
• Diode Protection on All Inputs/Outputs FUNCTION TABLE – MC74LVXT8053
• Analog Power Supply Range (VCC – GND) = 2.0 to 6.0 V Control Inputs
Select
• Improved Linearity and Lower ON Resistance Than Metal–Gate Enable C B A ON Channels
Counterparts L L L L Z0 Y0 X0
• Low Noise L L L H Z0 Y0 X1
• In Compliance With the Requirements of JEDEC Standard No. 7A L
L
L
L
H
H
L
H
Z0
Z0
Y1
Y1
X0
X1
LOGIC DIAGRAM L H L L Z1 Y0 X0
Triple Single–Pole, Double–Position Plus Common Off L H L H Z1 Y0 X1
12 L H H L Z1 Y1 X0
X0 14
13 X SWITCH X L H H H Z1 Y1 X1
X1 H X X X NONE
2 X = Don’t Care
ANALOG Y0 15 COMMON
1 Y SWITCH Y
5 ORDERING INFORMATION
Z0 4
3 Z SWITCH Z
Z1 Device Package Shipping
11
A MC74LVXT8053D SOIC 48 Units/Rail
CHANNEL-SELECT 10
B
INPUTS 9
C PIN 16 = VCC MC74LVXT8053DR2 SOIC 2500 Units/Reel
6
ENABLE PIN 8 = GND
MC74LVXT8053DT TSSOP 96 Units/Rail
Channel–Select Input A controls the X–Switch, Input B controls MC74LVXT8053DTR2 TSSOP 2500 Units/Reel

MC74LVXT8053
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
MAXIMUM RATINGS*
ÎÎÎÎ
Symbol
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
I DC Current, Into or Out of Any Pin –20 mA voltages to this high–impedance cir-
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
v v
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
Symbol
ÎÎÎÎ
VCC
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
Parameter
Min
2.0
Max
6.0
Unit
V
ÎÎÎÎ
ÎÎÎÎ
VIS
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
Î ÎÎ
0.0 VCC V
ÎÎÎÎ
Vin
VIO*
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎ
GND VCC
1.2
V
V
ÎÎÎÎ
TA
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
ns/V
ÎÎ
VCC = 3.3 V ± 0.3 V 0 100
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ VCC = 5.0 V ± 0.5 V 0 20
exceeded.
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185
MC74LVXT8053

Guaranteed Limit
VCC
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
Guaranteed Limit
VCC – 55 to
v v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
VIS = VCC to GND 4.5 30 32 37
v |IS| 10.0 mA (Figures 1, 2) 5.5 25 28 30
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Vin = VIL or VIH
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
∆Ron
v
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL or VIH
|IS| 10.0 mA
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
Ω
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186
MC74LVXT8053

Guaranteed Limit
VCC
tPHL (Figure 9) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPHL (Figure 10) 3.0 3.0 5.0 6.0
4.5 1.0 2.0 2.0
5.5 1.0 2.0 2.0
tPHZ (Figure 11) 3.0 20 25 30
4.5 15 18 22
5.5 15 18 20
tPZH (Figure 11) 3.0 12 14 15
4.5 8.0 10 12
5.5 8.0 10 12

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187
MC74LVXT8053

Limit*
VCC
or Minimum
Mi i Frequency
F Response
0dBm F Until
U til dB
3.0 120
4.5 120
RL = 50Ω, CL = 10pF
5.5 120
fin = 10kHz, RL = 600Ω, CL = 50pF 5.5 –50
3.0 –37
4.5 –37
fin = 1.0MHz, RL = 50Ω, CL = 10pF 5.5 –37
3.0 35
4.5 145
RL = 10kΩ, CL = 10pF 5.5 190
fin = 10kHz, RL = 600Ω, CL = 50pF 5.5 –50
3.0 –60
4.5 –60
fin = 1.0MHz, RL = 50Ω, CL = 10pF 5.5 –60
45
40
35
30
125°C
25 85°C
25°C
20
– 55°C
15
10
5
00 1.0 2.0 3.0 4.0

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188
MC74LVXT8053
35 30
30 25

125°C
25 125°C 85°C
85°C 20 25°C
20 25°C
15 – 55°C
15 – 55°C
10
10
5 5
0 0
0 1.0 2.0 3.0 4.0 5.0 0 1.0 2.0 3.0 4.0 5.0 6.0
PLOTTER
PROGRAMMABLE
SUPPLY
– + VCC
DEVICE
UNDER TEST
GND GND
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189
MC74LVXT8053
VCC VCC
VCC VCC
GND 16 GND 16
ANALOG I/O
OFF OFF
VCC A VCC
VIH 6 VIH 6
8 8
VCC VOS
VCC VCC
A 16 0.1µF 16 dB
ON fin ON METER
GND N/C CL* RL
OFF COMMON O/I
VCC ANALOG I/O
VIL 6 6
8 8
VIS VCC VOS VCC

0.1µF 16 dB 16
RL
TEST
POINT
OFF/ON RL CL*
RL
6 6
VCC
8 Vin ≤ 1 MHz 8 11
tr = tf = 3 ns
VIH
VIL or VIH VIL
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190
MC74LVXT8053
VCC
VCC
16
VCC
50% TEST
SELECT ANALOG I/O
POINT
OFF/ON CL*
GND
tPLH tPHL
6
ANALOG
OUT 50%
8
CHANNEL SELECT
VCC
16
VCC TEST
ON
ANALOG POINT
IN 50% CL*
GND
tPLH tPHL
6
ANALOG 8
OUT 50%

90%
ENABLE 50% 2
VCC
10%
GND VCC 1kΩ
tPZL tPLZ 16
HIGH 1 ANALOG I/O
IMPEDANCE TEST
ANALOG 2 ON/OFF
50% POINT
OUT 10% CL*
VOL
tPZH tPHZ VIH
ENABLE
VIL 6
90% VOH
ANALOG
OUT 50% 8
HIGH
IMPEDANCE
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191
MC74LVXT8053
VCC
VIS A
VCC
16 16
RL VOS
ANALOG I/O NC
0.1µF OFF/ON
OFF
RL CL* RL CL* VCC
RL 6
6 8 11
8 CHANNEL SELECT
0
VIS
0.1µF 16 – 20
TO
RL METER
CL* – 40
dB
– 50
DEVICE
– 60
6 SOURCE
– 70
8 – 80

– 100
1.0 2.0 3.125
FREQUENCY (kHz)
supply voltages VCC. The positive peak analog voltage VCC – GND = 2 to 6 volts
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192
MC74LVXT8053
VCC VCC
+5V VCC
16 Dx 16 Dx
+5V +5V
ANALOG ANALOG
ON ON/OFF
0V SIGNAL SIGNAL 0V
Dx Dx
GND GND
6 11 TO EXTERNAL LSTTL COMPATIBLE

10 CIRCUITRY 0 to VIH

+3V +5V
+3V 16 +3V +5V 16 +5V

ON/OFF ON/OFF
SIGNAL SIGNAL SIGNAL SIGNAL
GND GND GND GND
1.8 – 2.5V
6 11 6 11
1.8 – 2.5V 1.8 – 2.5V
10 10
CIRCUITRY CIRCUITRY
8 9 8 9
MC74VHC1GT50 BUFFERS
VCC = 3.0V
a. Low Voltage Logic Level Shifting Control b. 2–Stage Logic Level Shifting Control
Figure 17. Interfacing Low Voltage CMOS Inputs
11 LEVEL 13
A X1
SHIFTER
12
X0
14
X
10 LEVEL 1
B Y1
SHIFTER
2
Y0
15
Y
9 LEVEL 3
C Z1
SHIFTER
5
Z0
4
Z
6 LEVEL
ENABLE
SHIFTER
Figure 18. Function Diagram, LVXT8053
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193
MC74LVXT8053
MARKING DIAGRAMS
(Top View)
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10 9
LVXT8051 LVXT
8051
AWLYWW*
ALYW*
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

D SUFFIX DT SUFFIX
CASE 751B CASE 948F
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194
Package Specifications and Case Outlines
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195
TAPE & REEL SPECIFICATIONS
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
K P0 ±0.2 mm
D P2 (±0.008”)
t
TOP
E
COVER
TAPE
A0 SEE NOTE 2 F
W
B1 K0 + B0 + +
SEE
NOTE 2 D1
P
FOR COMPONENTS
EMBOSSMENT CENTER LINES 2.0 mm × 1.2 mm
FOR MACHINE REFERENCE AND LARGER
ONLY OF CAVITY
INCLUDING DRAFT AND RADII USER DIRECTION OF FEED
CONCENTRIC AROUND B0
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004”) MAX.
R MIN.
TAPE AND COMPONENTS

SHALL PASS AROUND RADIUS “R” EMBOSSED
WITHOUT DAMAGE CARRIER
BENDING RADIUS EMBOSSMENT
100 mm
MAXIMUM COMPONENT ROTATION (3.937”)
10° 1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE TAPE
1 mm 250 mm
(0.039”) MAX (9.843”)
TYPICAL
COMPONENT CAMBER (TOP VIEW)
CENTER LINE ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 1. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)

Tape B1
D D1 E F K P P0 P2 R T W
Size Max
8 mm 4.35 mm 1.5 +0.1/ 1.0 mm 1.75 3.5 2.4 mm 4.0 4.0 2.0 25 mm 0.3 8.0
(0.171”) –0.0 mm Min ±0.1 mm ±0.5 mm (0.094”) ±0.10 mm ±0.1 mm ±0.1 mm (0.98”) ±0.05 mm ±0.3 mm
(0.059 (0.039”) (0.069 (1.38 (0.157 (0.156 (0.079 (0.01 (0.315
+0.004/ ±0.004”) ±0.002”) ±0.004”) ±0.004”) ±0.002”) +0.0038/ ±0.012”)
–0.0”) –0.0002”)
1. Metric Dimensions Govern–English are in parentheses for reference only.
2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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196
t MAX
13.0 mm ±0.2 mm
1.5 mm MIN (0.512” ±0.008”)
(0.06”)
A 20.2 mm MIN 50 mm MIN

(0.795”) (1.969”)
FULL RADIUS
Figure 2. Reel Dimensions
REEL DIMENSIONS
Tape
Size A Max G t Max
8 mm 330 mm 8.400 mm, +1.5 mm, –0.0 14.4 mm
(13”) (0.33”, +0.059”, –0.00) (0.56”)
DIRECTION OF FEED
BARCODE LABEL
POCKET HOLE
Figure 3. Reel Winding Direction
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197
TAPE TRAILER
TAPE LEADER
(Connected to Reel Hub) COMPONENTS NO COMPONENTS
CAVITY TOP TAPE NO COMPONENTS
400 mm MIN
TAPE 160 mm MIN
DIRECTION OF FEED
Figure 4. Tape Ends for Finished Goods
“T1” PIN ONE TOWARDS SC–88A/SOT–353 (5 Pin)

SPROCKET HOLE DEVICE
User Direction of Feed
Figure 5. Reel Configuration
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198
CASE OUTLINE AND PACKAGE DIMENSIONS
SC–88A / SOT–353
DF SUFFIX
5–LEAD PACKAGE
CASE 419A–01 NOTES:
ISSUE B 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MM.
INCHES MILLIMETERS
G DIM MIN MAX MIN MAX
A 0.071 0.087 1.80 2.20
V B 0.045 0.053 1.15 1.35
C 0.031 0.043 0.80 1.10
D 0.004 0.012 0.10 0.30
G 0.026 BSC 0.65 BSC
5 4 H ––– 0.004 ––– 0.10
J 0.004 0.010 0.10 0.25
K 0.004 0.012 0.10 0.30
S –B–
N 0.008 REF 0.20 REF
1 2 3 S 0.079 0.087 2.00 2.20
V 0.012 0.016 0.30 0.40
0.5 mm (min)
ÉÉÉ ÉÉÉ
D 5 PL 0.2 (0.008) M B M
ÉÉÉ ÉÉÉ
N
ÉÉÉ ÉÉÉ
0.65 mm 0.65 mm
ÉÉÉ
J
C
ÉÉÉ
ÉÉÉ ÉÉÉ
0.4 mm (min)
ÉÉÉ ÉÉÉ
H
1.9 mm
PDIP–14
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01
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199
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01
PDIP–24
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
24 13 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 12 FLASH.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.37 32.13 1.235 1.265
A C L B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
N D 0.36 0.56 0.014 0.022
F 1.02 1.52 0.040 0.060
K G 2.54 BSC 0.100 BSC
H 1.65 2.03 0.065 0.080
H F M J J 0.20 0.38 0.008 0.015
SEATING K 2.92 3.43 0.115 0.135
G D PLANE
L 15.24 BSC 0.600 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040
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200
SO–14
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
SO–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019
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201
SO–16 WIDE
DW SUFFIX
CASE 751G–02
ISSUE A
–A– NOTES:
16 9 Y14.5M, 1982.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
–B– 8X P 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
0.010 (0.25) M B M
1 8 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
J MATERIAL CONDITION.
16X D
MILLIMETERS INCHES
0.010 (0.25) M T A S B S DIM MIN MAX MIN MAX
A 10.15 10.45 0.400 0.411
F B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
R X 45 _ F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
C K 0.10 0.25 0.004 0.009
–T– M 0_ 7_ 0_ 7_
SEATING M P 10.05 10.55 0.395 0.415
14X G K PLANE R 0.25 0.75 0.010 0.029
SO–24 WIDE
DW SUFFIX
CASE 751E–04
ISSUE E
–A–
24 13 NOTES:
Y14.5M, 1982.
–B– 12X P MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
0.010 (0.25) M B M
PER SIDE.
1 12 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
24X D J
MILLIMETERS INCHES
0.010 (0.25) M T A S B S
DIM MIN MAX MIN MAX
A 15.25 15.54 0.601 0.612
F B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
R X 45 _ D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
C J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
–T– M 0_ 8_ 0_ 8_
SEATING M P 10.05 10.55 0.395 0.415
PLANE 22X G K R 0.25 0.75 0.010 0.029
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202
TSSOP–14
DT SUFFIX
CASE 948G–01
ISSUE O
14X K REF NOTES:
0.10 (0.004) M T U S V S Y14.5M, 1982.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
N (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
2X L/2 FLASH OR PROTRUSION. INTERLEAD FLASH OR
M PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
–U– N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
IDENT. F EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1 7 6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
ÇÇ
0.15 (0.006) T U S
A K
MILLIMETERS INCHES
K1
ÉÉ
ÇÇ
–V– DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
ÉÉ
ÇÇ
J J1 C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N–N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
–T– SEATING D G H DETAIL E
PLANE
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004) M T U S V S
NOTES:
0.15 (0.006) T U S
ÉÉ
ÇÇÇ
K 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K1 2. CONTROLLING DIMENSION: MILLIMETER.
ÇÇÇ
ÉÉ
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
16 9 PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
ÇÇÇ
ÉÉ
2X L/2 J1 GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
B SECTION N–N FLASH OR PROTRUSION. INTERLEAD FLASH OR
L PROTRUSION SHALL NOT EXCEED
–U– 0.25 (0.010) PER SIDE.
J
PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT. PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
1 8 DIMENSION AT MAXIMUM MATERIAL CONDITION.
N 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.25 (0.010) 7. DIMENSION A AND B ARE TO BE DETERMINED AT
0.15 (0.006) T U S DATUM PLANE –W–.
A M
MILLIMETERS INCHES
–V–
DIM MIN MAX MIN MAX
N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
F C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
DETAIL E F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
0.10 (0.004) M 0_ 8_ 0_ 8_
–T– SEATING H DETAIL E
PLANE D G
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203
SO–14 EIAJ
F SUFFIX
CASE 965–01
ISSUE O NOTES:
Y14.5M, 1982.
3. DIMENSIONS D AND E DO NOT INCLUDE
14 8 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 7 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
D BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
A MILLIMETERS INCHES
e DIM MIN MAX MIN MAX
c A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
b A1 D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
0.13 (0.005) M 0.10 (0.004) e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 1.42 ––– 0.056
SO–16 EIAJ
F SUFFIX
CASE 966–01
ISSUE O NOTES:
Y14.5M, 1982.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031
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204
ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OFFICES
UNITED STATES CANADA INTERNATIONAL (continued)
ONTARIO KOREA
ALABAMA Ottawa . . . . . . . . . . . . . . . . . . . . (613)226–3491 Seoul . . . . . . . . . . . . . . . . . . . . 82–2–3440–7200
Huntsville . . . . . . . . . . . . . . . . . . (256)464–6800 QUEBEC MALAYSIA
CALIFORNIA Montreal . . . . . . . . . . . . . . . . . . . (514)333–3300 Penang . . . . . . . . . . . . . . . . . . . . 60(4)228–2514
Irvine . . . . . . . . . . . . . . . . . . . . . . (949)753–7360
MEXICO
San Jose . . . . . . . . . . . . . . . . . . (408)749–0510 INTERNATIONAL Guadalajara . . . . . . . . . . . . . . . . 52(36)78–0750
COLORADO BRAZIL PHILIPPINES
Littleton . . . . . . . . . . . . . . . . . . . . (303)256–5884 Sao Paulo . . . . . . . . . . . . . 55(011)3030–5244 Manila . . . . . . . . . . . . . . . . . . . . (63)2 807–8455
FLORIDA CHINA PUERTO RICO
Tampa . . . . . . . . . . . . . . . . . . . . . (813)286–6181 Beijing . . . . . . . . . . . . . . . . . . . 86–10–65642288 San Juan . . . . . . . . . . . . . . . . . . (787)641–4100
GEORGIA Guangzhou . . . . . . . . . . . . . . 86–20–87537888
SINGAPORE
Atlanta . . . . . . . . . . . . . . . . . . . . (770)338–3810 Shanghai . . . . . . . . . . . . . . . . 86–21–63747668 Singapore . . . . . . . . . . . . . . . . . . . . (65)4818188
ILLINOIS FRANCE SPAIN
Chicago . . . . . . . . . . . . . . . . . . . (847)413–2500 Paris . . . . . . . . . . . . . . . . . . . . . . 33134 635900 Madrid . . . . . . . . . . . . . . . . . . . . . 34(1)457–8204
MASSACHUSETTS GERMANY or . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)457–8254
Boston . . . . . . . . . . . . . . . . . . . . (781)932–9700 Munich . . . . . . . . . . . . . . . . . . . . 49 89 92103–0
SWEDEN
MICHIGAN HONG KONG Stockholm . . . . . . . . . . . . . . . . . 46(8)734–8800
Detroit . . . . . . . . . . . . . . . . . . . . . (248)347–6800 Hong Kong . . . . . . . . . . . . . . . 852–2–610–6888
TAIWAN
MINNESOTA INDIA Taipei . . . . . . . . . . . . . . . . . . . 886(2)27058000
Plymouth . . . . . . . . . . . . . . . . . . (612)249–2360 Bangalore . . . . . . . . . . . . . . . . . 91–80–5598615
THAILAND
NORTH CAROLINA ISRAEL Bangkok . . . . . . . . . . . . . . . . . . . 66(2)254–4910
Raleigh . . . . . . . . . . . . . . . . . . . . (919)870–4355 Tel Aviv . . . . . . . . . . . . . . . . . . . 972–9–9522333
UNITED KINGDOM
PENNSYLVANIA ITALY Aylesbury . . . . . . . . . . . . . . . 44 1 (296)395252
Philadelphia/Horsham . . . . . . . (215)957–4100 Milan . . . . . . . . . . . . . . . . . . . . . . . . 39(02)82201
TEXAS JAPAN
Dallas . . . . . . . . . . . . . . . . . . . . . (972)516–5100 Tokyo . . . . . . . . . . . . . . . . . . . 81–3–5487–8345
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205
ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS
REFERENCE MANUAL
A Reference Manual is a publication that contains a comprehensive system or device–specific description of the structure and function
(operation) of a particular part/system; used overwhelmingly to describe the functionality of a microprocessor, microcontroller, or some
other sub–micron sized device. Procedural information in a Reference Manual is limited to less than 40 percent (usually much less).
USER’S GUIDE
A User’s Guide contains procedural, task–oriented instructions for using or running a device or product. A User’s Guide differs from
a Reference Manual in the following respects:
* Majority of information (> 60%) is procedural, not functional, in nature
* Volume of information is typically less than for Reference Manuals
* Usually written more in active voice, using second–person singular (you) than is found in Reference Manuals
* May contain photographs and detailed line drawings rather than simple illustrations that are often found in Reference Manuals
POCKET GUIDE
A Pocket Guide is a pocket–sized document that contains technical reference information. Types of information commonly found in
pocket guides include block diagrams, pinouts, alphabetized instruction set, alphabetized registers, alphabetized third–party vendors and
their products, etc.
ADDENDUM
A documentation Addendum is a supplemental publication that contains missing information or replaces preliminary information in the
primary publication it supports. Individual addendum items are published cumulatively. Addendums end with the next revision of the
primary document.
APPLICATION NOTE
An Application Note is a document that contains real–world application information about how a specific ON Semiconductor
device/product is used with other ON Semiconductor or vendor parts/software to address a particular technical issue. Parts and/or software
must already exist and be available.
A document called “Application–Specific Information” is not the same as an Application Note.
SELECTOR GUIDE
A Selector Guide is a tri–fold (or larger) document published on a regular basis (usually quarterly) by many, if not all, divisions, that
contains key line–item, device–specific information for particular product families. Some Selector Guides are published in book format
and contain previously published information.
PRODUCT PREVIEW
A Product Preview is a summary document for a product/device under consideration or in the early stages of development. The Product
Preview exists only until an “Advance Information” document is published that replaces it. The Product Preview is often used as the first
section or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer at the bottom of the first
page: “ON Semiconductor reserves the right to change or discontinue this product without notice.”
ADVANCE INFORMATION
The Advance Information document is for a device that is NOT fully MC–qualified. The Advance Information document is replaced
with the Technical Data document once the device/part becomes fully MC–qualified. The Advance Information document displays the
following disclaimer at the bottom of the first page: “This document contains information on a new product. Specifications and information
herein are subject to change without notice.”
TECHNICAL DATA
The Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces the Advance Information
document and represents a part that is M, X, XC, or MC qualified. The Technical Data document is virtually the same document as the
Product Preview and the Advance Information document with the exception that it provides information that is unavailable for a product
in the early phases of development (such as complete parametric characterization data). The Technical Data document is also a more
comprehensive document that either of its earlier incarnations. This document displays no disclaimer, and while it may be informally
referred to as a “data sheet,” it is not labeled as such.
ENGINEERING BULLETIN
An Engineering Bulletin is a writeup that typically focuses on a single specific solution for a particular engineering or programming issue
involving one or several devices.
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206
BRD8007/D
Rev. 0, Apr-2000
ON Semiconductor
Analog Switches
ON Semiconductor
Analog Switches
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
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special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
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PUBLICATION ORDERING INFORMATION

PUBLICATION ORDERING INFORMATION

DC Ctrl for VCO Loop Impedance Remains

±2.5 Volts +3.3 Volts ±2.5 Volts

VEE, –3.3 Volts

VCC, 5.0 Volts

Quad Analog Switch/

The MC14016B quad bilateral switch is constructed with MOS

• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved 1

Protection. Antistatic Precautions Must Be Taken. 14

 Semiconductor Components Industries, LLC, 2000 8 Publication Order Number:

LOGIC DIAGRAM RESTRICTIONS IN

VIL: VC is raised from VSS until VC = VIL.

Figure 1. Input Voltage Test Circuit

PD , POWER DISSIPATION (µW)

VSS Vin 1.0

TYPICAL RON versus INPUT VOLTAGE

R ON, “ON” RESISTANCE (OHMS)

400 VC = VDD = 5.0 Vdc 400

200 200 VC = VDD = 15 Vdc

Figure 4. VSS = – 5.0 V and – 7.5 V Figure 5. VSS = 0 V

Figure 6. RON Characteristics Figure 7. Propagation Delay Test Circuit

Figure 14. ∆V Across Switch

Figure A. Application Example

Figure B. External Germanium or Schottky Clipping Diodes

 Semiconductor Components Industries, LLC, 2000 16 Publication Order Number:

MC14051B MC14052B MC14053B

6 INHIBIT 6 INHIBIT 6 INHIBIT

VDD = PIN 16 VDD = PIN 16 VDD = PIN 16

Figure 1. Switch Circuit Schematic

TRUTH TABLE 16 VDD

Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

VDD VEE VEE VDD

Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

A, B, and C inputs used to turn ON

Figure 7. Bandwidth and Off–Channel Figure 8. Channel Separation

OFF CHANNEL UNDER TEST

Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage

NOTE: See also Figures 7 and 8 in the MC14016B

VDD KEITHLEY 160

Figure 11. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

R ON , “ON” RESISTANCE (OHMS)

150 150 TA = 125°C

500 250 VDD = 2.5 V

VDD VSS VEE

Figure A. Application Example

Figure B. External Germanium or Schottky Clipping Diodes

ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMATION:

Quad Analog Switch/Quad

The MC14066B consists of four independent switches capable of

• Linearized Transfer Characteristics 1

• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical 14

• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B

Tstg Storage Temperature Range – 65 to +150 °C

MC14066BFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of

 Semiconductor Components Industries, LLC, 2000 25 Publication Order Number:

BLOCK DIAGRAM LOGIC DIAGRAM AND TRUTH TABLE

VDD VDD VDD

Figure 1. ∆V Across Switch Figure 2. Turn–On Delay Time Test Circuit

VDD – VSS Vin