EE312

Experiment 07
SAURABH KUMAR
190102065
Objective 1
Design a half adder in verilog and simulate the same in VIVADO using
testbench(simulation source).

Also produce the following for the design

1) Verilog code,
2) Test bench,
3) Behaviour simulation output waveform,
4) Synthesis report,
5) Post synthesis functional simulation output waveform,
6) Implementation report,
7) Post implementation functional simulation output waveform,
8) Timing report.

Half Adder:
A Half adder adds two inputs bits, to give one Sum and one Carry output bit. Half
adders have the following truth table and logic circuit.

Circuit:
Verilog design code:

module half_adder(
Data_in_A,
Data_in_B,
Data_out_Sum,
Data_out_Carry
);

//what are the input ports.

input Data_in_A;
input Data_in_B;
//What are the output ports.
output Data_out_Sum;
output Data_out_Carry;

//Implement the Sum and Carry equations using Verilog Bit operators.
assign Data_out_Sum = Data_in_A ^ Data_in_B; //XOR operation
assign Data_out_Carry = Data_in_A & Data_in_B; //AND operation

endmodule

Testbench:
`timescale 1ns / 1ps
module tb_half_adder();
reg Data_in_A,Data_in_B;
wire Data_out_Sum,Data_out_Carry;

half_adder dut(Data_in_A,Data_in_B,Data_out_Sum,Data_out_Carry);

initial begin
Data_in_A = 0;
Data_in_B = 0;
#100 Data_in_A = 1;
Data_in_B = 0;
#100 Data_in_A = 0;
Data_in_B = 1;
#100 Data_in_A = 1;
Data_in_B = 1;

end
endmodule
Behaviour simulation output waveform:

Synthesis:

Synthesis report:

Timing report:
Power report:

Post synthesis functional simulation waveform:

Implementation:

Implementation report:
Timing report:

Power report:

Post implementation functional simulation waveform:

Objective 2
Design a full adder using half adder of objective 1 in verilog and simulate the same in
VIVADO using testbench(simulation source).

Also produce the following for the design

1) Verilog code,
2) Test bench,
3) Behaviour simulation output waveform,
4) Synthesis report,
5) Post synthesis functional simulation output waveform,
6) Implementation report,
7) Post implementation functional simulation output waveform,
8) Timing report.

Full Adder:
Full adder is a basic combinational circuit which is extensively used in many designs.
They are the basic building blocks for all kinds of adders. A full adder adds three
input bits, to give out, two output bits - Sum and Carry. They have the following truth
table:

Circuit:

A Full adder can be implemented using half adders as shown below:

Verilog design code:

half_adder.v

//Declare the ports of Half adder module

`timescale 1ns/1ps
module half_adder(
Data_in_A,
Data_in_B,
Data_out_Sum,
Data_out_Carry
);

//what are the input ports.

input Data_in_A;
input Data_in_B;
//What are the output ports.
output Data_out_Sum;
output Data_out_Carry;

//Implement the Sum and Carry equations using Verilog Bit operators.
assign Data_out_Sum = Data_in_A ^ Data_in_B; //XOR operation
assign Data_out_Carry = Data_in_A & Data_in_B; //AND operation

endmodule

full_adder.v

//declare the Full adder verilog module.

`timescale 1ns/1ps
module full_adder(
Data_in_A, //input A
Data_in_B, //input B
Data_in_C, //input C
Data_out_Sum,
Data_out_Carry
);

//what are the input ports.

input Data_in_A;
input Data_in_B;
input Data_in_C;
//What are the output ports.
 output Data_out_Sum;
output Data_out_Carry;
//Internal variables
wire ha1_sum;
wire ha2_sum;
wire ha1_carry;
wire ha2_carry;
wire Data_out_Sum;
wire Data_out_Carry;

//Instantiate the half adder 1

half_adder ha1(
.Data_in_A(Data_in_A),
.Data_in_B(Data_in_B),
.Data_out_Sum(ha1_sum),
.Data_out_Carry(ha1_carry)
);

//Instantiate the half adder 2

half_adder ha2(
.Data_in_A(Data_in_C),
.Data_in_B(ha1_sum),
.Data_out_Sum(ha2_sum),
.Data_out_Carry(ha2_carry)
);

//sum output from 2nd half adder is connected to full adder output
assign Data_out_Sum = ha2_sum;
//The carry's from both the half adders are OR'ed to get the final
//carry.
assign Data_out_Carry = ha1_carry | ha2_carry;

endmodule

Testbench:
tb_full_adder.v

`timescale 1ns/1ps
module tb_fullAdd;

// Inputs
reg Data_in_A;
reg Data_in_B;
reg Data_in_C;

// Outputs
wire Data_out_Sum;
wire Data_out_Carry;

// Instantiate the Unit Under Test (UUT)

full_adder uut (
.Data_in_A(Data_in_A),
 .Data_in_B(Data_in_B),
.Data_in_C(Data_in_C),
.Data_out_Sum(Data_out_Sum),
.Data_out_Carry(Data_out_Carry)
);

initial begin
//Apply inputs. 8 combinations of inputs are possible.
//They are given below.
Data_in_A = 0; Data_in_B = 0; Data_in_C = 0; #100;
Data_in_A = 0; Data_in_B = 0; Data_in_C = 1; #100;
Data_in_A = 0; Data_in_B = 1; Data_in_C = 0; #100;
Data_in_A = 0; Data_in_B = 1; Data_in_C = 1; #100;
Data_in_A = 1; Data_in_B = 0; Data_in_C = 0; #100;
Data_in_A = 1; Data_in_B = 0; Data_in_C = 1; #100;
Data_in_A = 1; Data_in_B = 1; Data_in_C = 0; #100;
Data_in_A = 1; Data_in_B = 1; Data_in_C = 1; #100;
end

endmodule

Behaviour simulation output waveform:

Synthesis:

Synthesis report:
Timing report:

Power report:

Post synthesis functional simulation waveform:

Implementation:

Implementation report:

Timing report:

Power report:
Post implementation functional simulation waveform:

Objective 3
Design a 4-bit adder with the help of full adder designed in objective 2 in verilog and
simulate the same in VIVADO using testbench(simulation source).

Also produce the following for the design

1) Verilog code,
2) Test bench,
3) Behaviour simulation output waveform,
4) Synthesis report,
5) Post synthesis functional simulation output waveform,
6) Implementation report,
7) Post implementation functional simulation output waveform,
8) Timing report.

Verilog design code:

half_adder.v

//Declare the ports of Half adder module

`timescale 1ns/1ps
module half_adder(
Data_in_A,
Data_in_B,
Data_out_Sum,
Data_out_Carry
);

//what are the input ports.

input Data_in_A;
input Data_in_B;
//What are the output ports.
output Data_out_Sum;
output Data_out_Carry;

//Implement the Sum and Carry equations using Verilog Bit operators.
assign Data_out_Sum = Data_in_A ^ Data_in_B; //XOR operation
 assign Data_out_Carry = Data_in_A & Data_in_B; //AND operation

endmodule

FullAdder.v

//declare the Full adder verilog module.

`timescale 1ns/1ps
module full_adder(
Data_in_A, //input A
Data_in_B, //input B
Data_in_C, //input C
Data_out_Sum,
Data_out_Carry
);

//what are the input ports.

input Data_in_A;
input Data_in_B;
input Data_in_C;
//What are the output ports.
output Data_out_Sum;
output Data_out_Carry;
//Internal variables
wire ha1_sum;
wire ha2_sum;
wire ha1_carry;
wire ha2_carry;
wire Data_out_Sum;
wire Data_out_Carry;

//Instantiate the half adder 1

half_adder ha1(
.Data_in_A(Data_in_A),
.Data_in_B(Data_in_B),
.Data_out_Sum(ha1_sum),
.Data_out_Carry(ha1_carry)
);

//Instantiate the half adder 2

half_adder ha2(
.Data_in_A(Data_in_C),
.Data_in_B(ha1_sum),
.Data_out_Sum(ha2_sum),
.Data_out_Carry(ha2_carry)
);

//sum output from 2nd half adder is connected to full adder output
assign Data_out_Sum = ha2_sum;
//The carry's from both the half adders are OR'ed to get the final
//carry.
assign Data_out_Carry = ha1_carry | ha2_carry;
endmodule

4BitAdder.v

`timescale 1ns/1ps
module full_adder_4b(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;

full_adder f1 (a[0], b[0], cin, sum[0], cout0);

full_adder f2 (a[1], b[1], cout0, sum[1], cout1);
full_adder f3 (a[2], b[2], cout1, sum[2], cout2);
full_adder f4 (a[3], b[3], cout2, sum[3], cout);

endmodule

Testbench:
tb_FourBitAdder.v

`timescale 1ns / 1ps

module TestModule;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test (UUT)

full_adder_4b uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;

a = 2;
b = 3;
cin = 1;

// Wait 100 ns for global reset to finish

#100;

a = 3;
b = 5;
cin = 0;

// Wait 100 ns for global reset to finish

#100;

a = 4;
b = 5;
cin = 1;

// Wait 100 ns for global reset to finish

#100;

a = 5;
b = 7;
cin = 0;

// Wait 100 ns for global reset to finish

#100;

a = 12;
b = 3;
cin = 1;

// Wait 100 ns for global reset to finish

#100;

a = 14;
b = 3;
cin = 0;

// Wait 100 ns for global reset to finish

#100;

a = 14;
b = 14;
cin = 1;

#100;

end
endmodule
Behaviour simulation output waveform:

Synthesis:

Synthesis report:

Timing report:
Power report:

Post synthesis functional simulation waveform:

Implmentation:
Implementation report:
Timing report:

Power report:

Post implementation functional simulation report:

End of report