BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI

I SEMESTER 2021-2022
MEL G621 VLSI Design
LAB Assignment (OPEN BOOK/OPEN WEB)
M.M:2 19-10-2021 Due Date:19.10.2021
Name: ID.No

Lab Objective: CMOS based NAND and NOR

Propagation Delay (𝜏)

Problem Statement:
A. CMOS based NAND and NOR Logic Gate
1. Draw CMOS NAND and NOR logic gates in LTspice. For NAND, use Wn=440nm and Wp=440nm
and for NOR, Wp=880nm and Wn=220nm.
2. Fix the supply voltage VDD to 1.8 V.
3. Place a 100f F intermediate capacitive load and 200f F output capacitive load.
3. Perform transient analysis and plot the output with respect to time.
4. Determine the average propagation delay (𝜏P) of the logic gate outputs for all the input combination.

Simulation Results/Waveforms

Transient Waveform
CMOS based NAND and NOR

Propagation Delay (𝜏)

Case NAND NOR

B A 𝜏p 𝜏p
0 0 A=0 ; B= 1→0
A= 1→0; B=0
A= 1→0; B= 1→0
0 1 A=1 ; B= 1→0
A= 0→1; B=0
A= 0→1 ; B= 1→0
1 0 A=0 ; B= 0→1
A= 1→0 ;B=1
B= 0→1; A= 1→0
1 1 A=1 ; B= 0→1
A= 0→1 ; B=1
B= 0→1 ; A= 0→1