CARRY SELECT ADDER BASED ON DUAL RAIL

ERROR DETECTION AND EASY TESTABILITY

Submitted by: Guided by:

M Sailaja (208221017) Archana mam

Shri Krishna Saraswat (208221030)
Tushar Agnibhoj (208221033)

1.Brief write-up:

Concurrent error detection (CED) means detecting errors in parallel with normal operation of
the circuit. The error detection and testing are carried out on proposed carry select adder.
Error detection can be done using parity comparison. The comparison is between the
predicted parity of sum and parity of the sum generated.

The proposed system mainly consists of a multi-block carry select adder (CSA) with
concurrency property. This system assumes two carry inputs to each block, either 0 or 1.
Final sum output is calculated by selecting one carry using a multiplexer. Concurrent error
detectability is obtained by special design of half adder and incrementer. The incrementer has
2 carry outputs, where one is used for addition purpose and the other is used for parity
prediction.

2.Function:

This adder in the system generates sum output and parity. A parity generator is present,
which consist of XOR gates, it is used for generating parity of the sum. A two rail checker
compares the parity of sum and predicted parity along with carry outputs.
Inputs provided to the checker are complementary inputs, then the output should also be
complementary. If the output is erroneous, then it won’t be complementing to each other.
Hence error is detected.
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