An analytical drain current model for

symmetric double-gate MOSFETs

Cite as: AIP Advances 8, 045125 (2018); https://doi.org/10.1063/1.5024574
Submitted: 02 February 2018 • Accepted: 21 April 2018 • Published Online: 30 April 2018

Fei Yu, Gongyi Huang, Wei Lin, et al.

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© 2018 Author(s).
 AIP ADVANCES 8, 045125 (2018)

An analytical drain current model for symmetric

double-gate MOSFETs
Fei Yu,a Gongyi Huang, Wei Lin, and Chuanzhong Xu
College of Information Science and Engineering, Huaqiao University, Xiamen 361021, China
(Received 2 February 2018; accepted 21 April 2018; published online 30 April 2018)

An analytical surface-potential-based drain current model of symmetric double-gate

(sDG) MOSFETs is described as a SPICE compatible model in this paper. The con-
tinuous surface and central potentials from the accumulation to the strong inversion
regions are solved from the 1-D Poisson’s equation in sDG MOSFETs. Furthermore,
the drain current is derived from the charge sheet model as a function of the surface
potential. Over a wide range of terminal voltages, doping concentrations, and device
geometries, the surface potential calculation scheme and drain current model are ver-
ified by solving the 1-D Poisson’s equation based on the least square method and
using the Silvaco Atlas simulation results and experimental data, respectively. Such
a model can be adopted as a useful platform to develop the circuit simulator and pro-
vide the clear understanding of sDG MOSFET device physics. © 2018 Author(s).
All article content, except where otherwise noted, is licensed under a Creative
Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
https://doi.org/10.1063/1.5024574

I. INTRODUCTION
Silicon ICs have the strong demand for increasing dense so that the feature size of devices
shrinks into the nanometer scale. Simultaneously, the further scaling leads to hard limits1 for the
device performance improvement due to the short channel effects (SCEs). Recently, the multiple-
gate (MG) MOSFETs,2,3 such as double-, Π-, Ω-, surrounding-, quadruple-gate MOSFETs, etc.,
have become as the promising candidates for the classical MOSFETs to overcome the scaling limits.
Therefore, it is necessary to develop a drain current compact model of symmetric double-gate (sDG)
MOSFETs, in order to better exploit sDG MOSFET circuit design and simulation.
Besides of physical and computational accuracy, it is imperative that a practical model must
be continuous,4 simple,5 and convergent,6 in all operational regions. There are some sDG transistor
models reported in the literatures,7–17 but most models,8–11 including those reviewed by Ortiz-Conde
et al.,7 are either suitable for the undoped device or based on the regional approach.12 In addition,
the physics-based 2-D model proposed by A. Sehgal et al.13 is complicated and unfitted for cir-
cuit simulators. Our previous works14 suitable for simulating sDG polysilicon thin-film transistors
cannot be directly applied into the sDG MOSFETs without any adjustment. T. K. Chiang et al.15
developed an analytical threshold voltage model for the sDG MOSFETs which can be applied to
circuit simulation due to its computational efficiency, but the drain current model is still required in
the circuit simulation. S.–C. Lo et al.16 solved the nonlinear Poisson equation for sDG metal-oxide-
semiconductor transistors to get the explicit solution of the surface potential, but they also used the
regional approach leading to the absence of the physical meaning and decrease of the computational
accuracy in the transition between the different operational regions. J. He et al.17 developed a con-
tinuous channel potential solution from the accumulation to the strong inversion region for the sDG
MOSFETs, but this model is not suitable for the short-channel devices. Based on the above literatures,
we can observe that the improvement rooms are left for accuracy, simplicity, and continuity without

a
Corresponding author e-mail: yufei jnu@126.com

2158-3226/2018/8(4)/045125/11 8, 045125-1 © Author(s) 2018

045125-2 Yu et al. AIP Advances 8, 045125 (2018)

smoothing functions, especially in the transition between the different regions of the short-channel
sDG MOSFETs.
In this paper, we give solutions of the surface and central potential in a closed form without
any smoothing functions, which are continuous from accumulation, subthreshold, to strong inversion
regions. Furthermore, we formulate the drain current expression by using the charge sheet model18 for
the sDG MOSFETs. Finally, we give the important attention on the high accuracy and fast convergence
of such a sDG MOSFET model, which is verified by the least square method results, Silvaco Atlas
simulation results, and experimental data.

II. SURFACE AND CENTRAL POTENTIAL

According to the cross section structure and the 1-D band diagram of the symmetric double-gate
(sDG) MOSFETs shown in Fig. 1, the surface and central potentials should be solved from the 1-D
Poisson’s equation in the channel, i.e.,
d 2 ϕ q  ni2 ϕ − Vch
! !
−ϕ 

= exp + Na − Na exp . (1)
dx 2 ε si  Na Vt Vt 

Here, ϕ is the electrostatic potential as a function of x, ϕs is the surface potential with ϕs =ϕ(t si /2), ϕo is
the central potential with ϕo =ϕ(0), ni is the intrinsic carrier concentration, N a is the uniform acceptor
doping concentration in the channel, q is the magnitude of electronic charge, ε si is the dielectric
permittivity of silicon, Vch is the electron quasi-Fermi potential, Vt is the thermal voltage (kT /q),
k is the Boltzmann constant, and T is the absolute temperature. In addition, t si and t ox are the channel
film thickness and gate oxide thickness in the Fig. 1, respectively. To the best of our knowledge,
ϕ cannot be solved analytically from (1). Therefore, ϕs and ϕo cannot also be formulated directly
from (1).
A. Surface and central potential derivation
Based on the symmetric structure in Fig. 1, the initial conditions of (1) are (dϕ/dx)x =0 = 0
and ϕ(0)=ϕo . It is noted that the sDG MOSFETs, unlike the classical MOSFETs, operate in the
full-depletion mode so that ϕo is coupling with ϕs rather than a constant. Using the relationship of
d dϕ 2
 dϕ  d 2 ϕ
dx dx 2 , we can obtain the electric field E, symbolled with dϕ/dx, along the x-direction
 
dx dx = 2
as −Vch
!2
2qVt  ni2 e Vt  Vϕ ϕ − ϕo
 ! 
dϕ ϕo
  −ϕ −ϕo 
E = −
2
= e t − e Vt + Na − Na e Vt − e Vt  . (2)
ε si  Na

dx Vt 
 

FIG. 1. Schematic of sDG MOSFETs in the plane of x-y.

045125-3 Yu et al. AIP Advances 8, 045125 (2018)

Furthermore, according to Gauss’ law, we can obtain the first coupling equation between ϕs and ϕo ,
i.e.,
−Vch
 2 2qVt  ni2 e Vt  ϕs ϕs − ϕo
 ! 
ϕo
   −ϕs −ϕ o 
Cox Vgs − Vfb − ϕs =
2
e t − e t + Na
V V − Na e t − e t  , (3)
V V
ε si  Na

Vt 

where C ox is the gate capacitance per unit area, Vgs is the gate-to-source voltage, and Vfb is the
flat-band voltage.
In (3), there are two unknown variables ϕs and ϕo . Therefore, we need look for another equation
between ϕs and ϕo to derive a solution. According to (1), the electrostatic potential ϕ at the arbitrary
position along the x axis in the channel can be expressed by integrating (1) twice, i.e.,
x v
q  ni2 ϕ − Vch
! !
−ϕ 

ϕ − ϕo = exp + Na − Na exp dudv, (4)
ε si  Na Vt Vt 
0 0  
where u and v are integral intermediate variables. Considering (dϕ/dx)x =0 = 0, we can reformulate
(4) and get another equation between ϕs and ϕo as
ϕo Na tsi 2
" ! ! #
q −ϕo
ϕs − ϕo = η s exp + ρs exp + . (5)
ε si Vt Vt 8
Here, .
tsi
 2v
ni2 e−Vch /Vt ϕs − ϕo
!
ηs = exp dudv, (6)
Na Vt
0 0
.
tsi
 2v
ϕs − ϕo
!
ρs = −Na exp − dudv. (7)
Vt
0 0
In order to solve (6) and (7), we assume the difference between the surface potential and the central
potential as a constant:
q Na  tsi  2
ϕs − ϕo = . (8)
ε si 2 2
It is noted that (8) can be derived directly from the simplified 1-D Poisson’s equation valid in the
subthreshold region. Substituting (6)–(8) into the right hand side of (5), the second coupling equation
between ϕs and ϕo can be obtained as
ϕo
! !
−ϕo
ϕs − ϕo = a · exp + b · exp + c. (9)
Vt Vt
qNa t 2
!
si Vch qNa t 2
2 2
q tsi ni − − si qNa t 2
where a = , b = − qN , and c = 8εsisi .
8εsi Vt Vt a
εsi 8Na e εsi e
8εsi Vt

Now, we can solve the surface potential and the central potential from the combination between
(3) and (9) by using the Newton iterative method,19 which leads to the fast convergences. It is
interesting that (9) is analogous as the approximation20 derived by J. M. Sallese et al. The distinction
is that the derivation of the initial guess difference between ϕs and ϕo is based on device physics
in this paper, rather than that the electrostatic potential ϕ is defined as a local approximation,21
i.e., ϕ=ϕo , in the coarse finite difference method.20
Furthermore, based on the solutions of ϕs and ϕo , we derive the threshold voltage Vth , which is
defined as the gate-to-source voltage on the condition that the free charge density is equated with the
twice time doping concentration in the 1-D Poisson’s equation. Combining with the 1-D Poisson’s
equation and Gauss’ law, and considering the condition of Boltzmann’s distribution, we can derive
Vth as
2N 2 qNa tsi tox
Vth = Vfb + Vt ln* 2a + + + 3Vt . (10)
, ni - ε ox
045125-4 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 2. Comparisons between our electrostatic potential model and the least square method at the source terminal.

It is interesting that there is a little influence on Vth from both t si and t ox because of the sub-nanometer
scale dimensions in sDG MOSFETs.

B. Surface and central potential verification

In this part, we using the least square method to verify our electrostatic potential model in the case
of the large channel width and length, avoiding the secondary order effects due to the short channel
effects. In addition, for the given different drain-to-source voltage Vds and device dimensions, the
surface and central potentials are calculated at the source terminal Vds =0V and the drain terminal
Vds =Vch , respectively.
In Fig. 2, we provide the predicted surface and central potentials versus the gate-to-source voltage
Vgs at the source terminal, compared with the least square method results. We can observe that our
electrostatic potential model shows a good match with the least square method results in the whole
operational region without any smoothing functions. In addition, the difference between ϕs and ϕo
levels off to zero, because the channel of sDG MOSFETs is the ultra-thin film. From Fig. 3, we
can observe that the errors between our model and the least square method results are in the mV
scale. At the drain terminal, ϕs and ϕo vs. Vgs for the different Vch are predicted in Fig. 4, which
shows that Vch has an influence on the strong inversion region, but not accumulation and subthreshold
regions.

FIG. 3. Errors between our electrostatic potential model and the least square method at the source terminal.
045125-5 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 4. Comparisons between electrostatic potential model and the least square method for the different Vch .

FIG. 5. Comparisons between our electrostatic potential model and the least square method for the different t si .

FIG. 6. The difference between ϕ s and ϕ o for the different t si .

045125-6 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 7. Comparisons between our electrostatic potential model and the least square method for the different t ox .

FIG. 8. The difference between ϕ s and ϕ o for the different t ox .

FIG. 9. Comparisons between our electrostatic potential model and the least square method for the different Na .
045125-7 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 10. The difference between ϕ s and ϕ o for the different Na .

According to Figs. 5–8, we can observe that the effects from t si and t ox on ϕs and ϕo . On the one
side, in Figs. 5 and 6, t si has a little influence on ϕs and Vth . However, the absolute results of ϕo in
both accumulation and strong inversion regions increase as t si decreases. On the other side, in Figs. 7
and 8, t ox has a little influence on ϕo and Vth , but the absolute results of ϕs in both accumulation and
strong inversion regions increase as t ox decreases.
Furthermore, we can see in Figs. 9 and 10 that N a affects ϕs , ϕo , and Vth , simultaneously. All of
them are show positive correlation with N a . However, N a has a little effect on the difference between
ϕs and ϕo .

III. DRAIN CURRENT MODEL

A. Drain current model derivation
The conduction of sDG MOSFETs, like a sheet of charge, takes place at the interface between gate
dielectric and channel film. Due to the sub-nanometer scale channel film of sDG MOSFETs, under
the conditions of the gradual channel approximation and the constant mobility along the channel, we
adopt the surface-potential-based charge sheet model (CSM)18 to obtain the drain current expression,
consisting of drift and diffusion currents,22,23 i.e.,
 
Ids = 2 Ids drift + Ids diff . (11)
The drift and diffusion currents are expressed as
ϕsd
W
Ids drift = −µ Qi (ϕs )dϕs , (12)
L
ϕss

ϕsd
W
Ids diff =µ dQi (ϕs ). (13)
L
ϕss

Here, ϕss and ϕsd are the solutions of ϕs at the source and drain terminals, corresponding to
Vch =0V and Vch = Vds , respectively. Vds is the drain-to-source voltage, µ is the charge mobility,
W is the channel width, and L is the channel length. Qi (ϕs ) is the free charge density per unit gate
area in the channel, that is obtained from the Gauss’ law as
 
Qi (ϕs ) = −Cox Vgs − Vfb − ϕs − Qa (14)
where Qa is the doping charge per unit gate area in the channel film in the case of full-depletion,
leading to
045125-8 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 11. Comparisons of output characteristics between our drain current model (solid lines) and Atlas simulation (symbols).

tsi
Qb = −qNa
. (15)
2
Substituting (12)–(15) into (11), the drain current I ds is analytically derived as
" ! # ϕss
W qNa tsi
Ids = µCox −ϕ2s + 2 Vgs − Vfb − + Vt ϕs . (16)
L 2Cox ϕsd

It should be pointed that (16) derived from the charge sheet model is in close-form without any
smoothing functions and in continuity without any fitting parameters, because ϕs and ϕo are also
in both close-form and continuity for all the operational regions from the accumulation to strong
inversion regions of the sDG MOSFETs.

B. Drain current model verification

Firstly, we provide our model verification in the cases of the long and moderate channels of sDG
MOSFETs, respectively. For the 18µm long channel and the 6µm moderate channel, Figs. 11–14
show the predicted I-V characteristics of sDG MOSFETs. Figs. 11 and 13 show the comparisons
of the output characteristics between our model with the Silvaco Atlas simulation results at four
different gate-to-source voltage Vgs , and good agreements have been observed. In Figs. 12 and 14, we
give the predictions about the transfer characteristics at three different drain-to-source voltage Vds ,

FIG. 12. Comparisons of transfer characteristics between our drain current model (solid lines) and Atlas simulation (symbols).
045125-9 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 13. Comparisons of output characteristics between our drain current model (solid lines) and Atlas simulation (symbols).

FIG. 14. Comparisons of transfer characteristics between our drain current model (solid lines) and Atlas simulation (symbols).

FIG. 15. Comparisons of output characteristics between our drain current model (solid lines) and Atlas simulation (symbols).
045125-10 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 16. Comparisons of transfer characteristics between our drain current model (solid lines) and Atlas simulation
(symbols).

the accurate matches are obtained not only in the subthreshold region but also in the strong inversion
region.
Secondly, for the short channel sDG MOSFETs, the short channel effects are prominent, as
shown in Figs. 15 and 16, especially in the strong inversion region due to the pinch-off behavior in
the channel. As such, we take the pinch-off behavior into account by adopting the effective drain-to–
source voltage approach.12 In practice, we substitute the effective drain-to–source voltage Vdseff for
Vch in (3) and (9) to make our model include the pinch-off behavior, i.e.,
Vds
Vdseff = q . (17)
β β
1 + (Vds /Vdsat )

Here, the parameter β governs the transition from Vds to Vdseff , and Vdsat is an extracted saturation
voltage parameter.
Finally, considering the practical validation comes from a comparison with experimental results
of the sDG MOSFETs. we added the comparison between our model with the experimental results,24
as shown in Figs. 17 and 18. We can observe that our model can be used to simulate the I-V
characteristics of the sDG MOSFETs coming into sub-nanometer scale.

FIG. 17. Comparisons of output characteristics between our drain current model (solid lines) and experimental results24
(symbols).
045125-11 Yu et al. AIP Advances 8, 045125 (2018)

FIG. 18. Comparisons of transfer characteristics between our drain current model (solid lines) and experimental results24
(symbols).

IV. CONCLUSION
In this paper, we have derived an analytical drain current model for symmetric double-gate
MOSFETs. Such a model starts from the fast derivation of the surface and central potentials. In
particularly, the solutions of the surface and central potentials are continuous without any smoothing
functions from the accumulation to strong inversion regions. Then, we verify the electrostatic potential
model with the results in the least square method. Furthermore, we use the surface potential results
to calculate directly the drain current based on the charge sheet model. Finally, we validate the drain
current model by using Silvaco Atlas simulation results and experimental data, and obtain the good
agreements over a wide range of bias voltages and channel lengths. As a result, this model is suitable
to be adopted as a useful tool implemented into a circuit simulator.

ACKNOWLEDGMENTS
This work was funded partially by the Scientific Research Funds of Huaqiao University under
grant 600005-Z16X0114 and partially by the Scientific Research Funds for the Young Teachers of
Fujian Province under grant JAT170034.
1 ITRS — International Technology Roadmap for Semiconductor, 2009.
2 I. Ferain, C. A. Colinge, and J.-P. Colinge, Nature 479, 310 (2011).
3 ITRS — International Technology Roadmap for Semiconductor, 2014.
4 Y. Taur, X. Liang, W. Wang, and H. Lu, IEEE Electron Device Lett. 25, 107 (2004).
5 N. Arora, “MOSFET models for VLSI circuit simulation: Theory and practice,” Shrewsbury, 1st ed. (Springer-Verlag,

New York, NY, USA, 1993), pp. 5–8.

6 J. Watts et al., “Advanced compact models for MOSFETs,” in Proc. Workshop Compact Models-Nanotech, 2005, pp. 9–12.
7 A. Ortiz-Conde, F. J. Garcı́a-Sánchez, J. Muci, S. Malobabic, and J. J. Liou, IEEE Trans. Electron Devices 54, 131 (2007).
8 Y. Taur, IEEE Electron Device Lett. 21, 245 (2004).
9 B. Yu, H. Lu, M. Liu, and Y. Taur, IEEE Trans. Electron Devices 54, 2715 (2007).
10 O. Moldovan, D. Jiménez, J. Roig, F. A. Chaves, and B. Iñiguez, IEEE Trans. Electron Devices 54, 1718 (2007).
11 B. González, J. B. González, B. Roldán, A. Iñiguez, and A. Cerdeira, Microelectron. J. 46, 320 (2015).
12 J. Huang, W. Deng, X. Zheng, and X. Jiang, IEEE Trans. Electron Devices 57, 2607 (2010).
13 A. Sehgal, T. Mangla, S. Chopra, M. Gupta, and R. S. Gupta, Semicond. Sci. Technol. 21, 370 (2006).
14 F. Yu, W. Deng, J. Huang, X. Ma, and J. J. Liou, IEEE Trans. Electron Devices 64, 2221 (2017).
15 T. K. Chiang and M. L. Chen, Solid-State Electron. 51, 387 (2007).
16 S.-C. Lo, Y. Li, and S.-M. Yu, Mathematical and Computer Modelling 46, 180 (2007).
17 J. He, F. Liu, X.-Y. Zhou, J. Zhang, and L.-N. Zhang, Chin. Phys. B 20, 016102 (2011).
18 J. R. Brews, Solid-State Electron. 21, 345 (1978).
19 A. Ben-Israel, J. Math. Anal. Appl. 15, 243 (1966).
20 J.-M. Sallese, N. Chevillon, C. Lallement, B. Iñiguez, and F. Prégaldiny, IEEE Trans. Electron Devices 58, 2628 (2011).
21 F. Liu, J. He, J. Zhang, Y. Chen, and M. Chan, IEEE Trans. Electron Devices 55, 3494 (2008).
22 R. F. Pierret and J. A. Shields, Solid-State Electron. 26, 143 (1983).
23 A. Ortiz-Conde, R. Herrera, P. E. Schmidt, F. J. G. Sánchez, and J. Andrian, Solid-State Electron. 9, 1291 (1992).
24 J. Song, B. Yu, Y. Yuan, and Y. Taur, IEEE Trans. Circuits and Systems—I 56, 1858 (2009).