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  • FIFO

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    AFSAL A
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    This document describes a FIFO module with the following functionality: 1. It contains a 16 entry buffer to store 32-bit data words written by a write clock domain and read by a read clock domain independently. 2. Status signals indicate when the FIFO is empty (read and write pointers match) or full (write pointer is one ahead of read pointer). 3. A testbench is provided to generate read/write clocks and signals to test the empty/full conditions in different scenarios by changing the read/write pointers.

    Original Description:

    questions on fifo

    Original Title

    FIFO (1)

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    This document describes a FIFO module with the following functionality: 1. It contains a 16 entry buffer to store 32-bit data words written by a write clock domain and read by a read clock domain independently. 2. Status signals indicate when the FIFO is empty (read and write pointers match) or full (write pointer is one ahead of read pointer). 3. A testbench is provided to generate read/write clocks and signals to test the empty/full conditions in different scenarios by changing the read/write pointers.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    5 views5 pages

    FIFO

    Uploaded by

    AFSAL A
    This document describes a FIFO module with the following functionality: 1. It contains a 16 entry buffer to store 32-bit data words written by a write clock domain and read by a read clock domain independently. 2. Status signals indicate when the FIFO is empty (read and write pointers match) or full (write pointer is one ahead of read pointer). 3. A testbench is provided to generate read/write clocks and signals to test the empty/full conditions in different scenarios by changing the read/write pointers.

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    © All Rights Reserved
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    of 5

    // fifo design

    module fifo5 (output reg [31:0]rdata,


    output wfull,rempty,

    input [31:0] wdata,


    input winc, wclk, wrst_n, rinc, rclk, rrst_n);

    parameter DSIZE = 32;


    parameter ASIZE = 4;

    reg [ASIZE:0] wptr, wrptr;


    reg [ASIZE:0] rptr, rwptr;

    reg [DSIZE-1:0] ex_mem [0:15];

    //data write
    always @(posedge wclk or negedge wrst_n)
    if (!wrst_n) wptr <= 0;
    else if (winc && !wfull) begin
    ex_mem[wptr[ASIZE-1:0]] <= wdata;
    wptr <= wptr+1;
    end

    //write pointer
    always @(posedge wclk or negedge wrst_n)
    if (!wrst_n) wrptr <= 0;
    else wrptr <= rptr;

    //read data
    always @(posedge rclk or negedge rrst_n)
    if (!rrst_n) rptr <= 0;
    else if (rinc && !rempty) begin
    rdata = ex_mem[rptr[ASIZE-1:0]];
    rptr <= rptr+1;
    end

    //read pointer
    always @(posedge rclk or negedge rrst_n)
    if (!rrst_n) rwptr <= 0;
    else rwptr <= wptr;

    assign rempty = (rptr == rwptr);


    assign wfull = ((wptr[ASIZE-1:0] == wrptr[ASIZE-1:0]) &&
    (wptr[ASIZE] != wrptr[ASIZE] ));

    endmodule

    //fifo testbench

    // Code your testbench here


    // or browse Examples
    module fifo_tb5();

    wire rempty,wfull;
    wire [31:0] rdata;

    reg [31:0] wdata;


    reg winc,wclk=1,wrst_n;
    reg rinc,rclk=1,rrst_n;

    integer i;

    fifo5 fifo5(.rdata(rdata),.rempty(rempty),.wfull(wfull),.wdata(wdata),
    .winc(winc),.wclk(wclk),.wrst_n(wrst_n),
    .rinc(rinc),.rclk(rclk),.rrst_n(rrst_n));

    //Generating read and write clock


    always #0.8 rclk=~rclk;
    always #0.6 wclk=~wclk;

    //Burst Data
    initial fork
    wdata=32'h00000001;
    for(i=0;i<65;i=i+1)
    #1.5 wdata=wdata+32'h00000001;

    //read and write reset


    wrst_n=1'b0;
    rrst_n=1'b0;
    #0.5 wrst_n=1'b1;
    #0.5 rrst_n=1'b1;

    //test case one


    //wptr == 00011 and rptr == 00011--> empty=1
    #8 winc=1'b0;
    rinc=1'b1;

    //test case two


    //wptr==10011 and rptr==00011--> full=1
    #10 winc=1'b1;
    #19 rinc=1'b0;

    //test case three


    //wptr== 10011 and rptr==10011

    #47 winc=1'b0;
    #20 rinc=1'b1;

    //test case four


    //wptr==00011 and rptr==10011

    #48 winc=1'b1;
    #52 rinc=1'b0;

    join

    endmodule
    FIFO full test

    FIFO wptr == 00011 and rptr == 00011--> empty=1

    wptr==10011 and rptr==00011--> full=1


    wptr== 10011 and rptr==10011 → empty ==1

    wptr==00011 and rptr==10011 -->full==1

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