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This laboratory will provide you with practice and experience writing
VHDL descriptions. Specificially, you will be interfacing to an LCD
display and register file (memory). To complete these tasks, you will
have to design a counter, register file, and state machine controller.
Starting out
Create a new Xilinx project for this lab and create the top-level file
with the entity statement shown in Figure L3. The pin assignments for
the top-level I/O signals are shown in Figure L3.
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ENTITY top_level IS
PORT ( clock : IN STD_LOGIC;
reset_in : IN STD_LOGIC;
rs : OUT STD_LOGIC;
rw : OUT STD_LOGIC;
enable : OUT STD_LOGIC;
lcd_data : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END top_level;
COMPONENT BUFGP
PORT ( I : IN STD_LOGIC;
O : OUT STD_LOGIC );
END COMPONENT;
BEGIN
U1: BUFGP
PORT MAP ( I => reset_in,
O => reset );
...
END behavioral;
Figure L3.2: The pin assignments for the top-level I/O signals. These assume
that the Digilab IO2 peripheral board is connected to the Digilab 2E board via
connectors C and D.
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High to indicate that the address and data lines are valid. Note that
all three of these signals can be set at the same time (i.e., in the same
state). Also, be aware that the LCD driver looks for a pulse on the
write line, so you must take it Low after each character is written.
When your completed project compiles correctly, ask the TA for the
Digilab DIO2 peripheral board and plug it into connectors C and D on
your Digilab 2E board. Then apply power to the board and download
your design file to the FPGA.
Remember to get checked-off by the teaching assistant before continuing!
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