Package Dimensions: Single-Chip NTSC Color TV IC

Ordering number : ENN5841
Monolithic Linear IC
LA7615
Single-Chip NTSC Color TV IC
Overview Package Dimensions

The LA7615 is an NTSC color TV IC that supports unit: mm
computer control over an I2C bus. In addition to improved 3071-DIP64S
quality and increased functionality in color TV products,
this IC supports the development of a TV set product line [LA7615]
in software and the simplification of end product design.

64 33
The provision of an I2C bus means that this product can
also respond to desires for increased total manufacturing
19.05
productivity, including improved automation of computer
16.8
controlled production lines.
0.25
1 32
Functions 57.2
• I2C bus control, VIF, SIF, Y, C, and deflection circuits
3.2 5.0max
4.0
integrated on a single chip.
0.51min
0.95 0.48 1.78 1.01
Features
• Pursuit of higher integration levels SANYO: DIP64S
The LA7615 integrates VIF, SIF, luminance,
chrominance, and deflection (horizontal and vertical
synchronization) circuits, A/V switching, and power
supply control on a single chip.
• Bus control for reduced external component counts and
mechanical adjustment points
All the LA7615 signal-processing circuits can be
controlled and adjusted digitally over the I2C bus. All
adjustments, both those required during manufacture and
the user controls, can be controlled over the I2C bus, and
both function selection and characteristics settings can
be performed in software over the I 2 C bus. This
increases flexibility in designing a product line of TV
sets and also enhances productivity by allowing mixed
production runs.
While this device supports multifunction and good
performance, it is also economical in that it achieves
reduced power and reduced pin count.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91799RM (OT) No. 5841-1/39
LA7615
Specifications
Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
V2 max 9.6 V
V17 max 9.6 V
Maximum supply voltage
V32 max 9.6 V
V60 max 9.6 V
Maximum supply current I24 max 30 mA
Allowable power dissipation Pd max Ta ≤ 65°C 1.5 W
Operating temperature Topr –10 to +65 °C
Storage temperature Tstg –55 to +150 °C
Operating Conditions at Ta = 25°C

Parameter Symbol Conditions Ratings Unit
V2 7.6 V
V17 7.6 V
Recommended supply voltage
V32 7.6 V
V60 7.6 V
Recommended supply current I24 24 mA
V2 op 7.3 to 7.9 V
V17 op 7.3 to 7.9 V
Operating supply voltage range
V32 op 7.3 to 7.9 V
V60 op 7.3 to 7.9 V
Operating supply current range I24 op 20 to 30 mA
Functional Description
<VIF/SIF Functions>
In addition to a PLL synchronous detection system, the IF block also adopts a split system in which the VIF signal and
the SIF signal are processed separately.
• Low-level VCO
The LA7615 achieves a significant reduction in beat generation due to interference by lowering the VCO oscillator
level from that used in earlier ICs.
• Adjustment-free VCO coil implemented using bus control
By compensating for manufacturing variations in the VCO coil using bus control, the LA7615 eliminates coil
adjustment from the manufacturing line.
• Built-in 4.5 MHz trap
The LA7615 incorporates an on-chip trap that also provides a video equalizer function. Thus the number of external
trap, inductor, and capacitor components is reduced.
• Built-in SIF FM detector: 4.5 MHz quadrature detection
• The video signal and FM demodulated signal levels can be controlled from the serial bus.
The improved precision associated with controlling the output level over the serial bus makes it easier to design the
interface with the following stage.
• Built-in buzz canceler
Allows high performance to be maintained even during stereo reception.
• Built-in video switch (INT/EXT(AUX) switching circuit)
Built-in AUX input switching circuit means that the dedicated switching ICs required can be reduced. Also, the ability to
control this switch from the serial bus makes it easier to design the peripheral wiring pattern.
• Dedicated IF video signal output pin
The provision of this pin makes it easier to design end products that support PIP and similar features.
<Luminance and Chrominance Circuits>

These blocks have been designed to minimize the use of external components as much as possible. The filter circuits are
now integrated on the same chip, and not only the adjustment circuits, but also the function selection and characteristics
modifications functions can be controlled over the serial bus. As a result, basically all the signal processing from input to
output can be performed with only the addition of the chrominance circuit VCO crystal and the APC filter circuit.
No. 5841-2/39
LA7615
Furthermore, this IC also supports high image quality systems and responds to needs from a diverse range of end
products.
• Two independent inputs for the luminance and chrominance signals and switching between the Y1/C1 and Y2/C2 inputs
• Video muting on/off switch
• Built-in filters (The filter f0 adjustment function can be used to select the filter characteristics.)
Chrominance system: Bandpass filter (symmetric and asymmetric types)
Luminance system: Color trap and delay line
<f0 Mode Selection>

Mode f0 = Y signal Chroma signal
Trap f0 *Total delay BPF *Total 500 ns delay
0 3.58 MHz 500 ns Asymmetric (peaking type) 515 ns
1 4.2 MHz 510 ns
Symmetric 535 ns
2 5.0 MHz 520 ns
3 10.0 MHz 265 ns Bypass 265 ns
*: Reference values
<Luminance System Circuit>

• Built-in high image quality variable-type luminance system filter (color trap and delay line)
Luminance filter mode selection (f0 adjustment)
Four modes are provided: 3.58 MHz trap, 4.2 MHz trap, 5.0 MHz wide, and 10.0 MHz high band.
• Peaking (sharpness) control
Aperture type control implemented using the delay line
The emphasis frequency is automatically selected according to the f0 mode using the delay line.
One of the four frequencies 2.2, 2.6, 3.0, or 4.9 MHz is emphasized according to which of the f0 modes (3.58 MHz
trap, 4.2 MHz trap, 5.0 MHz wide, or 10.0 MHz high band) is used.
• Adaptive coring
For low-level signals, the above peaking is suppressed to reduce the image contamination due to that peaking.
The coring level is automatically adjusted according to the amplitude of the input signal.
• Black stretch circuit: Can be turned on or off under control of the serial bus interface.
• SYO (Selected luminance (Y) output)
One of the Y1/Y2 inputs is selected, and that input signal is output as the sync separator circuit signal directly.
However, the DC level of that signal is clamped at 1/2 VCC.
Also, this signal can be used for closed captions or as a velocity modulation.
• Support for analog/digital OSD
Amplitude level limiting is applied to digital input signals internally to the IC.
• Contrast and brightness controls
• ABL (automatic beam limiter)
Three-pin system (IB IN, BRT ABL FILT, and CONTRAST ABL FILT pins), mode switching under control of serial
bus data.
• R, G, and B output drive and bias adjustments
• Sub-bias (brightness) control
The DC level of each of the R, G, and B signals can be adjusted over a 4-step (2-bit) range.
<Chrominance Circuit>
• Built-in chrominance bandpass filter
Chrominance system filter mode selection: bandpass filter peaking/symmetric type selection and chrominance
bandpass filter bypass on/off setting
• Auto Flesh: Flesh tone correction (on/off)
• Overload (on/off)
Limits the saturation of the color when the ratio of the burst and color signals is large, i.e. when the color is highly
saturated.
• Color phase and saturation controls
• Demodulation angle: 104°
No. 5841-3/39
LA7615
<Deflection Circuits>
Dedicated sync separator circuit input pin
The horizontal deflection circuit adopts a dual AFC circuit, and the horizontal oscillator uses the 32fH (503 kHz) pulse
signal as the horizontal decrement counter clock.
The following are the main settings for the horizontal output system that can be controlled over the serial bus interface.
These settings support even more efficient end product design.
• AFC gain (first loop gain control)
• APC gain (second loop gain control)
• Horizontal duty cycle
• Horizontal phase
*: The vertical deflection circuit adopts a decrement counter system, and provides constantly adjustment-free and stable
vertical synchronization for any type of signal, from TV on air, to weak reception conditions, to VCR signals.
Furthermore, this circuit uses an internal capacitor to implement a ramp generator, and allows the corrections
described later in this document to be applied to correct image distortion and other problems due to manufacturing
variations in the TV tube itself.
<Horizontal Circuit Functions>

• High-stability adjustment-free horizontal oscillator that uses a ceramic oscillator element
• Dual AFC circuit
• Multi-mode control of the AFC gain (first loop gain)
• Horizontal duty and phase controls
• Geometrical distortion correction: East-west DC (horizontal size)
East-west amplitude (horizontal pin-cushion distortion correction)
Corner pin
East-west corner 1
East-west corner 2
Tilt adjustment
• Sync killer
<Vertical Circuit Functions>

• Forcible non-standard mode support (standard mode: 262.5 H)
• Vertical size/linearity and vertical DC (vertical position) adjustments, vertical S-curve correction
• V-comp adjustment (Corrects for changes in the vertical size due to variations in the luminance.)
• Vertical killer
<Power System>
PWM circuits have come to be widely used in TV set power supplies in recent years. This IC integrates parts of the
power supply circuit (the pulse generator and its control system) and allows the supply voltage (high B) to be adjusted
over the serial bus.
No. 5841-4/39
LA7615
Bus Control
General Functions
ON/OFF SW 1 bit
Video muting switch 1 bit
VIF/SIF
Video signal switching 1 bit
RF AGC delay 6 bits
IF AGC SW 1 bit
PLL tuning 7 bits
APC detector adjustment 6 bits
AFT defeat switch 1 bit
Noise inverter defeat switch 1 bit
Video level 3 bits
Sound 4.5 MHz trap 4 bits
FM level 4 bits
F0 fast (FM detection speed) 1 bit
Luminance/Chrominance Systems
Y/C input selection (one of two inputs) switch 1 bit
Luminance (Y) F0 adjustment (filter control) 2 bits
Chrominance signal bandpass filter mode switch 1 bit
Chrominance signal bandpass filter bypass switch 1 bit
Black stretch on/off switch 1 bit
Peaking (sharpness) control 5 bits
Coring on/off switch 1 bit
Auro flesh on/off 1 bit
Overload switch 1 bit
Contrast control 6 bits
Brightness control 6 bits
Tint control 7 bits
Saturation control 7 bits
RGB bias adjustment 6 bits each
RGB bias adjustment 7 bits each
Sub-brightness control 2 bits each
Brightness ABL operating point control 3 bits
Brightness ABL mode defeat switch 1 bit each
Emergency ABL defeat switch 1 bit
Deflection System
AFC gain (sync killer) 2 bits
APC gain 2 bits
Horizontal duty adjustment 2 bits
Horizontal phase adjustment 4 bits
Geometrical distortion correction
EAST-WEST DC 5 bits
EAST-WEST AMPLITUDE 4 bits
East-west corner 1/2 3 bits each
Tilt adjustment 4 bits
Vertical linearity adjustment 4 bits
Vertical S-curve correction 4 bits
Vertical size adjustment 7 bits
Vertical DC adjustment 6 bits
Standard/nonstandard mode switch 1 bit
VERTICAL KILL 1 bit
V-COMP adjustment 3 bits
DAC REF. (+B TRIM) 4 bits
Others: Status Register
POWER ON RESET 1 bit
X-ray protection switch 1 bit
Horizontal lock detection 1 bit
AFT and RF AGC status discrimination 2 bits each
No. 5841-5/39
LA7615
Vertical Linearity
Wide Narrow
Narrow Wide
A10048
Vertical S-Curve Correction
Wide Narrow
Narrow Wide
Wide Narrow
A10049
Tilt
A10050
East-West Amp
A10051
Corner Pin
East-west corner 1
East-west corner 2
A10052
The distortion correction operation is symmetric left to right.
No. 5841-6/39
LA7615
Bus : Control Register Bit Allocation Map

Control Register Bit Allocations
IC address Sub address MSB Data bits LSB
IC Add7 → Add0 ¥ Add7 → Add0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1011 1010 0000 0000 1 On/Off Video AFC gain/sync kill
mute (b1) (b0)
0001 1 APC gain B+ trim
(b1) (b0) (b3) (b2) (b1) (b0)
0010 1 Hor duty cycle Horizontal phase
(b1) (b0) (b3) (b2) (b1) (b0)
0011 1 BNI RF AGC delay
defeat (b5) (b4) (b3) (b2) (b1) (b0)
0100 1 IF AGC AFT FM level
defeat defeat (b4) (b3) (b2) (b1) (b0)
0101 1 VCO free running
(b6) (b5) (b4) (b3) (b2) (b1) (b0)
0110 1 4.5 MHz trap
(b3) (b2) (b1) (b0) (b2) (b1) (b0)
0111 1 Video IF APC offset adjust.
switch (b5) (b4) (b3) (b2) (b1) (b0)
1000 1 Vertical Vertical DC
kill (b5) (b4) (b3) (b2) (b1) (b0)
1001 1 Countdown mode East-west DC
(b1) (b0) (b4) (b3) (b2) (b1) (b0)
1010 1 East-west amp
(b3) (b2) (b1) (b0)
1011 1 Vertical comp. East-west tilt
(b2) (b1) (b0) (b3) (b2) (b1) (b0)
1100 1 Vertical size
(b6) (b5) (b4) (b3) (b2) (b1) (b0)
1101 1 Vertical linearity
(b3) (b2) (b1) (b0)
1110 1 FM mode Vertical S-correction
switch (b3) (b2) (b1) (b0)
1111 1 East-west bottom corner East-west top corner
(b2) (b1) (b0) (b2) (b1) (b0)
Bits are transmitted in this order
No. 5841-7/39
LA7615
Bus : Control Register Bit Allocation Map

Control Register Bit Allocations (cont)
IC Add7 → 0 Add7 → Add0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1011 1010 0001 0000 1 Red bias
(b6) (b5) (b4) (b3) (b2) (b1) (b0)
0001 1 Green bias
(b6) (b5) (b4) (b3) (b2) (b1) (b0)
0010 1 Blue bias
(b6) (b5) (b4) (b3) (b2) (b1) (b0)
0011 1 Red drive
(b5) (b4) (b3) (b2) (b1) (b0)
0100 1 Green drive
(b5) (b4) (b3) (b2) (b1) (b0)
0101 1 Blue drive
(b5) (b4) (b3) (b2) (b1) (b0)
0110 1 Blue sub bias Red sub bias Green sub bias Y/C
(b1) (b0) (b1) (b0) (b1) (b0) switch
0111 1 Brightness control
(b5) (b4) (b3) (b2) (b1) (b0)
1000 1 Pix control
(b5) (b4) (b3) (b2) (b1) (b0)
1001 1 Coring Peaking control
switch (b4) (b3) (b2) (b1) (b0)
1010 1 F0 select Chroma Auto Chrom Over
(b1) (b0) BPF flesh bypass load
1011 1 Tint control
(b6) (b5) (b4) (b3) (b2) (b1) (b0)
1100 1 Color control
(b6) (b5) (b4) (b3) (b2) (b1) (b0)
1101 1 ABL Mid Stp EMG Bright ABL threshold
defeat defeat defeat (b2) (b1) (b0)
1110 1 Test register 1 Test register 2
(b3) (b2) (b1) (b0) (b2) (b1) (b0)
1111 1 Test regster 3 Black Stretch Blanking Reserved
(b3) (b2) (b1) (b0) defeat defeat
Bits are transmitted in this order
Table 8 : Status Register Bit Allocation Map

Status Register Bit Allocations
IC Add7 → Add0 Add7 → Add0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1011 1010 0001 0000 Pon XRay Horiz On/off AFT status RF AGC status
lock
0001 1 1 1 1 1 1 1 1
No. 5841-8/39
LA7615
Bus : Control Register Truth Table

Control Register Truth Table
Register 0 HEX 1 HEX 2 HEX 3 HEX
On/off Off On na na
Video mute Active Mute na na
AFC gain/sync Kill Sync Kill Low gain (auto mode) Mid gain High gain
BNI defeat Enable BNI Defeat na na
IF AGC defeat Enable AGC Defeat na na
AFT defeat Enable AFT Defeat na na
Video switch IF video Aux video na na
Vertical Kill Vertical active Vertical Killed na na
Countdown mode Standard Non-standard 50 Hz 48 Hz
FM mode switch Normal Fast na na
Y/C switch Y1/C1 IN Y2/C2 IN na na
Coring switch Defeat Enable na na
F0 select 3.58 Trap 4.20 Trap 5.00 APF 10.0 APF
Chrom BPF Symmetrical Peaker na na
Autoflesh Off On na na
Chroma bypass BPF Bypass na na
Over load Off Active na na
Bright ABL defeat Enable Defeat na na
Bright mid stop defeat Enable Defeat na na
Emergency ABL defeat Enable Defeat na na
Black Str defeat Enable Defeat na na
Blanking defeat Enable Defeat na na
Bus : Status Register Truth Table

Status Register Truth Table
Register 0 HEX 1 HEX 2 HEX 3 HEX
POR Inactive Low standby detected na na
XRP Inactive XRP fault detected na na
Horizontal lock Locked Unlocked na na
On/off Off On na na
AFT IF frequency in high IF frequency in range na IF frequency is low
RF AGC RF AGC voltage is Low. RF AGC voltage is in range. na RF AGC voltage is High.
No. 5841-9/39
LA7615
Initial Condition
Function
On/off 1 HEX
Video mute 0 HEX
AFC gain & sync Kill 1 HEX
APC gain 3 HEX
B+ trim 8 HEX
Horizontal duty 1 HEX
Horizontal phase 8 HEX
BNI defeat 0 HEX
RF AGC delay 20 HEX
IF AGC defeat 0 HEX
AFT defeat 0 HEX
FM level 10 HEX
IF VCO free running 40 HEX
4.5 trap 8 HEX
Video level 4 HEX
Video switch 0 HEX
IF APC offset 20 HEX
Vertical Kill 0 HEX
Vertical DC 20 HEX
Countdown mode 0 HEX
East/west DC 10 HEX
East/west amplitude 8 HEX
Vertical comp. 0 HEX
East/west tilt 8 HEX
Vertical size 40 HEX
Vertical linearity 8 HEX
FM mode switch 0 HEX
Vertical S-correction 8 HEX
East/west bottom 0 HEX
East/west top corner 0 HEX
Red bias 00 HEX
Green bias 00 HEX
Blue bias 00 HEX
Red drive 3F HEX
Green drive 3F HEX
Blue drive 3F HEX
Blue sub bias 2 HEX
Red sub bias1 2 HEX
Green sub bias 2 HEX
Y/C switch 0 HEX
Brightness control 20 HEX
Pix control 20 HEX
Coring switch 0 HEX
Peaking control 00 HEX
F0 select 1 HEX
Chroma BPF 0 HEX
Autoflesh 0 HEX
Chroma bypass 0 HEX
Over load 0 HEX
Tint control 40 HEX
Color control 40 HEX
Bright ABL defeat 0 HEX
Bright mid stop 0 HEX
Emergency ABL defeat 0 HEX
Bright ABL threshold 0 HEX
Test registers 1, 2, 3 0 HEX
Black strech defeat 1 HEX
Blanking defeat 0 HEX
No. 5841-10/39
Standby 6.3VDC
Vcc 3.0VDC
ON/OFF
BIT
Power Up Sequence <Reference>
Registers
(TR1-TR2)
Video.Mute
BIT
XRP BIT
LA7615
(STATUS)
Pon BIT
(STATUS)
Run.Vcc 7.3VDC
stable
Registers
(TR3-TR31)
time ≥ 2ms ON/OFF Initialize ON/OFF Initialize Mute

=0 TR1 to TR2 =1 TR3 to TR31 =0
After Standby Vcc reaches 3.0VDC, the microcontroller has to wait 2ms in order to intitialize the HC Interface in LA7615. A10053
No. 5841-11/39
LA7615
Electrical Characteristics at Ta = 25°C, VCC = V2 = V17 = V32 = V60 = 7.6 V, ICC = I24 = 24 mA
Ratings
Parameter Symbol Conditions Unit
min typ max
[Circuit Voltages and Currents]
Horizontal supply voltage HVCC 7.2 7.6 8 V
IF power supplly current (V2) I2 (IFICC) IF AGC : 5 V 28 43 58 mA
Vertical supply current (V17) I17 (DEFICC) 10 13 16 mA
Video/chrominance supply current (V32) I32 (YCICC) 65 85 105 mA
FM supply current (V60) I60 (FMICC) 5.5 8.5 11.5 mA
[VIF Block]
No signal AFT output voltage V14 With no input signal 2.8 3.8 4.8 Vdc
No signal video output voltage V53 With no input signal 4.7 4.9 5.1 Vdc
After APC, PLL, and D/A converter
APC pull-in range (U) fPU 1 MHz
adjustment
After APC, PLL, and D/A converter
APC pull-in range (L) fPL 1 MHz
adjustment
Maximum RF AGC voltage V4H CW = 91 dBµ, DAC = 0 7.7 8.2 9.0 Vdc
Minimum RF AGC voltage V4L CW = 91 dBµ, DAC = 63 0 0.2 0.4 Vdc
RF AGC Delay Pt (@DAC = 0) RFAGC0 DAC = 0 96 dBµ
RF AGC Delay Pt (@DAC = 63) RFAGC63 DAC = 63 86 dBµ
Maximum AFT output voltage V14H CW = 93 dBµ, frequency change 6.2 6.5 7.6 Vdc
Minimum AFT output voltage V14L CW = 93 dBµ, frequency change 0.5 0.9 1.2 Vdc
AFT detection sensitivity Sf CW = 93 dBµ, frequency change 33 25 17 mV/kHz
4.5 MHz attenuation TRAP V100 kHz/V4.5 MHz –35 –32 dB
Video output amplitude VO53 93 dBµ, 87.5% Video MOD 1.8 2 2.2 Vp-p
Synchronizing signal tip level V53TIP 93 dBµ, 87.5% Video MOD 2.4 2.6 2.8 Vdc
Input sensitivity VIN Output –3 dB 43 46 dBµ
Vide/sync ratio (@100 dBµ) V/S 100 dBµ, 87.5% Video MOD 2.4 2.5 3
Differential gain DG 93 dBµ, 87.5% Video MOD 2 10 %
Differential phase DP 93 dBµ, 87.5% Video MOD 2 10 deg
Video signal-to-noise ratio S/N CW = 93 dBµ 55 58 dB
920 kHz beat level I920 V3.58 MHz/V920 kHz –57 –50 dB
[SIF Block]
[1st.SIF]
4.5 MHz conversion gain SGG 21 26 31 dB
4.5 MHz output level SVO 91 96 101 dB
First SIF maximum input SVM –1 0 +1 dB
[SIF Block]
FM detection output voltage SOADJ 414 424 434 mVrms
FM limiting sensitivity SLS 50 dBµ
FM detector output bandwidth SF 50 100k Hz
FM detector output distortion STHD 1 %
AM rejection ratio SAMR 40 dB
SIF. Signal-to-noise ratio SSN 74 dB
[Chrominance Block]
ACC amplitude characteristics 1 ACCM1 Input: +6 dB/0 dB, 0 dB = 40 IRE 0.8 1.0 1.2 times
ACC amplitude characteristics 2 ACCM2 Input: –14 dB/0 dB 0.8 1.0 1.1 times
B-Y/Y amplitude ratio CLRBY 75 100 120 %
Color control characteristics 1 CLRMN Color: max/normal 1.7 2.0 2.3 times
Color control characteristics 2 CLRMN Color: max/min 33 40 50 dB
Color control sensitivity CLRSE 1 2 4 %/bit
Tint center TINCEN TINT NOM –10 +5 deg
Tint control max TINMAX TINT max 30 45 60 deg
Tint control min TINMIN TINT min –60 –45 –30 deg
Tint control sensitivity TINSE 0.7 2.0 deg/bit
Demodulated output ratio: B-Y/R-Y BR 1.06 1.19 1.32
Demodulated output ratio: G-Y/R-Y GR 0.34 0.40 0.46
Continued on next page.
No. 5841-12/39
LA7615
Continued from preceding page.
Ratings
min typ max
Demodulation angle B-Y/R-Y ANGBR 99 104 109 deg
Demodulation angle G-Y/R-Y ANGGR –146 –136 –127 deg
Killer operating point KILL 0 dB = 40IRE –32 –26 –22 dB
Chrominance VCO free-running frequency CVCOF Deviation from 3.579545 MHz –250 +250 Hz
Chrominance pull-in range (+) PULIN+ 350 Hz
Chrominance pull-in range (–) PULIN– –350 Hz
Auto Flesh characteristics: 73° AF073 8 20 30 deg
Auto Flesh characteristics: 118° AF118 –7 0 +7 deg
Auto Flesh characteristics: 163° AF163 –30 –20 –8 deg
Overload characteristics 1 OVL1 3.2 4.7
[Chrominance Bandpass Filter Block]
Peaking amplitude characteristics: 3.08 MHz CPE308 Referenced to 3.48 MHz –5 –3 –1 dB
Peaking amplitude characteristics: 3.88/3.28 MHz CPE Referenced to 3.28 MHz –0.5 +1.5 +3.5 dB
Peaking amplitude characteristics: 4.08/3.08 MHz CPE05 Referenced to 3.08 MHz –5.0 2.5 –1 dB
Bandpass amplitude characteristics: 3.08 MHz CBP308 Referenced to 3.48 MHz –5 –3 –1 dB
Bandpass amplitude characteristics: 3.88/3.28 MHz CBP Referenced to 3.28 MHz –2 0 +2 dB
Bandpass amplitude characteristics: 4.08/3.08 MHz CBP05 Referenced to 3.08 MHz –2.5 0 +2.5 dB
[Video Block]
Video overall gain (at maximum contrast) CONT63 10 12 14 dB
Contrast adjustment characteristics (normal/max) CONT32 –7.5 –6.0 –4.5 dB
Contrast adjustment characteristics (min/max) CONT0 –15 –12 –9 dB
Video frequency characteristics: f0 = 3 Yf03 –6.0 –3.5 0.0 dB
Chrominance trap level: f0 = 0 Ctrap –23 –15 dB
DC restoration ClampG 95 100 105 %
Luminance delay: f0 = 1 YDLY 480 505 530 ns
Maximum black stretch gain BKSTmax 12 16 20 IRE
Black stretch threshold (40 IRE ∆black) BKSTTH –2 0 +2 IRE
Sharpness variation range (normal) Sharp16 4 6 8 dB
(max) Shaprp31 9.0 11.5 14.0 dB
(min) Shapr0 –6.0 –3.5 –1.0 dB
Horizontal/vertical blanking output level RGBBLK 1.4 1.7 2.0 V
[OSD Block]
OSD fast switch threshold FSTH 1.7 1.9 2.2 V
RGB output level: red ROSDH 120 165 200 IRE
RGB output level: green GOSDH 70 120 140 IRE
RGB output level: blue BOSDH 85 120 155 IRE
Analog OSD output level RRGB 1.12 1.4 1.68 Ratio
Gain matching Linearity LRRGB 45 50 60 %
No. 5841-13/39
LA7615
Ratings
min typ max
Analog OSD green output level GRGB 0.8 1.0 1.2 Ratio
Gain matching Linearity LGRGB 45 50 60 %
Analog OSD blue output level BRGB 0.8 1.0 1.2 Ratio
Gain matching Linearity LBRGB 45 50 60 %
[RGB Output (cutoff and drive) Block]
Brightness control (normal) BRT32 2.0 2.35 2.7 V
High brightness (max) BRT63 15 20 25 IRE
Low brightness (min) BRT60 –25 –20 –5 IRE
Cutoff control (min) Vbias0 1.6 2.0 2.4 V
(bias control) (max) Vbias128 2.8 3.2 3.6 V
Cutoff contrad Resolution Vbiassns 3 4 6 mV/bit
Sub-bias control resolution Vsbiassns 160 220 280 mV/bit
Drive adjustment: maximum output RGBout63 2.4 3.0 3.6 Vp-p
Output attenuation RGBout0 7 9 11 dB
[Deflection Block]
Sync separator circuit sensitivity Ssync 10 15 IRE
Horizontal free-running frequency deviation ∆fH 15.634 15.734 15.834 kHz
Horizontal pull-in range fH PULL ±400 Hz
Horizontal output pulse width @0 Hduty0 ON time, Hduty : 0 36.0 37.5 39.0 µs
Horizontal output pulse saturation voltage VHsat 0.4 V
Horizontal output pulse phase HPHCEN 9.5 10.5 11.5 µs
Horizontal position adjustment range HPHrange 4 bits ±2 µs
Horizontal position adjustment maximum variation HPHstep 350 ns
X-ray protection circuit operating voltage VXRAY 2.7 3.0 3.3 V
POR circuit operating voltage VPOR 5.5 6.3 6.7 V
[Vertical Screen Size Adjustment]
Vertical ramp output amplitude @64 Vsize64 VSIZE : 1000000 1.44 1.74 2.04 Vp-p
[High Voltage Dependency Vertical Size Correction]
Vertical size correction @3 Vsizecomp VCOMP : 11 0.96 0.97 0.98 ratio
[Vertical Screen Position Adjustment]
Vertical ramp DC voltage @32 Vdc32 VDC : 1000000 3.686 3.876 4.484 Vdc
Vertical linearity @8 Vlin8 VLIN : 1000 0.93 0.985 1.04 ratio
Vertical S-curve correction @8 VScor8 VS : 1000 0.77 0.84 0.92 ratio
No. 5841-14/39
LA7615
Ratings
min typ max
[Horizontal Size Adjustment]
East/west DC voltage @16 EWdc16 EWDC : 10000 3.60 4.00 4.40 Vdc
[Pin cushion Distortion Correction]
East/west parabola amplitude @8 EWamp8 EWAMP : 1000 0.58 0.73 0.88 Vp-p
[Trapezoidal Distortion Correction]
East/west parabola tilt @8 EWtilt4 EWTILT : 1000 –0.14 0 +0.14 V
East/west parabola tilt @0 EWtilt0 EWTILT : 0000 –0.37 –0.23 –0.09 V
East/west parabola tilt @15 EWtilt7 EWTILT : 1111 0.09 0.23 0.37 V
[Corner Distortion Correction]
East/west parabola corner, top EWcorTOP CORTOP : 111-000 0.15 0.25 0.35 V
East/west parabola corner, bottom EWcorTOP CORBOTTOM : 111-000 0.15 0.25 0.35 V
[Sandcastle Output]
Burst gate pulse peak value VBGP 5.0 5.7 6.5 V
Burst gate pulse phase TdBGP 4.6 5.1 5.6 µs
Burst gate pulse width PWBGP 2.35 2.85 3.35 µs
Blanking pulse peak value VBLK 3.4 3.9 4.4 V
[D/A Converter Output]
Pin 30 D/A converter voltage @0 VDAC0 +B TRIM : 0000 2.75 3.00 3.25 V
Circuit Voltage and Current Test Conditions at Ta = 25°C, VCC = V2 = V17 = V32 = V60 = 7.6 V, ICC = I24 = 24 mA
Parameter Symbol Test point Input signal Test procedure Bus condition
[Circuit Voltage and Current]
Apply a 24-mA current to pin 24 and measure
Horizontal supply voltage HVCC 24 the voltage on pin 24 at that time. Initial
Apply 7.6 V to pin 2 and measure the DC

IF current drain (pin 2) I2 (IFICC) 2 No signal current (in mA) that flows into the IC. Initial
(With 5 V applied to the IF AGC)
Vertical current drain (pin 17) I17 (DEFICC) 17 current (in mA) that flows into the IC. Initial
Video, chrominance, current drain Apply 7.6 V to pin 32 and measure the DC
(pin 32) I32 (YCVCC) 32 current (in mA) that flows into the IC. Initial

FM power supply current (pin 60) I60 (FMVCC) 60 No signal
current (in mA) that flows into the IC. Initial
No. 5841-15/39
LA7615
VIF Block - Input Signals and Test Conditions

1. All input signals are input to VIF IN in the test circuit diagram.
2. The input signal voltages are all taken to be the voltage at VIF IN in the test circuit diagram.
3. The signals and their levels are as follows.
Input signal
Input signal Waveform Condition
SG1 45.75 MHz
CW
A10054
SG2 42.17 MHz
CW
A10055
SG3 41.25 MHz
CW
A10056
SG4 Variable frequency

CW
A10057
SG5 45.75 MHz

87.5% video modulation
10-step waveform
(subcarrier: 3.58 MHz)
A10058
SG6 45.75 MHz

40 IRE 87.5% video modulation
50 IRE Sweep signal
(APL: 50 IRE, sweep signal level: 40 IRE)
A10059
SG7 45.75 MHz

87.5% video modulation
100 IRE Flat field signal
A10060
4. Before testing, adjust the D/A converter in the order presented below.
Parameter Test point Input signal Adjustment
APC DAC 14 No signal, with pin 11 connected to ground Set the pin 14 DC voltage to be as close to 3.8 V as possible.
PLL DAC 14 SG1, 93 dBµ Set the pin 14 DC voltage to be as close to 3.8 V as possible.
Video level DAC 53 SG7, 93 dBµ Set the pin 53 output level to be 2.0 ±0.2 Vpp.
Lower the D/A converter from its maximum (15) and set the circuit so that the
Trap 53 SG6, 93 dBµ 4.5 MHz component is at least –32 dB below the 100 kHz component.
No. 5841-16/39
LA7615
(Test Conditions)
[VIF Block]
Connect the pin 11 to ground and measure the pin The adjusted values
No signal AFT output voltage V14 14 No signal
14 DC voltage. from item 4.
Connect the pin 11 to ground and measure the pin The adjusted values
No signal video output voltage V53 53 No signal
53 DC voltage. from item 4.
Monitor pin 53 with an oscilloscope, and modify SG4
to have a frequency higher than 45.75 MHz so that
the PLL goes to the unlocked state. (Beating should
appear at this point.) Gradually decrease the SG4
frequency until the PLL circuit locks, and measure
SG4 93 dBµ The adjusted values
APC pull-in range (U), (L) fPU, fPL 53 the lock frequency.
from item 4.
Also, and modify SG4 to have a frequency lower
than 45.75 MHz so that the PLL goes to the
unlocked state. Gradually increase the SG4
frequency until the PLL circuit locks, and measure
the lock frequency.
SG1 Set the RF AGC D/A converter to 0 and measure the The adjusted values
Maximum RF AGC voltage V4H 4 91 dBµ pin 4 DC voltage. from item 4.
SG1 Set the RF AGC D/A converter to 63 and measure The adjusted values
Minimum RF AGC voltage V4L 4 91 dBµ the pin 4 DC voltage. from item 4.
SG7 Monitor the pin 53 with an oscilloscope, and The adjusted values
Video output amplitude VO53 53 93 dBµ measure the peak-to-peak value of the waveform. from item 4.
Set the RF AGC D/A converter to 0 and determine
RF AGC Delay Pt The adjusted values
(@DAC = 0)
RFAGC0 4 SG1 the input level such that the pin 4 DC voltage
from item 4.
becomes 3.8 ±0.5 V.
Set the RF AGC D/A converter to 63 and determine
RF AGC Delay Pt The adjusted values
(@DAC = 63)
RFAGC63 4 SG1 the input level such that the pin 4 DC voltage
from item 4.
becomes 3.8 ±0.5 V.
Monitor the pin 53 with an oscilloscope, and
measure the peak-to-peak value of the waveform.
The adjusted values
Input sensitivity VIN 53 SG7 Gradually decrease the input level and determine the
from item 4.
input level such that the output goes down to a level
lower than the video amplitude (VO 53) by –3 dB.
Monitor the pin 53 with an oscilloscope, and
Video/Sync ratio SG7 measure the peak-to-peak values of the sync The adjusted values
(@100 dBµ)
V/S 53 100 dBµ waveform (Vs) and the luminance signal (Vy) to from item 4.
determine the ratio Vy/Vs.
SG5 The adjusted values
Differential gain DG 53 93 dBµ
Measure the pin 53 with a vectorscope.
from item 4.
Differential phase DP 53 93 dBµ
Measure the pin 53 with a vectorscope.
from item 4.
Pass the noise voltage signal generated at pin 53
SG1 through a 4 to 10 MHz bandpass filter and measure The adjusted values
Video signal-to-noise ratio S/N 53 93 dBµ that signal(Vsn) with an rms voltmeter. Determine the from item 4.
value of the formula 20log(1.43/Vsn).
Synchronizing signal tip level V53 TIP 53 93 dBµ
Measure the pin 53 DC voltage.
from item 4.
SG6 Measure the values of the 100 kHz and 4.5 MHz The adjusted values
4.5 MHz attenuation TRAP 53 93 dBµ components and determine their ratio. from item 4.
Input the 93 dBµ SG1 signal, and measure the pin
11 DC voltage (V11). Mix the three signals SG1 = 87
SG1 dBµ, SG2 = 82 dBµ, and SG3 = 63 dBµ, and input
The adjusted values
920 kHz beat level I920 53 SG2 that signal to VIF IN. Apply the voltage V11 to pin 11
from item 4.
SG3 using an external power supply. Measure the
difflerence of the 3.58 MHz and 920 kHz
components using a spectrum analyzer.
SG4
Maximum AFT output voltage V14H 14 93 dBµ Measure the pin 14 DC voltage.
44.75 MHz
SG4
Minimum AFT output voltage V14L 14 93 dBµ Measure the pin 14 DC voltage.
46.75 MHz
Gradually change the SG4 frequency and
SG4 determined the frequency change ∆f required to
AFT detection sensitivity Sf 14 93 dBµ change the pin 14 DC voltage from 2.5 V to 5.0 V.
Sf = 2500/∆f [mV/kHz]
No. 5841-17/39
LA7615
First SIF Block - Input Signals and Test Conditions

For each of the test items, set up the following conditions unless otherwise specified.
1. PIF.IN: 45.75 MHz, 93 dBµ, CW
2. Bus control conditions: Set the following 4 items to their adjusted values.
(See the VIF block test description for details on the adjustment procedure.)
• APC DET.ADJ
• PLL tuning
• 4.5 MHz trap
• Video level
3. Apply the input signal to the pin 12, using a signal with a frequency of 41.25 MHz CW.
Measure the pin 59 output 4.5 MHz component (mV
rms). Let SV1 be this measured value and perform
4.5 MHz conversion gain SCG 59 60 dBµ
the following calculation.
SCG = 20 × log(SV1 × 1000) – 60 [dB]
4.5 MHz output level SVO 59 88 dBµ
SCO = 20 × log(SV2 × 1000) [dB]
First SIF maximum input SVM 59 96 dBµ
SCM = 20 × log(SV3/SV1) [dB]
SIF Block - Input Signals and Test Conditions

1. Connect pin 13 (SIF AGC) to ground.
2. Bus control conditions: IF.AGC.SW = 1.
3. SW:IF1 = off
4. Apply the input signal to pin 61. The carrier frequency should be 4.5 MHz.
Adjust the D/A converter (FM.LEVEL) so that the pin
90 dBµ, 5 FM detector output 1 kHz component is as close to
FM detector output voltage SOADJ 5 fm = 1 kHz, 424 mV rms as possible. Measure the output (mV
FM = ±25 kHz rms) at that time.
Let SV1 be the measured value at this time.
Determine the input level (dBµ) such that the pin 5
fm = 1 kHz, FM.LEVEL =
FM limiting sensitivity SLS 5 FM = ±25 kHz
FM detector output 1 kHz component is down –3 dB
adjusted value.
from SV1.
Determine the modulation frequency bandwidth (Hz)
90 dBµ, FM.LEVEL =
FM detector output bandwidth SF 5 FM ±25 kHz
for a –3 dB drop in the pin 5 FM detector output
adjusted value.
1 kHz component with respect to SV1.
90 dBµ, Determine the distortion in the pin 5 FM detector
FM.LEVEL =
FM detector output distortion STHD 5 fm = 1 kHz, output 1 kHz component.
adjusted value.
FM ±25 kHz
Measure (in mV rms) the pin 5 FM detector output
90 dBµ, 1 kHz component.
FM.LEVEL =
AM rejection ratio SAMR 5 fm = 1 kHz, Let SV2 be the measured value at this time and
adjusted value.
AM = 30% perform the following calculation.
SAMR = 20 × log(SV1/SV2) [dB]
Set the SW:IF1 switch to the on state.
Measure the noise level (mV rms) on pin 5.
FM.LEVEL =
SIF signal-to-noise ratio SSN 5 90 dBµ, CW Let SV3 be the measured value at this time and
adjusted value.
perform the following calculation.
SSN = 20 × log(SV1/SV3) [dB]
No. 5841-18/39
LA7615
Video Block - Input Signals and Test Conditions

[Input Signals]
<CIN input signal>
*: chrominance burst signal: 40 IRE
<YIN input signal>
0 IRE signal (L-0): NTSC standard synchronizing signal
[ 100 IRE : 714 mV ]
Pedestal level
H SYNC
4.7 µs (H/V SYNC : 40 IRE : 286 mV)
A10061
X IRE signal (L-X)
X IRE (X = 0 to 100)
0 IRE
A10062
CW signal (L-CW)
20 IRE CW signal
50 IRE
A10063
Black stretch 0 IRE signal (L-BK)
50 µs
100 IRE
5 µs
(Point A)
A10064
<R/G/B IN input signal>

RGB input signal 1 (O-1)
20 µs each
0.7 V
0.35 V
B
A A10065
0.0 VDC
RGB input signal 2 (O-2)
20 µs 30 µs 1.0 VDC
A10066
0.0 VDC
No. 5841-19/39
LA7615
(Test Conditions)
Parameter Symbol Test point Input signal Test procedure Bus bits/input signal
[Video Block]
Overall video gain (at maximum Measure the output signal 50 IRE amplitude (CNTHB TR24: Contrast
CONT63 38 L-50
contrast) Vp-p) and calculate CONT63 = 20log(CNTHB/0.357). 111111
Contrast adjustment Measure the output signal 50 IRE amplitude (CNTCB

characteristics (normal/max)
CONT32 38 L-50
Vp-p) and calculate CONT32 = 20log(CNTCB/0.357).
Contrast adjustment Measure the output signal 50 IRE amplitude (CNTLB TR24: Contrast
characteristics (normal/max)
CONT0 38 L-50
Vp-p) and calculate CONT0 = 20log(CNTLB/0.357). 000000
With the input signal CW = 100 kHz, measure the

Video frequency characteristics
Yf03 L-CW amplitude of the CW signal in the output signal TR26: F0 Adjust 01
f0 = 1 (sharp 0)
(PEAKDC Vp-p).
38 With the input signal CW = 10 MHz, measure the TR26: F0 Adjust 11
amplitude of the CW signal in the output signal TR25: Sharpness
f0 = 3 (sharp 15)
(F03 Vp-p). 01111
Calculate Yf3 = 20log(F03/PEAKDC).
With the input signal CW = 3.58 MHz, measure the
Chrominance trap level amplitude of the CW signal in the output signal TR26: F0 Adjust 00
f0 = 0 (sharp 0)
Ctrap 38 L-CW
(F00 Vpp).
Calculate Ctrap = 20·log(F00/PEAKDC).
TR23: Brightness
Measure the output signal 0 IRE DC level 000000
L-0
(BRTPL (V)). TR24: Contrast
111111
DC restoration ClampG 38
Measure the output signal 0 IRE DC level (DRVPH TR23: Brightness
(V)) and the 100 IRE amplitude (DRVH Vpp). 000000
L-100
Calculate TR24: Contrast
ClampG = 100 × (1 + (DRVPH – BRTPL)/DRVH)). 111111
Measure the time difference (amount of delay)
between the rise of the input signal 50 IRE
Luminance delay f0 = 1 YDLY 38 L-50
amplitude, and rise of the output signal 50 IRE
amplitude.
Measure the 0 IRE DC level at point A in the output
TR31: BKST Defeat
signal when the black stretch function is defeated
1
(black stretch off). (BKST1 (V))
Measure the 0 IRE DC level at point A in the output
Maximum black stretch gain BKSTmax 38 L-BK
signal when the black stretch function is on.
TR31: BKST Defeat
0
(BKST2 (V))
Calculate
BKSTmax = 2 × 50 × (BKST1 – BKST2)/CNTHB.
Measure the 40 IRE DC level in the output signal TR31: BKST Defeat
when the black stretch function is on. (BKST3 (V)) 0
Measure the 40 IRE DC level in the output signal
Black stretch threshold when the black stretch function is defeated TR31: BKST Defeat
BKSTTH∆ 38 L-40
1
∆black(40 IRE ∆black) (black stretch off). (BKST4 (V))
Calculate
BKSTTH∆ = 50 × (BKST4 – BKST3)/CNTHB.
With the input signal CW = 2.2 MHz, measure the TR26: F0 Adjust 00
Sharpness (peaking) variability amplitude of the CW signal in the output signal TR25: Sharpness
characteristics Sharp16 L-CW (F00S16 Vp-p). 10000
(normal)
Calculate Sharp16 = 20log(F00S16/PEAKDC).

(maximum) Sharp31 L-CW 11111
(F00S31 Vp-p).
38
(minimum) Sharp0 L-CW 00000
(F00S0 Vp-p).
Horizontal/vertical blanking Measure the DC level of the output signal during the
output level
RGBBLK 38 L-100
blanking period (RGBBLK (V)).
No. 5841-20/39
LA7615
[OSD Block]
Gradually increase the pin 39 voltage starting at 1.5
L-0 Pin 42: Apply signal
OSD fast switching threshold FSTH 38 O-2
V, and determine the pin 39 voltage at the point
O-2.
where the output signal switches to the OSD signal.
Measure the 50 IRE amplitude in the output signal.
L-50
(CNTCR Vp-p).
RGB red output level ROSDH 36 L-0 Pin 39: Apply 3.5 V.
Measure the OSD output amplitude (OSDHR Vp-p).
O-2 Pin 40: Apply signal O-2.
Calculate ROSDH = 50 × (OSDHR/CNTCR).
L-50
(CNTCG Vp-p).
RGB green output level GOSDH 37 L-0
Measure the OSD output amplitude (OSDHG Vpp).
Pin 39: Apply 3.5 V.
Calculate GOSDH = 50 × (OSDHG/CNTCG).
L-50
(CNTCB Vp-p).
BOSDH
RGB blue output level 38 L-0
Measure the OSD output amplitude (OSDHB Vp-p).
Pin 39: Apply 3.5 V.
Calculate BOSDH = 50 × (OSDHB/CNTCB).
Measure the amplitudes at point A (the 0.35 V
component of the input signal O-1) and point B (the Pin 39: Apply 3.5 V.
L-0
Analog OSD red output level 36 O-1
0.7 V component of the input signal O-1) in the Pin 40: Apply signal
output signal and record these as RGBLR and O-1.
RGBHR (Vp-p) respectively.
Gain matching RRGB Calculate RRGB = RGBLR/CNTCR.
Linearity LRRGB Calculate LRRGB = 100 × (RGBLR/RGBHR).
L-0
Analog OSD green output level 37 0.7 V component of the input signal O-1) in the Pin 34: Apply signal
O-1
output signal and record these as RGBLG and O-1.
RGBHG (Vp-p) respectively.
Gain matching GRGB Calculate GRGB = RGBLG/CNTCG.
Linearity LGRGB Calculate LGRGB = 100 × (RGBLG/RGBHG).
L-0
Analog OSD blue output level 38 O-1
0.7 V component of the input signal O-1) in the Pin 41: Apply signal
output signal and record these as RGBLB and O-1.
RGBHB (Vp-p) respectively.
Gain matching BRGB Calculate BRGB = RGBLB/CNTCB.
Linearity LBRGB Calculate LBRGB = 100 × (RGBLB/RGBHB).
[RGB Output Block]
(Cutoff and Drive Blocks)
L-0 Measure the output signal 0 IRE DC levels of the R
Brightness control 36 output (pin 36), G output (pin 37), and B output (pin TR24: Contrast
(normal) BRT32 38) and record these as BRTPCR, BRTPCG, and 111111
37 BRTPCB (V), respectively.
Calculate
38
BRT63 = (BRTPCR + BRTPCG + BRTPCB)/3.
Measure the output signal 0 IRE DC level of the B TR23: Brightness
output (pin 38) (BRTPHB). 111111
(maximum) BRT63
Calculate
BRT63 = 50 × (BRTPHB – BRTPCB) / CNTHB.
38 Measure the output signal 0 IRE DC level of the B TR23: Brightness
output (pin 38) (BRTPLB). 000000
(minimum) BRT0
Calculate
BRT0 = 50 × (BRTPLB – BRTPCB) / CNTHB.
No. 5841-21/39
LA7615
[RGB Output Block]
(Cutoff and Drive Blocks)
Bias (cutoff) control Measure the output signal 0 IRE DC levels of the R TR24: CONTRAST
output (pin 36), G output (pin 37), and B output (pin 111111
(minimum) Vbias0 L-50
38) and record these as Vbias0* (V), where * : R, G, TR22: SUB-BIAS
and B, respectively. R, G, B 000000
TR16: R BIAS
111111
TR: G BIAS
Measure the output signal 0 IRE DC levels of the R 111111
(maximum) Vbias128 output (pin 36), G output (pin 37), and B output (pin TR18: B BIAS
38) and record these as Vbias128* (V), where * : R, 111111
G, and B, respectively. TR24: CONTRAST
111111
TR22: SUB-BIAS
R, G, B 111111
TR16: R BIAS
36 1010000
Measure the output signal 0 IRE DC levels of the R TR17: G BIAS
37 38) and record these as BAS80* (V), where * : R, G, TR18: B BIAS
and B, respectively. 1010000
38 TR24: CONTRAST
111111
Bias (cutoff) control resolution Vbiassns TR16: R BIAS
0110000
Measure the output signal 0 IRE DC levels of the R TR17: G BIAS
38) and record these as BAS48* (V), where * : R, G, TR18: B BIAS
and B, respectively. 0110000
TR24: CONTRAST
11111
Vbiassns * = (BAS80 * – BAS48 *)/32
Measure the output signal 0 IRE DC levels of the R TR22: SUB-BIAS
output (pin 36), G output (pin 37), and B output (pin R, G, B 101010
Sub-bias control resolution Vsbiassns L-50 38) and record these as SBTPM* (V), where * : R,
G, and B, respectively.
Vsbiassns * = (BRTPC * – SBTPM *)
Measure the output signal 100 IRE DC amplitudes of TR24: CONTRAST
Maximum drive adjustment the R output (pin 36), G output (pin 37), and B output 111111
RGBout63
output (pin 38) and record these as DRVH* (Vpp), where * : TR23: Brightness
R, G, and B, respectively. 000000
TR24: CONTRAST
36 111111
TR23: Brightness
L-100
37 Measure the output signal 100 IRE DC amplitudes of 000000
the R output (pin 36), G output (pin 37), and B output TR19: R DRIVE
Output attenuation RGBout0 (pin 38) and record these as DRVL* (Vpp), where * : 000000
38 R, G, and B, respectively. TR20: G DRIVE
000000
TR21: B DRIVE
000000
RGBout0 * = 20 log(DRVH */DRVL *)
No. 5841-22/39
LA7615
Chrominance Block - Input Signals and Test Conditions

1. VIF and SIF blocks: No signal
2. Deflection block: Input a horizontal/vertical composite sync signal and verify that the deflection block is locked on
the synchronizing signal. (See the section on input signals and test conditions for the deflection block.)
3. Bus control conditions: All conditions set to their initial values, unless otherwise specified.
4. Connect a crystal oscillator circuit to pin 16. Adjust the impedance (Z) of the series capacitance and resistance as
shown below.
Z = 0 deg @ 3.579545 MHz ±10 Hz
–40 ±1 deg @3.579345 MHz
5. Luminance (Y) input: No signal
6. Chrominance (C) input: Input the signal to the C1IN pin (pin 51).
7. The method for calculating the demodulation angle is shown below.
B-Y axis angle = tan – 1 (B(0)/B(270)) + 270°
R-Y axis angle = tan – 1 (R(180)/R(90)) + 90°
G-Y axis angle = tan – 1 (G(270)/G(180)) + 180°
R-Y axis 90°
R (90)
R (180)
B (270)
180° 0°
B (0) B-Y axis

G (180)
G (270)
270°
G-Y axis
A10067
8. The method for calculating the AF angle is shown below.

BR · · · · The B-Y/R-Y demodulation output ratio
θ · · · · · · ANGBR: the B-Y/R-Y demodulation angle
R – Y/B – Y × BR – Cosθ
AFXXX = tan – 1 ———————————
Sinθ
No. 5841-23/39
LA7615
[Input Signal]
C-1 40 IRE
Burst 0° 90° 180° 270°

3.58 MHz
A10068
77IRE
X IRE signal (L-X)

0 IRE
A10069
40IRE 62.5IRE
C-2
Burst 3.58 MHz 364°

A10070
C-3 40 IRE
Burst 3.48 MHz (However, when a frequency is specified, that frequency is to be used.)
CW
A10071
C-4 40 IRE
28° 73° 118° 163°
A10072
35 µs
C-5
Burst 3.48 MHz

Chroma A10073
No. 5841-24/39
LA7615
(Test Conditions)
[Chrominance Block]
Bout Measure the output amplitude when the
C-1 chrominance input is set to 0 dB and the output
ACC amplitude characteristics 1 ACCM1 38 0 dB amplitude when the input is reduced by – 6 dB, and
+6 dB calculate the ratio.
ACCM1 = 20log(+6 dB data/0 dB data)
Bout Measure the output amplitude when the
C-1 chrominance input is set to –14 dB and calculate the
ACC amplitude characteristics 2 ACCM2 38 –14 dB ratio.
ACCM2 = 20log(–14 dB data/0 dB data)
YIN: L77
Measure the luminance (Y) output level(V1).
C-1: No signal
Next, apply a signal to the CIN input (with only a sync
B-Y/Y amplitude ratio CLRBY 38 applied to the Y input) and measure the output level
C-2
(V2). Calculate the following formula.
CLRBY = 100 × (V2/V1) +15%
Measure V1: the output amplitude when the color TR28: Color Control
control is maximum, and V2: the output amplitude 1111111
Color control characteristics 1 CLRMN 38 C-3
when the color control is normal (Color control:
1000000) and calculate CLRMN = V1/V2. 1000000
Color control characteristics 2 CLRMM 38 C-3 control is minimum and calculate CLRMM = 0000000
20·log(V1/V3).
control is 90, and V5: the output amplitude when the 1011010
Color control sensitivity CLRSE 38 C-3
color control is 38. Calculate the following formula. Color Ctontrol
CLRSE = 100 × (V4 – V5) / (V2 × 52) 0100110
Measure each section of the output waveform and TR27: TINT
Tint center TINCEN 38 C-1
calculate the angle of the B-Y axis. 0111111
Measure each section of the output waveform and
calculate the angle of the B-Y axis. Calculate the TR27: TINT
Tint control (max) TINMAX 38 C-1
following formula. 1111111
TINMAX = (the B-Y axis angle) – TINCEN
Measure each section of the output waveform and
calculate the angle of the B-Y axis. Calculate the TR27: TINT
Tint control (min) TINMIN 38 C-1
following formula. 0000000
TINMIN = (the B-Y axis angle) – TINCEN
Measure A1: the angle when the tint control is 85,
TR27: TINT
and A2: the angle when the tint control is 42.
Tint control sensitivity TINSE 38 C-1
Calculate the following formula.
1010101
0101010
TINSE = (A1 – A2)/43
Demodulation output ratio 38 Measure Vb: the BOUT output amplitude and Vr: the TR28: Color Control
BR C-3
B-Y/R-Y ROUT output amplitude, and calculate BR = Vb/Vr. 1000000
36
Demodulation output ratio Measure Vg: the GOUT output amplitude and TR28: Color Control
G-Y/R-Y
GR 37 C-3
calculate GR = Vg/Vr. 1000000
No. 5841-25/39
LA7615
38 Measure the BOUT and ROUT output levels and calculate

Demodulation angle B-Y/R-Y ANGBR C-1 the angle between the B-Y and R-Y axes. Calculate
36 ANGBR = (R-Y angle) – (B-Y angle).
Measure the GOUT output level and calculate the angle

Demodulation angle G-Y/R-Y ANGGR 37 C-1 between the G-Y and R-Y axes. Calculate ANGGR = (R-Y
angle) – (G-Y angle).
Gradually decrease the amplitude of the input signal and

Killer operating point KILL 38 C-3 measure the input level when the output level falls less
than 150 mVpp.
Chrominance VCO free-running CIN Measure the oscillator frequency f and calculate the
frequency
CVCOF 16 No signal following formula. CVCOF = f – 3579545 (Hz)
Gradually decrease the input signal subcarrier frequency
Chrominance pull-in range (+) PULIN+ 38 C-1 starting at 3.579545 MHz + 1000 Hz, and measure
frequency at the point the output waveform locks.
Gradually raise the input signal subcarrier frequency
Chrominance pull-in range (–) PULIN– 38 C-1 starting at 3.579545 MHz – 1000 Hz, and measure
frequency at the point the output waveform locks.
With Auto Flesh = 0, measure the level that corresponds
to a BOUT and ROUT output waveform of 73° and calculate
38 the angle AF073A.
TR26: Auto Flesh :
**** 0 **
Auto Flesh characteristics 73° AF073 C-4 With Auto Flesh = 1, measure the angle AF073B in the
TR26: Auto Flesh :
36 same manner.
**** 1 **
AF073 = AF073B – AF073A
to a BOUT and ROUT output waveform of 118° and
TR26: Auto Flesh :
38 calculate the angle AF118A.
**** 0 **
TR26: Auto Flesh :
36 same manner.
**** 1 **
AF118 = AF118B – AF118A
to a BOUT and ROUT output waveform of 163° and
38 TR26: Auto Flesh :
calculate the angle AF163A.
**** 0 **
TR26: Auto Flesh :
36 same manner.
**** 1 **
AF163 = AF163B – AF163A
Measure V1: the output amplitude when the input signal
burst level is set to 40 IRE and the chrominance level is
set to 8 IRE, and V2: the output amplitude when the input TR26: OverLoad :
Overload characteristics 1 OVL1 36 C-5 signal burst level is set to 40 IRE and the chrominance ****** 1
level is set to 40 IRE.
OVL1 = V2/V1
No. 5841-26/39
LA7615
Measure V3: the output amplitude when the input
signal burst level is set to 40 IRE and the
Overload characteristics 2 OVL2 36 C-5 chrominance level is set to 80 IRE. TR26: Overload
Calculate the following formula. ******1
OVL2 = V3/V1
signal burst level is set to 20 IRE and the
Overload characteristics 3 OVL3 36 C-5 chrominance level is set to 80 IRE. TR26: Overload
Calculate the following formula. ******1
OVL3 = V4/V1
[Chrominance Bandpass Filter Characteristics]
Measure V0: the output amplitude.
Next, set the input chrominance signal (CW)
Peaking amplitude frequency to 3.08 MHz and measure V1: the output TR26: CHR.BPF:
characteristics: 3.08 MHz
CPE308 38 C-3
amplitude. ***1***
CPE308 = 20log(V1/V0)
chrominance signal (CW) frequency is 3.28 MHz,
Peaking amplitude and V3: the output amplitude when the input TR26: CHR.BPF:
characteristics: 3.88/3.28 MHz
CPE 38 C-3
chrominance signal (CW) frequency is 3.88 MHz. ***1***
CPE = 20log(V3/V2)
Peaking amplitude chrominance signal (CW) frequency is 4.08 MHz. TR26: CHR.BPF:
CPE05 38 C-3
Calculate the following formula. ***1***
CPE05 = 20log(V4/V1)
Measure V5: the output amplitude.
Next, measure V6: the output amplitude when the
Bandpass amplitude input chrominance signal (CW) frequency is set to TR26: CHR.BPF:
characteristics: 3.08 MHz
CBE308 38 C-3
3.08 MHz. ***0***
CPE308 = 20log(V6/V5)
chrominance signal (CW) frequency is 3.28 MHz,
Bandpass amplitude and V8: the output amplitude when the input TR26: CHR.BPF:
CBE 38 C-3
chrominance signal (CW) frequency is 3.88 MHz. ***0***
CPE = 20log(V8/V7)
chrominance signal (CW) frequency is set to 4.08
Bandpass amplitude TR26: CHR.BPF:
CBE05 38 C-3 MHz.
characteristics: 4.08/3.08 MHz ***0***
CPE05 = 20log(V9/V6)
No. 5841-27/39
LA7615
Deflection Block - Input Signals and Test Conditions

1. VIF and SIF blocks: No signal
2. Luminance (Y) input and chrominance (C) input: No signal
3. Sync input: Horizontal/vertical composite sync signal (DC offset: 3.8 V, 40 IRE. Other timing and other parameters
must conform to the FCC broadcast standards.)
Caution: There must be no burst or chrominance signal under the pedestal level.
Signal inappropriate for use as a sync input Signal appropriate for use as a sync input
Chrominance signal
Burst signal
A10074
4. Bus control conditions: All conditions set to their initial values, unless otherwise specified.
5. The delay time from the rise of the horizontal output (the pin 26 output) to the rise of the F.B.P IN (pin 27 input)
must be 9 µs.
6. The pin 18 (the vertical size correction circuit input pin) voltage must be VCC (7.6 V).
7. Pin 28 (the x-ray protection circuit input pin) must be connected to ground.
Notes:
Perform the following operations if the horizontal output pulse signal was stopped.
1. Set the bus on/off bit to off (0) temporarily, and then set it to on (1) again.
(If the x-ray protection circuit and/or the PON-RES circuit operate, an IC internal latch circuit will be set. The on/off
bit must be set to off (0) to reset that latch circuit, even if the horizontal output signal is not output. Since the PON-
RES circuit operates when the horizontal supply voltage rises, the on/off bit must be set to off (0).)
2. Note on video muting

If the horizontal output pulse signal was stopped, after performing the operation described in paragraph 1 above, clear
the video muting bit to 0.
(This is because the video muting bit is forcibly set to 1 when the on/off bit is set to 0 or when either the x-ray
protection circuit or the PON-RES circuit operate. This also applies at power on.)
No. 5841-28/39
LA7615
[Deflection Block]
SYNC IN:
Gradually decrease the level of the synchronizing
horizontal and
signal input to SYNC IN (pin 44) and measure the
Sync separator circuit sensitivity Ssync 44 vertical
level of the synchronizing signal when the
synchronizing
synchronization is unlocked.
signal
Connect the pin 26 output (Hout) to a frequency
counter and measure the horizontal free-running
Horizontal free-running SYNC IN: no
∆fH 26 frequency.
frequency deviation signal
∆fH = <measured value> – 15.743 kHz
SYNC IN:
Monitor the horizontal synchronizing signal input to
horizontal and
SYNC IN (pin 44) and the pin 26 output (Hout) with
Horizontal pull-in range fH PULL 44 vertical
an oscilloscope. Vary the frequency of the horizontal
synchronizing
synchronizing signal and measure the pull-in range.
signal
SYNC IN:
horizontal and
Measure the low-level period in the pin 26 horizontal
Horizontal output pulse width @0 Hduty 0 26 vertical
pulse waveform.
HDUTY: 00
synchronizing
signal
SYNC IN:
horizontal and
pulse waveform.
HDUTY: 01
synchronizing
signal
SYNC IN:
horizontal and
pulse waveform.
synchronizing
signal
SYNC IN:
horizontal and
pulse waveform.
HDUTY: 11
synchronizing
signal
SYNC IN:
horizontal and
Horizontal output pulse Measure the voltage during low-level period in the
saturation voltage
VHsat 26 vertical
pin 26 horizontal pulse waveform.
synchronizing
signal
Measure the delay time from the rise of the pin 26
horizontal output pulse waveform to the fall of the
SYNC IN horizontal synchronizing signal.
HPHCEN
SYNC IN:
26 horizontal and
Horizontal output pulse phase HPHCEN vertical
synchronizing
44 signal
20 IRE
Horizontal output 3.8V
A10075
No. 5841-29/39
LA7615
horizontal output pulse to the fall of SYNC IN
horizontal synchronizing signal with HPHASE set to
both 0 and 15 and calculate the difference with
respect to HPHCEN.
Measurement
SYNC IN:
Horizontal position adjustment
26 horizontal and
HPHASE: 0000
HPHrange vertical
range HPHASE: 1111
44 synchronizing 20 IRE
signal
Horizontal output 3.8V
A10076

horizontal output pulse to the fall of SYNC IN
horizontal synchronizing signal while varying HPHASE
from 0 to 15, and measure the amount of variation at
each step. Find the step with the largest value of the
data.
SYNC IN: Measurement

HPHASE: 0000
26 horizontal and
Maximum horizontal position to
HPHstep vertical
adjustment variability HPHASE: 1111
synchronizing
44 signal 20 IRE
Horizontal output
A10077
SYNC IN:
Connect a DC voltage source to pin 28, and
26 horizontal and
X-ray protection circuit operating gradually increase that voltage starting at 0 V.
VXRAY vertical
voltage Measure the pin 28 DC voltage at the point the pin
28 synchronizing
26 horizontal output pulse stops.
signal
SYNC IN: Replace the current source connected to pin 24 with
24 horizontal and a DC voltage source, and gradually decrease the
POR circuit operating voltage VPOR vertical voltage starting at 7.3 V. Measure the pin 24 DC
26 synchronizing voltage at the point the pin 26 horizontal output pulse
signal stops.
[Vertical Screen Size Adjustment]
Monitor the pin 19 vertical ramp output and measure
the voltages at the 22nd line and at the 262nd line.
SYNC IN: Vsize64 = Vline262 – Vline22
horizontal and
Vertical ramp output amplitude Vsize64 19 vertical Vertical ramp output
@64 synchronizing
signal 262nd line
22nd line A10078
No. 5841-30/39
LA7615
Vsize0 = Vline262 – Vline22
SYNC IN:
horizontal and Vertical ramp output
Vertical ramp output amplitude Vsize0 19 vertical VSIZE: 0000000
@0 synchronizing
signal 262nd line
22nd line A10079

Vsize0 = Vline262 – Vline22
SYNC IN:
Vertical ramp output amplitude Vsize127 19 vertical VSIZE: 1111111
@127 synchronizing
262nd line
signal
22nd line A10080
[High-Voltage Dependency Vertical Size Correction]

Calculate Va from the following formula.
SYNC IN: Va = Vline262 – Vline22
horizontal and Next, apply 3.8 V to pin 18, and once again measure
Vertical size correction @7
(maximum)
Vsizecomp 19 vertical the voltages at the 22nd line and at the 262nd line. VCOMP: 111
synchronizing Calculate Vb from the following formula.
signal Vb = Vline262 – Vline22
Finally, calculate Vsizecomp from the following
formula.
Vsizecomp = (Va – Vb)/Va × 100
[Vertical Screen Position Adjustment]
the voltage at the 142nd line.
SYNC IN: Vertical ramp output

horizontal and
Vertical ramp DC voltage @32 Vdc32 19 vertical
synchronizing
signal
142nd line
A10081

SYNC IN:
Vertical ramp DC voltage @0 Vdc0 19 vertical VDC: 000000
synchronizing
signal
142nd line
A10082
No. 5841-31/39
LA7615
SYNC IN:
Vertical ramp output
horizontal and
Vertical ramp DC voltage @63 Vdc63 19 vertical VDC: 111111
synchronizing
signal
142nd line
A10083

the voltages at the 22nd line, the 142nd line, and the
262nd line. Let Va, Vb, and Vc be these
measurements, and calculate the following formula.
Vline8 = (Vb – Va)/(Vc – Va)
SYNC IN:
horizontal and 262nd line
Vertical linearity @8 Vlin8 19 vertical Vertical ramp output
synchronizing
signal
142nd line
A10084
22nd line

Vline0 = (Vb – Va)/(Vc – Va)
SYNC IN:
horizontal and 262nd line
Vertical linearity @0 Vlin0 19 vertical Vertical ramp output VLIN: 0000
synchronizing
signal
142nd line
A10085
22nd line

SYNC IN: Vline15 = (Vb – Va)/(Vc – Va)
horizontal and
262nd line
vertical
Vertical linearity @15 Vlin15 19 synchronizing
Vertical ramp output VLIN: 1111
signal
142nd line
22nd line A10086
No. 5841-32/39
LA7615
the voltages at the 32nd line, the 52nd line, the
132nd line, the 152nd line, the 232nd line, and the
252nd line. Let Va, Vb, Vc, Vd, Ve, and Vf be these
VScor8 = 0.5[(Vb – Va) + (Vf – Ve)] / (Vd – Vc)
SYNC IN:
horizontal and Vertical ramp output 252nd line
Vertical S-curve correction @8 VScor8 19 vertical 232nd line VS: 1000
synchronizing 152nd line
signal
132nd line
52nd line
32nd line A10087

VScor0 = 0.5[(Vb – Va) + (Vf – Ve)] / (Vd – Vc)
SYNC IN:
horizontal and Vertical ramp output 252nd line
Vertical S-curve correction @0 VScor0 19 vertical 232nd line
signal
132nd line
52nd line
32nd line A10088
Monitor the pin 19 vertical ramp output and measure VS: 1111
SYNC IN: measurements, and calculate the following formula.
horizontal and VScor15 = 0.5[(Vb – Va) + (Vf – Ve)] / (Vd – Vc)
Vertical S-curve correction @15 VScor15 19 vertical
synchronizing Vertical ramp output 252nd line
signal 232nd line
152nd line
132nd line
52nd line
32nd line A10089
No. 5841-33/39
LA7615
[Horizontal Size Adjustment]
Monitor the pin 21 east/west output (parabola
waveform output) and measure the voltage at the
142nd line.
SYNC IN: East/west output 142nd line

horizontal and
East/west DC voltage @16 EWdc16 21 vertical
synchronizing
signal
A10090

142nd line.
SYNC IN:
East/west output 142nd line
horizontal and
East/west DC voltage @0 EWdc0 21 vertical EWDC: 00000
synchronizing
signal
A10091

142nd line.
SYNC IN:
East/west output 142nd line
horizontal and
East/west DC voltage @31 EWdc31 21 vertical EWDC: 11111
synchronizing
signal
A10092
[Pin-Cushion Distortion Correction]

waveform output) and measure the voltages at the
22nd line and at the 142nd line. Let Va and Vb be
these measurements, and calculate the following
formula.
SYNC IN:
EWamp8 = Vb – Va
horizontal and
East/west parabola amplitude EWamp8 21 vertical
East/west output
@8 synchronizing 142nd line
signal
22nd line
A10093

formula.
SYNC IN:
EWamp0 = Vb – Va
horizontal and
East/west parabola amplitude EWamp0 21 vertical
East/west output
EWAMP: 0000
@0 synchronizing 142nd line
signal
22nd line
A10094
No. 5841-34/39
LA7615
formula.
SYNC IN: EWamp15 = Vb – Va
horizontal and
East/west parabola amplitude
@15
EWamp15 21 vertical East/west output EWAMP: 1111
signal
22nd line
A10095
[Trapezoidal Distortion Correction]

formula.
SYNC IN: EWamp8 = Va – Vb
horizontal and
East/west parabola tilt @8 EWtilt8 21 vertical East/west output
signal
22nd line
A10096

formula.
SYNC IN: EWtilt0 = Va – Vb
horizontal and
East/west parabola tilt @0 EWtilt0 21 vertical East/west output EWTILT: 0000
signal
22nd line
A10097

formula.
SYNC IN: EWtilt15 = Va – Vb
horizontal and
East/west parabola tilt @15 EWtilt15 21 vertical East/west output EWTILT: 1111
signal
22nd line
A10098
No. 5841-35/39
LA7615
[Corner Distortion Correction]
22nd line under the conditions with CORTOP set to
111 and to 000. Let Va and Vb be these
measurements. Calculate the following formula.
SYNC IN: EWcortop = Va – Vb
horizontal and
East/west parabola corner: Top EWcortop 21 vertical East/west output CORTOP: 111-000
synchronizing
signal
22nd line
A10099

262nd line under the conditions with CORBOT set to
111 and to 000. Let Va and Vb be these
measurements. Calculate the following formula.
SYNC IN: EWcorbot = Va – Vb
horizontal and
East/west parabola corner: CORBOTTOM:
Bottom
EWcorbot 21 vertical East/west output
111-000
synchronizing
signal
262nd line
A10100
[Sandcastle Output]
Measure the pin 29 output burst gate pulse peak
value.
SYNC IN: Pin 29 output

horizontal and VBGP
Burst gate pulse peak value VBGP 29 vertical BGP
synchronizing
signal
A10101
Measure the delay time from the rise of the

horizontal synchronizing signal to the rise of the pin
29 burst gate pulse.
SYNC IN: Horizontal synchronizing signal
29 horizontal and
Burst gate pulse phase TdBGP vertical
synchronizing
44 signal
TdBGP
Pin 29 output BGP
A10102
Measure the width of the pin 29 burst gate pulse.
SYNC IN: Pin 29 output

horizontal and PWBGP
Burst gate pulse width PWBGP 29 vertical BGP
synchronizing
signal
A10103
No. 5841-36/39
LA7615
Measure the peak value of the pin 29 output
blanking pulse.
SYNC IN:
Pin 29 output
horizontal and
Blanking pulse peak value VBLK 29 vertical
synchronizing
signal
VBLK Blanking pulse
A10104
[D/A Converter Output]

Pin 30 D/A converter output Measure the pin 30 D/A converter output DC
voltage @0
VDAC0 30 voltage.
+BTRIM: 0000
voltage @8
VDAC8 30 voltage.
voltage @15
VDAC15 30 voltage.
+BTRIM: 1111
No. 5841-37/39
61 60 59 56 55 54 53 51 50 48 47 46 44 42 41 40 39 38 37 36
R69
R68
100 Ω
100 Ω
+
R53
R52
R51
R49
75 Ω
75 Ω
75 Ω
75 Ω
1 µF
C55
R74
0.01 µF
R65
R64
R70
R61
R59
75 Ω
75 Ω
75 Ω
75 Ω
24 kΩ
R56
C53
560 Ω
C58 50 Ω
0.01 µF C56
100 pF
Test Circuit Diagram
L102
R57
470 kΩ
R63
R60
M C52 +7.6 V
100 Ω
100 Ω
R50
+7.6 V
1100 Ω
1 µF
C43
+ +7.6 V
100 pF +
1 µF
C59
R58
+ +
C51
+
10 µF
47 pF
R62
15 kΩ
C50
C44
1 µF
1 µF
1 µF
R48
R47
R46
C48
C41
C40
C39
C37
C36
C45
1 µF
C49
1 µF
10 kΩ
16 kΩ
16 kΩ
16 kΩ
100 pF
1.5 µF
+ + + +
0.01 µF
1 µF C38
+
100 pF
100 pF
R67
2 kΩ
+ +
R54
R62
C42
22 µF
C47
15 kΩ
680 kΩ
2.2 µF C46
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCO VCO F0 SND FM SND BUS EQ VIDEO BUS BUS SELECTED TEST C1 Y1 CHROMA C2 Y2 SELECTED SYNC BLACK BLU GRN RED FAST BLU GRN RED BRT CONTRAST VID/
TANK1 TANK2 FILTER IF VCC IF GND FILTER OUT DATA CLOCK VIDEO IT IN IN KILLER IN IN Y ADAPTIVE IN LEVEL IN IN IN SWITCH OUT OUT OUT ABL (PIX) CHROMA
IN OUT OUT FILTER OUT CORING DET IN FILT ABL GND
FILT
LA7615
AUX RF WB PIF RAMP HORIZ SAND VID
FM IF VIDEO AGC AUDIO APC IF PIF PIF PIF PIF SIF SIF AFT CHROMA VERT SIZE VERT ALC E-W HORIZ HORIZ STANDBY AFC HORIZ X CASTLE DAC IB CHROMA
DISCRI VCC IN OUT OUT FILTER GND IN1 IN2 AGC1 AGC2 IN AGC OUT APC XTAL VCC COMP OUT FILTER OUT RES GND VCC FILTER OUT FLYBACK RAY OUT OUT IN VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
+7.6 V
+ +7.6 V +7.6 V +7.6 V
LA7615
C3
C8
C9
1 µF
C10
C12
+9 V
R4
0.01 µF
0.01 µF
7.5 kΩ
C25
0.022 µF
+
R16
+
C2
+
0.033 µF
R13
C7
R10
R5
1 µF
+
C35
R75
C34
50 kΩ
C29
R40
R42
C22
10 kΩ
C118
100 µF
2.2 kΩ
0.01 µF
CSB503F (44)
R26
100 kΩ
1 kΩ
0.01 µF
0.01 µF
0.01 µF
C19
0.47 µF
16 pF
C15 3 kΩ
R2
C31
R3
R14 100 kΩ
T101 + +
100 Ω
150 Ω
100 kΩ
0.033 µF
R11
V101 +
50 Ω
C11
C13 R12 0.01 µF
R36
1 µF
R28
R27
M
1.8 kΩ 1 µF
10 kΩ
10 kΩ
0.047 µF 820 Ω
766-2
C24
R18
6.2 kΩ 10 µF C17
0.47 µF
R76 + +9 V + +7.6 V
+
R43
1 kΩ
IF1
R1
C4
C1
+ +
75 Ω
R7
R9
100 µF
C21
0.47 µF
16 Ω
50 Ω
C14
1T363
100 µF
C23
3.9 kΩ
C26
10 µF
10 µF
0.01 µF
*
R41
1 kΩ
C6
R25
CHR1
3.3 kΩ
0.01 µF
R15
+
750 Ω
R8
R6
C28
68 Ω
16 Ω
C119
C27
10 µF
0.01 µF
0.01 µF
+9 V
1744
R22
C117
Tr1
7.5 kΩ
0.01 µF
C16
2 3 4 5 6 9 11 12 13 14 16 17 18 19 21 24 28 29 30 31 32
0.01 µF
VIF
R17
R21
+7.6 V
470 Ω
1.6 kΩ
IN 26
DELAY2
R33
5 kΩ
R38
1 kΩ
*: Used for adjusting the characteristics of the crystal oscillator. (9US)
+7.6 V
R32
8.2 kΩ
C30
NC
1500 pF 1 2 3 4 5 6 7 8
LC4528B
+7.6 V
16 15 14 13 12 11 10 9
NC
C22
R34 R37
2200 pF
5 kΩ 8.2 kΩ
WIDTH (12US) (Includes two monostable multivibrators.)
A10105
No. 5841-38/39
LA7615
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of September, 1999. Specifications and information herein are
subject to change without notice.
PS No. 5841-39/39

Package Dimensions: Single-Chip NTSC Color TV IC

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Ordering number : ENN5841

Overview Package Dimensions

in software and the simplification of end product design.

• I2C bus control, VIF, SIF, Y, C, and deflection circuits

SANYO Electric Co.,Ltd. Semiconductor Company

Operating Conditions at Ta = 25°C

<Luminance and Chrominance Circuits>

<f0 Mode Selection>

<Luminance System Circuit>

<Horizontal Circuit Functions>

<Vertical Circuit Functions>

Vertical S-Curve Correction

Bus : Control Register Bit Allocation Map

Bits are transmitted in this order

Bus : Control Register Bit Allocation Map

Bits are transmitted in this order

Table 8 : Status Register Bit Allocation Map

Bus : Control Register Truth Table

Bus : Status Register Truth Table

time ≥ 2ms ON/OFF Initialize ON/OFF Initialize Mute

Continued from preceding page.

Continued on next page.

Continued from preceding page.

Continued on next page.

Continued from preceding page.

Apply 7.6 V to pin 2 and measure the DC

Apply 7.6 V to pin 60 and measure the DC

VIF Block - Input Signals and Test Conditions

SG2 42.17 MHz

SG3 41.25 MHz

SG4 Variable frequency

SG5 45.75 MHz

SG6 45.75 MHz

SG7 45.75 MHz

First SIF Block - Input Signals and Test Conditions

SIF Block - Input Signals and Test Conditions

Video Block - Input Signals and Test Conditions

X IRE signal (L-X)

Black stretch 0 IRE signal (L-BK)

<R/G/B IN input signal>

RGB input signal 2 (O-2)

Contrast adjustment Measure the output signal 50 IRE amplitude (CNTCB

With the input signal CW = 100 kHz, measure the

With the input signal CW = 2.2 MHz, measure the

Continued on next page.

Continued from preceding page.

Continued from preceding page.

Chrominance Block - Input Signals and Test Conditions

R-Y axis 90°

B (0) B-Y axis

8. The method for calculating the AF angle is shown below.

Burst 0° 90° 180° 270°

X IRE signal (L-X)

Burst 3.58 MHz 364°

28° 73° 118° 163°

Burst 3.48 MHz

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38 Measure the BOUT and ROUT output levels and calculate

Measure the GOUT output level and calculate the angle

Gradually decrease the amplitude of the input signal and

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Deflection Block - Input Signals and Test Conditions