A High Resolution FPGA-based Merged Delay
Line TDC with Nonlinearity Calibration
Yuan-Ho Chen
Department of Information and Computer Engineering,
Chung Yuan Christian University, Taiwan.
Email: yhchen@ice.cycu.edu.tw
Abstract—This paper proposes a merged delay line (MDL)
field-programmable gate array (FPGA) based time-to-digital
converter (TDC). Instead of traditional tapped delay line (TDL),
the proposed MDL-TDC merges several small delay cells to
improve the linearity performance effectively. Implemented in a
Xilinx XC5VLX110T-1FF1136 FPGA device, the proposed MDL-
TDC has 50 ps time resolution, and the ranges of differential
non-linearity (DNL) and integral non-linearity (INL) can be
reduced 16.6% and 5.4% as compared with traditional one,
respectively. Furthermore, 29 ps root-mean-square (RMS) is
measured for the proposed MDL-TDC inputting a constant delay
source. Therefore, the proposed MDL-TDC is recommended to
implement in FPGA-based TDC achieving a high-resolution time
and linearity performance.
Index Terms—Time-to-digital converter, Field-programmable
gate array, Differential non-linearity, Merged delay line.
I. I NTRODUCTION
Time-to-digital converter (TDC) is an essential component
in many scientific applications, such as positron emission
tomography (PET) scanners [1]-[3]. Recently, many researches
implement TDCs in field-programmable gate arrays (FPGAs)
due to the cost, development time, and flexibility [4]-[14].
Time resolution and linearity are the important issues in
the FPGA-based TDC design [5]. Kalisz et al. present the
calibration circuit in QuickLogic pASIC FPGA device to
achieve 200-ps resolution time, and the measured range of
TDC is 43-ns [6]-[7]. Song et al. employ the dedicated carry-
chain of FPGA devices to implement the tapped delay line
(TDL)-TDC [8]. After calibration, the resolution time of the
TDC implemented in an Altera EP1K50TC144-1 FPGA device
is 65 ps, and that of the TDC implemented in a Xilinx
XC2V4000-6BF957 FPGA device is 46.2 ps [8]. Due to
the uncertainty of the placed and routed (P&R) from FPGA
supported electronic design automation (EDA) tools, Wang et
al. introduce the LOC and RLOC operands to allocate the delay
cells in Xilinx family FPGAs [9]. Thus, the EDA tools can
automatic handle the P&R instead of the time consuming man-
made P&R. Furthermore, FPGA-based TDCs using dedicated
resources, such as Slice and DCM, are presented in [10]-
[11]. Besides, the ultra wide bins (UWBs) occur in FPGA-
based TDC due to the bank boundary. Wave Union TDCs are
presented to deal with the UWBs effect improving the time
resolution hugely because of the divided of the original bin
size [12]-[14].
978-1-4673-5762-3/13/$31.00 ©2013 IEEE
Start t1 t2 t3 tM
D Q D Q D Q D Q
FF FF FF FF
Stop
Encoder
TDC
Outputs
Fig. 1. The architecture of traditional TDL-TDC.
In this paper, merged delay line (MDL) TDCs are proposed
to improve the linearity. To divide the dedicated CARRY4 cell
in Xilinx Vertix-5 FPGA, the merged window chooses the
same time delay in all MDL cells. Thus, the small differential
non-linearity (DNL) values can be achieved, and the DNL
and integral non-linearity (INL) values of proposed MDL-
TDC can be reduced hugely as compared with the traditional
TDL-TDC. Implemented in a Xilinx XC5VLX110T-1FF1136
FPGA device, the proposed MDL-TDC achieves 50 ps reso-
lution and the ranges of DNL and INL are [−0.47, 0.62] and
[−0.87, 0.68] least-significant-bit (LSB), respectively. Further-
more, based on the constant delay source, the proposed MDL-
TDC achieves 29 ps root-mean-square (RMS) time resolution.
Thus, the proposed MDL-TDC is suitable to be applied to the
high-resolution applications in time measured.
This paper is organized as follows. In Section II, the design
of proposed MDL-TDC is presented that includes the architec-
ture of traditional tapped delay line, important issues for FPGA
design, and the proposed MDL-TDC. Experimental results and
discussions are presented in Section III, and conclusions are
drawn in Section IV.
II. P ROPOSED MDL-TDC D ESIGN
A. Traditional Tapped Delay Line TDC
The taped delay line (TDL) is the most used architecture in
FPGA-based TDC design. Figure 1 shows the architecture of
the M -bin TDC with traditional TDL architecture. It is easily
to be implemented using the M delay cells and registers, and
FPGA is a recommended platform to implement the TDL-
TDC because of its dedicated resources. The time resolution
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 Traditional TDL-TDC t1 t2 t3 tM

Start

200

D Q D Q D Q D Q
FF FF FF FF
150
Delay Time (ps)

Stop

100 Encoder

TDC
Outputs
50

Fig. 4. The divided CARRY4 cell in TDC design.

0 ti
0 20 40 60 80 100 120
Bin Number ti2

Fig. 2. The bin delay time of the traditional TDL-TDC.

ti1
ti3
COUT tiN

Merged Window
LUT
Gate Reg
D
D D Fig. 5. The proposed merged delay line.

LUT
Gate Reg TDL-TDC. By using the dedicated carry chains to implement
C
C C
the delay cells, the phenomenon of non-uniform distribution
is existed in every FPGA-based TDC. Therefore, the non-
LUT linearity calibration becomes more and more important in
Gate Reg
B
B B
FPGA-based TDC design.

LUT Gate C. Proposed Merged Delay Line TDC

Reg
A A
CARRY4
CIN
Fig. 3. A simplified diagram of SLICE in Xilinx Vertix-5 FPGA.
of the TDC is based on the delay cells in TDL architecture.
Therefore, the smaller time delay for the delay cell, the higher
time resolution can be achieved.
B. Issues of FPGA-based TDL-TDC Design
Two important issues in FPGA-based TDC with TDL archi-
tecture are resolution and non-linearity. The time resolution
in TDL-TDC can be improved by using high speed FPGA.
However, the non-linearity in FPGA-based TDC is difficult
to handle by using advanced FPGA. Figure 2 shows the cell
delay in Xilinx XC5VLX110T-1FF1136 FPGA device. In the
fast carry chain, CARRY4 is the dedicated resource in a single
slice of Xilinx Virtex-5 FPGA as shown in Fig. 3. Therefore,
CARRY4 can be implemented into a unit delay cell for a
A
Instead of the delay cell, the proposed merged delay line
(MDL) cell is applied to the FPGA-based TDC, and the
proposed MDL-TDC can improve the non-linearity effect of
the non-uniform delay cells. In general, the unit delay cell
is implemented using single CARRY4 cell in Virtex-5 FPGA.
However, the CARRY4 cell can be divided into four delay
element during the internal carry-chain. Thus, the TDC can
be shown as Fig. 4 Figure 5 shows the operation of the
proposed MDL cell. By sliding the merged window to choose
delay cells, small DNL effect can be achieved. The MDL cell
consists of 1 to N different delay cells {τi1 , τi2 , . . . , τiN },
and the proposed TDC chooses the same delay time in each
merged window to achieve small DNL values. Where N is the
window size and the definition of DNL is shown as follows:
ti
DN Li (LSB) = − 1. (1)
LSB
To achieve small DNL values, it must choose the delay cell
τik which has the minimal deference from LSB △ τik . For
this reason, the choosing of the delay cell for each MDL cell

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 Differential Nonlinearity of Original TDL-TDC. [-0.99908,3.7339] LSB.
Differential Nonlinearity of Proposed MDL-TDC. [-0.53702,0.62241] LSB.

3 0.5
DNL (LSB)

DNL (LSB)
1 0
0

-0.5
0 20 40 60 80 100 120
0 20 40 60 80 100 120
Bin Code
Bin Code
Integral Nonlinearity of Original TDL-TDC. [-16.1933,4.6398] LSB.
Integral Nonlinearity of Proposed MDL-TDC. [-1.0179,0.75219] LSB.

0 0.5
INL(LSB)

INL(LSB)
-5 0

-10
-0.5

-15
-1
0 20 40 60 80 100 120 0 20 40 60 80 100 120
Bin Code Bin Code

Fig. 6. The DNL and INL of traditional TDL-TDC. Fig. 7. The DNL and INL of the proposed MDL-TDC as N = 4.

Differential Nonlinearity of Proposed MDL-TDC. [-0.47339,0.62241] LSB.

is the minimal △ τik not the smallest delay time τik . 0.6
0.4
t1 ≈ t2 ≈ · · · ≈ tM (2)
DNL (LSB)

0.2
ti = M in{△ τi1 , △ τi2 , · · · △ τiN } (3) 0
△ τik = abs{τik − LSB} (4) -0.2
-0.4
where M in{•} and abs{•} are the minimum and absolute 0 20 40 60 80 100 120
operators, respectively. Bin Code
Integral Nonlinearity of Proposed MDL-TDC. [-0.87306,0.67578] LSB.
III. E XPERIMENTAL R ESULTS AND D ISCUSSIONS 0.5
The experiments are conducted with the Xilinx XUPV5-
INL(LSB)

LX110T evaluation platform. The proposed MDL-TDC is 0

synthesized using Xilinx ISE 13.2 and implemented in Xilinx

-0.5
XC5VLX110T-1FF1136 FPGA device. For the code density
test [15], two pulse sources (Agilent 81130A pulse data 0 20 40 60 80 100 120
generator and a 100MHz oscillator with dedicated phase- Bin Code
locked loop) generate their own 166.7 MHz clock without
Fig. 8. The DNL and INL of the proposed MDL-TDC as N = 5.
synchronization. Thus, very slow ramp signal in time dif-
ference can be generated and 10 × 217 samples of averaged
Differential Nonlinearity of Proposed MDL-TDC. [-0.76306,0.62241] LSB.
TDC outputs can alleviate the jitter effect. Due to 50 ps time
resolution at 166.7 MHz frequency, 120 bins are needed to 0.5

divide 6 ns time duration.

DNL (LSB)

0
For the linearity test, the DNL and INL of TDL-TDC are
illustrated in Fig. 6. The proposed MDL-TDC can achieve
-0.5
different INL and DNL values because of different merged
window size is adopted. The INL and DNL values of window 0 20 40 60 80 100 120
size between 4 to 6 are shown in Fig. 7 - 9. The obtained Bin Code

DNL is between −0.999 and 3.73 LSB, and the obtained INL’s 0.5
Integral Nonlinearity of Proposed MDL-TDC. [-1.7441,0.51151] LSB.

range is [−16.19, 4.64] LSB in the TDL-TDC and the LSB bin
0
size of this measurement is 50 ps. After the merged calibration,
INL(LSB)

-0.5
the proposed MDL-TDC can improve the performance in DNL
and INL. Thus, the DNL’s range of the proposed MDL-TDC -1
can be reduced to [−0.47, 0.62] LSB, and the INL’s range is -1.5
[−0.87, 0.68] LSB (window size equal to 5), as shown in Fig. 0 20 40 60 80 100 120
8. Large number of DNL and INL can be improved in FPGA- Bin Code

based TDC by using proposed MDL architecture. Besides, Fig.

Fig. 9. The DNL and INL of the proposed MDL-TDC as N = 6.
10 shows the measured delay time of each bin for traditional

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 Traditional TDL-TDC
IV. C ONCLUSION
200
This paper proposes the MDL-TDC. The choosing of each
Delay Time (ps)

150 MDL cell delay time by merged window is based on the mini-
100 mal DNL constraint. Therefore, the measured results show that
50
a large number of DNL and INL improvement can be achieved
and a high time resolution also can be reached in the proposed
0
0 20 40 60 80 100 120 MDL-TDC. Consequently, the proposed MDL-TDC can deal
Bin Number
with dedicated non-uniform delay distribution in FPGA to
Proposed MDL-TDC (N=5)
80 achieve high linearity and high resolution performance.
Delay Time (ps)

60
ACKNOWLEDGMENT
40
This work was supported by the National Science Council
20
of Taiwan R.O.C., under project number NSC-101-2218-E-
0 033-005.
0 20 40 60 80 100 120
Bin Number
The author would like to thank Prof. Chih-Wen Lu for
providing the testing equipment.
Fig. 10. The bin delay time of TDL-TDC and MDL-TDC.
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