392
2, FEBRUARY 2011
A Synthesis-Based Bandwidth Enhancement
Technique for CMOS Amplifiers: Theory and Design
Deyi Pi, Member, IEEE, Byung-Kwan Chun, Student Member, IEEE, and Payam Heydari, Senior Member, IEEE
Abstract—A synthesis-based bandwidth enhancement technique
for CMOS amplifiers/buffers is presented. It achieves bandwidth-
enhancement ratio (BWER) of 4.84, close to a proven theoretical
upper limit of 4.93 for passive network with balanced capacitive
loads. By employing a step-by-step design methodology, the pro-
posed technique can be applied to any load condition, which is
characterized by the ratio between the load capacitance and the
output capacitance of the transconductor cell. Time-domain be-
havior of the proposed technique is examined. Two prototype am-
plifier/buffer circuits are designed using lower order passive net-
works to save chip area and circuit complexity. The test chips are
fabricated in a 0.18 m CMOS process, and measurements verify
the frequency- and time-domain analyses. The amplifier provides
18.5 dB gain and 28 GHz bandwidth, while consuming 52 mW
power from a 1.8 V supply.
Index Terms—Bandwidth enhancement, CMOS amplifier, pas-
sive network, peaking, wide-band amplifier.
I. INTRODUCTION
M ULTI-Gbps integrated circuits (ICs) for broadband
communication systems, once dominated by very
fast/expensive processes—such as GaAs or other III-V tech-
nologies—can now be realized in nanoscale CMOS processes.
Indeed, the integration capability of the CMOS process makes it
possible to develop a power- and area-efficient system-on-chip
(SoC) that incorporates the digital back-end and the high-speed
analog front-end on a single die. Despite the tremendous
progress made in designing high-speed circuits, there are still
important problems left to be addressed in order to take full
advantage of nanoscale CMOS. Resistively loaded differential
amplifiers/buffers are widely used in high-speed transceiver
front-ends due to their high operation speed and immunity
to common-mode noise. In order to further improve the op-
eration speed, many bandwidth-enhancing techniques have
been proposed in prior work, such as shunt peaking [1], series
peaking [1], T-coil peaking [1], [2], and combination of shunt
and series peakings [3], [4]. These circuits replace the simple
Manuscript received June 14, 2010; revised September 15, 2010; accepted
September 22, 2010. Date of publication November 29, 2010; date of current
version January 28, 2011. This paper was approved by Associate Editor Domine
Leenaerts. This work was supported in part by grants sponsored by Broadcom
Corporation and Intel Corporation.
D. Pi is now with Broadcom Corporation, Irvine, CA 92617 USA (e-mail:
dpi@broadcom.com).
B.-K. Chun and P. Heydari are with the Nanoscale Communication IC Lab-
oratory, University of California, Irvine, CA 92697 USA (e-mail: bchun@uci.
edu; payam@uci.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2010.2088290
0018-9200/$26.00 © 2010 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO.
resistive loads with more complex passive network to broaden
the bandwidth.
However, all the above techniques, with the exception of
shunt peaking, reach their claimed performance only under
some pre-specified load conditions. More precisely, the ratio
between the load capacitance and the output capacitance of the
differential pair needs to be set to a certain value (e.g., 1:1 in
[3]; and 9:1, 8:2 and 7:3 in [2]) to guarantee the bandwidth
enhancement promised by these approaches. [2] successfully
showed the validity of asymmetric T-coil peaking in improving
bandwidth under three different load conditions. It still remains
unclear whether and how the asymmetric T-coil peaking can
maintain its high 3 dB-bandwidth enhancement ratio (BWER)
under any load condition. On the other hand, shunt peaking
provides unvarying performance under any load conditions.
However, it suffers from a low BWER of 1.7 for a maximally
flat frequency response.
From a different perspective, Bode’s work in [5] started with a
theoretical study to prove that the maximum achievable BWER
(or to be more precise, average-gain’s (AG-) BWER, as defined
in Section II) in a BW-enhanced single-stage amplifier/buffer
is 4.93, under the balanced condition in which the load capac-
itance is equal to the output capacitance of the transconductor
cell. Then, a passive network with AG-BWER of 4.84 was syn-
thesized to approach this theoretical limit. In [6], we extended
Bode’s work to a more general and commonly encountered im-
balanced case, and explore new circuit topologies that achieve
BWER of 4.84 under any load condition.
This paper is an extension of [6]. We provide more extensive
analytical studies leading to a systematic design methodology
for the proposed bandwidth-enhancement technique. Moreover,
both frequency- and time-domain analyses are carried out to
provide more design insight. In addition to the experimental re-
sults shown in [6], we provide two new prototype results for
high-performance applications.
The paper is organized as follows. Section II provides several
definitions which give a more accurate evaluation of high-order
bandwidth-enhancement techniques. Sections III and IV in-
stantiate Bode’s theory on bandwidth’s upper limit calculation
for one-port and balanced two-port passive networks in the
context of CMOS differential amplifiers/buffers. Section V
extends this theory to the general case of imbalanced load
condition. Section VI introduces a step-by-step methodology
for designing bandwidth-enhancing networks under any load
condition. Section VII discusses time-domain behavior of the
proposed technique. Experimental results are demonstrated in
Section VIII. Finally, Section IX provides the conclusion.
PI et al.: A SYNTHESIS-BASED BANDWIDTH ENHANCEMENT TECHNIQUE FOR CMOS AMPLIFIERS: THEORY AND DESIGN 393

II. BACKGROUND AND DEFINITIONS

In amplifiers incorporating high-order filter loads with pass-
band frequency ripple, DC gain and 3 dB bandwidth are no
longer considered to be solid indications of gain and bandwidth
performance. In order to better evaluate the bandwidth-enhance-
ment performance of a high-order filter, we use the following
definitions:
Definition 1. Flat-Gain Bandwidth (FG-BW): If an amplifier
achieves a flat gain across the frequency range from 0 to ,
by definition, it will exhibit a flat-gain’s bandwidth of with
a gain of .
Definition 1 is only valid for an amplifier with flat gain re-
sponse. Definition 2 generalizes the gain and bandwidth to am- Fig. 1. Differential amplifiers/buffers with general one-port load.
plifiers with ringing in their frequency response.
Definition 2. Average-Gain and Average-Gain Bandwidth
(AG-BW): For a given frequency range from 0 to , if an am- load and parasitic output capacitors of the differential pair are
plifier’s pass-band frequency response exhibits low amplitude combined into a lumped capacitor . To maximize the band-
ripples, and areas of ripples above and below a gain level width of this amplifier using one-port load and under a given
(which is not necessarily equal to DC gain of the amplifier) are gain level, there should not be any additional capacitor placed
equal with one another,1 then, by definition, the amplifier has in the shunt branch of the network . Thus,
an average gain of and average-gain’s bandwidth of .
Based on Definition 2, we define a new BWER that can better (1)
evaluate the performance of an amplifier (or buffer) with high-
order bandwidth-enhancing network. Furthermore, is a physically realizable passive
Definition 3. Average-Gain Bandwidth-Enhancement Ratio impedance with the following properties:
(AG-BWER) and Flat-Gain Bandwidth-Enhancement Ratio 1) is an analytical function over the right-half s-plane
(FG-BWER): Consider two amplifiers with the same transcon- (RHP);
ductor cell and the same load capacitors. One amplifier 2) exhibits Hermitian symmetry;
incorporates a bandwidth enhancing passive network, while the 3) the real part of is non-negative; .
other uses a simple resistive load. Assuming the average-gain We calculate the natural logarithm of so as to separate
of the bandwidth-enhanced amplifier is equal to the DC gain of its amplitude and phase responses and be able to study them
the amplifier with resistive load, the ratio between the AG-BW distinctly, i.e.,
of the former and the 3 dB bandwidth of the latter is defined
as average-gain’s bandwidth-enhancement ratio (AG-BWER). (2)
As a special case, for amplifiers with flat pass-band’s gain
response, the AG-BWER can be redefined as flat-gain’s band- For a positive-real function , the phase shift varies be-
width enhancement ratio (FG-BWER). tween . As discussed in great details in [5, pp
406], an analysis based on the Cauchy integral theorem results
III. ONE-PORT BANDWIDTH ENHANCING NETWORK in (3):

A. Theoretical Analysis
(3)
A differential amplifier with a general passive one-port load
is shown in Fig. 1. In a one-port load, the input current flows
into the same port at which the output voltage is measured. where is the AG-BW (defined above). Eq. (3) actually states
Using small-signal model, the transfer function of this am- that if remains constant between 0 and , its maximum
plifier can be expressed as , where is the achievable value will be . In other words, the max-
transconductance of each differential-pair transistor and imum achievable flat magnitude-response within the
is the impedance of each one-port load. Two important ques- frequency range from 0 to is . Therefore, AG-BW
tions arise regarding the circuit of Fig. 1; (1) for any positive-real of this amplifier is twice the 3 dB bandwidth of the amplifier
impedance, is there any upper limit for AG-BWER? (2) If such with a resistive load and resistance value of , as shown
upper limit is proved to exist, which passive network(s) can in Fig. 2. Subsequently, the maximum achievable AG-BWER
achieve it? of any open-loop capacitively loaded amplifier with a one-port
is comprised of two components in parallel, i.e., BW-enhancing network is 2.
, where the impedance is positive-real. The To be able to synthesize a network with a driving-point
1In fact, here the area is calculated with respect to a non-linear frequency axis.
impedance of , the phase characteristic has to be determined.
However, we suppose the ringing to be small so that a linear frequency axis is Details about the phase characteristic of passive realizable
a good approximation. networks are provided in [5]. To achieve a maximum constant
394
Fig. 2. Frequency responses of one-port load with AG-BWER of 2 and original
RC load.
gain between 0 and , the phase shift in this frequency range
is derived as follows [5, p. 409]:
(4)
The phase shift at frequencies above has to be (i.e.,
for ), in order to guarantee the maximum
gain integral given in (3). Having derived phase and magnitude
responses, the frequency response of the impedance , there-
fore, becomes
(5)
Thus, a network with driving point impedance of in (5)
needs to be synthesized, as will be discussed in Section III-B.
B. Circuit Realization
To synthesize the passive one-port load whose driving point
impedance is given by (5) and can achieve the maximum
AG-BWER of 2, the admittance function is first derived:
(6)
A passive network realization of (6) is shown in Fig. 3(a). This
network is comprised of a lumped capacitor in parallel with
a well-terminated midshunt artificial transmission line (T-line)
with cut-off frequency of (the same used in Section III-A).
The two capacitors in the near-end termination are merged
into one lumped capacitor that corresponds to the load capacitor
. The midshunt artificial T-line without in its near-end
termination, in fact, realizes . Fig. 3(b) depicts the frequency
response of the circuit shown in Fig. 3(a), demonstrating how
the frequency responses of the artificial T-line and are su-
perimposed to result in the final response. The circuit achieves
a FG-BWER of 2. It is noteworthy that approaches at
frequencies much higher than , a behavior predicted by (1).
IV. TWO-PORT BANDWIDTH ENHANCEMENT NETWORK
WITH BALANCED LOAD
A. Theoretical Analysis
The maximum AG-BWER of 2 obtained from a one-port load
may not be sufficient for amplifiers/buffers used in ultra-broad-
band integrated circuits, thereby demanding the use of a more
general load network. Since only one input and one output are
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011
Fig. 3. (a) One-port load that can achieve FG-BWER of 2 and (b) its frequency
response.
of interest, a two-port load will present the most general case,
where the input current flows into one port while the output
voltage is taken from the other port. One reason to employ a
two-port load is that it is capable of providing a phase shift less
than , which, in turn, removes the AG-BW limitation set
forth in (3) by one-port networks. From another perspective, a
two-port network separates the load capacitor from the output
capacitor of the differential pair. Therefore, there is no longer a
big lumped capacitor that could have severely limited the band-
width. In this section, only the balanced case, in which the load
capacitance is equal to the output capacitance of the differential
pair, is studied. The more general case of imbalanced load will
be investigated in Section V.
For the balanced case, as proved in [5, pp. 441], the maximum
AG-BWER of an amplifier incorporating a passive two-port net-
work is , where is an integer number
and is defined such that the phase shift of the two-port network
reaches the expected multiple integer value of at infinitely
large frequencies. For an infinitely large value of , the max-
imum AG-BWER reaches its upper limit of . How-
ever, this will result in a very complicated network which must
exhibit infinite number of frequency sub-bands. On the other
hand, results in a realizable network—as will be illus-
trated later in this section—with an AG-BWER of 4.84 which
is only 2% lower than the upper limit of 4.93. We will, therefore,
synthesize the passive two-port load for the AG-BWER of 4.84.
An example of a two-port network that can achieve this
AG-BWER is a symmetric -network. Fig. 4 shows a differ-
ential amplifier that uses symmetric -network. The transfer
function of the circuit is given by , where
is the transimpedance from node to node . Note that
represents transimpedance rather than a driving-point
impedance, thus it may not necessarily be a positive-real func-
tion. This implies that the analysis we had for one port network
is no longer usable. To resolve this problem, another network
PI et al.: A SYNTHESIS-BASED BANDWIDTH ENHANCEMENT TECHNIQUE FOR CMOS AMPLIFIERS: THEORY AND DESIGN
Fig. 4. Differential amplifiers/buffers with balanced  -shape two-port load.
Fig. 5. The equivalent driving-point impedance of the  -network.
is analyzed whose driving point impedance is identical to the
transimpedance of this symmetric -network. In doing so,
is re-expressed as
(7)
As indicated in (7), the transimpedance is composed of
series combination of a positive and a negative driving-point
impedance, resulting in the equivalent circuit of Fig. 5.
It has already been shown in Section III that a general
driving-point impedance with a lumped capacitor sitting in its
shunt branch has an AG-BWER upper limit of 2, and this upper
limit can be attained using the low-pass filter (LPF) shown in
Fig. 3(a). On the other hand, with the same shunt capacitor ,
a bandpass filter (BPF) obtained using low-pass-to-band-pass
transformation from the LPF can achieve the same AG-BW.
If the positive and negative driving-point impedances in the
equivalent circuit of Fig. 5 are realized using these LP and
BP networks, respectively, each of them will thus provide
an AG-BWER of 2. The resulting two-port network contains
an overall phase shift of at very high frequencies.
Moreover, as shown in Fig. 6, the extra AG-BWER of 0.84,
as predicted for the case where , is attained from the
overlapping region. This is because the inductive component of
the negative impedance in Fig. 5 compensates for the roll-off
in the transition region of Fig. 6 associated with the capacitive
reactance of the positive impedance. Further separation of the
LP and BP sections will clearly provide larger bandwidth but
at the expense of dip in the gain, thereby lowering the average
gain. Section IV-B discusses the synthesis of the two-port
network with AG-BWER of 4.84.
395
Fig. 6. Frequency response of the two-port load achieving AG-BWER of 4.84.
B. Circuit Realization
The positive driving point impedance comprising of
and in Fig. 5 is synthesized as a low-pass one-port BW-en-
hancing network with AG-BWER of 2. Using the same
procedure illustrated in Section III, in Fig. 5 should be a
part of an artificial LC T-line with a characteristic impedance
of and a cut-off frequency of , where is the resistive
load in the original amplifier. The impedance of the positive
part will be capacitive at frequencies greater than the cut-off
frequency and will asymptotically approach at increas-
ingly higher frequencies. Therefore, the circuit combination
in Fig. 5 approximately behaves as
in the bandpass frequency range. This notion also implies
that the branch in the negative part of the equivalent
circuit can be neglected. As a result, a circuit realizing
is synthesized in such away that forms a
bandpass artificial T-line (to construct the BP portion of Fig. 6
and to achieve maximum AG-BWER) with center frequency
of (covering the frequency range from to
), bandwidth of , and characteristic impedance
of . The complete network is shown in Fig. 7. The values
of circuit components in Fig. 7 with respect to and are
summarized in Table I.
V. TWO-PORT BANDWIDTH ENHANCING NETWORK
WITH IMBALANCED LOAD
Despite exhibiting an AG-BWER close to the theoretical
upper limit, the bandwidth-enhancement technique discussed
in Section IV suffers from a number of drawbacks that prevent
it from being used in high-speed ICs:
1) The analysis and realization of BW-enhancing networks in
Section IV are based on the assumption that the load capac-
itance is equal to the output capacitance of the differential
pair, which is typically invalid in high-speed ICs.
2) Too many inductors are to be used in the implementation
to reach the theoretical limit of 4.84 AG-BWER, which
makes the realization of the BW-enhanced circuit imprac-
tical in CMOS process.
To address the first issue, [5] proposed a method that per-
forms the impedance transformation using ideal transformer,
which results in an extra AG-BWER of .
However, the on-chip realization of such transformer exhibits
finite self-inductance, a less-than-unity coupling coefficient ,
and resistive loss, all of which contributing to degradation of
396 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011

Fig. 7. Two-port network that can achieve AG-BWER of 4.84.

TABLE I
COMPONENT PARAMETERS IN BALANCED TWO-PORT
BANDWIDTH ENHANCING NETWORK OF FIG. 7

Fig. 8. Differential amplifiers/buffers with imbalanced load.

AG-BWER. As a result, a design methodology based on a gen- A differential amplifier incorporating the asymmetric net-
eral analytical study of BW-enhancing networks under any load work with the load capacitance unequal to the output ca-
condition that tackles both issues is of utmost importance. The pacitance will be meticulously analyzed, and the method
following considerations contribute to practical implementation discussed in Section IV will be extended to the general case
of BW-enhancing networks: of imbalanced loads.
1) Lower-order LP and BP filters are used to realize the A differential amplifier/buffer with imbalanced two-port
building blocks of the two-port networks. Clearly, the load is shown in Fig. 8. and are the output and the
use of lower-order filters trades with a lower AG-BWER. load capacitances, respectively. We define ,
Such lower-order LPF should, however, closely follow the , , .
frequency-domain behavior of the infinitely long T-line The transimpedance of the circuit in Fig. 8 is
shown in Fig. 3(a). The design of low-order LPFs has been obtained as follows:
extensively discussed in traveling wave filter design books (8)
as well as in [5]. The BPF can be designed in a similar
way using LP-to-BP transformation. Similar to the analysis in Section IV, an equivalent circuit
2) The two-port -network of Fig. 4 employs two ’s, both whose driving-point impedance is equal to the transimpedance
of those realizing the same LPF. One of these impedance of Fig. 8 is constructed. To find this equivalent circuit,
elements can be dropped to further reduce the number of is re-expressed as
passive components. This, however, requires the analysis
of an asymmetric network (described later in this section). (9)
PI et al.: A SYNTHESIS-BASED BANDWIDTH ENHANCEMENT TECHNIQUE FOR CMOS AMPLIFIERS: THEORY AND DESIGN 397

Fig. 9. The equivalent driving-point impedance of the imbalanced  -network.

where is defined as
Fig. 10. Proposed bandwidth enhanced differential amplifiers/buffers.
(10)

Comparison between (9) and the equivalent driving-point

impedance in (7), also shown in Figs. 9 and 5, reveals topo-
logical similarity between the balanced and imbalanced cases
with a difference in the coefficient of , which is 1/4 in the
former and in the latter.
Scaling the impedance values will transform the imbalanced
to the balanced case. For a constant , the synthesis of BW-en-
hancing network resembles the one for balanced load by simply
multiplying the original by a factor of .
Moreover, it can be seen from Fig. 8 that two ’s are em-
ployed in the -network to implement its LPF part, which make
the number of passive components excessively large. To address
this problem, the passive network of Fig. 8 is simplified to two
possible circuits shown in Figs. 10 and 12. The following anal-
ysis shows that by correctly choosing between these two cir- Fig. 11. (a) Z and its approximation and (b) Z and its approximation.
cuits, can be approximated as a constant factor.
Two cases are distinctly analyzed, in order to find and syn-
thesize the BW-enhancing network, (1) and (2)
.
First, consider the case . As will be explained later
in this section, the factor remains approximately a constant
value if the impedance , sitting next to the smaller capac-
itor (in this case, ) is chosen to be dropped. Dropping
correspondingly reduces passive components, resulting in the
amplifier shown in Fig. 10. The impedances and of
this new network are to be determined such that the equivalent
driving-point impedance of the network in Fig. 10 becomes the
same as that of the balanced case. This way guarantees that, for a
Fig. 12. Proposed bandwidth enhanced differential amplifiers/buffers (mir-
given gain level and total capacitance, this imbalanced network rored version).
achieves the same AG-BWER as the balanced network.
We define and ( and
were defined earlier and , in this case), thus Consider the second case where . Naturally, the pas-
. Referring to Fig. 9, solely contributes to the sive network used in Fig. 10 is the first topology to be exam-
bandpass portion of the equivalent driving-point impedance. ined. However, sits next to the smaller capacitance ,
The impedance approaches across which implies that the effect of on may not be ne-
bandpass frequency range, because , realized using the glected, leading to being highly frequency dependent. To ad-
ladder LC circuit in Fig. 3(a), is inductive and exhibits high dress this quandary the impedance is moved to the right
impedance across this frequency range, compared to the reac- port near the larger capacitor , as shown in Fig. 12. Accord-
tance associated with . Similarly, approaches ingly, and , which cor-
since . Therefore, as shown responds to a previously discussed situation with
in Fig. 11, becomes a positive constant and simply being swapped. Eqs. (8) and (10) clearly indi-
cate that both and are symmetric with respect to and
(11)
, verifying the reciprocal property of passive networks [7].
398
Fig. 13. (a) Proposed circuits with fifth-order LPF and sixth-order BPF and
(b) its normalized simulated frequency response.
Thus, of the passive networks of Figs. 10 and 12 become
the same when and get swapped.
By correctly choosing the circuit in Figs. 10 or 12 based on
whether or , a bandwidth enhancing network
can be synthesized under all load conditions, while achieving the
same BWER close to the theoretical limit of 4.84. Fig. 13(a) de-
picts the proposed bandwidth-enhancing circuit incorporating a
fifth-order LPF and a sixth-order BPF. Fig. 13(b) demonstrates
the simulated frequency response under seven load conditions,
where the frequency and gain are normalized to the 3 dB-band-
width and DC-gain of the original resistive load buffer/ampli-
fier. It can be seen that the circuit achieves an AG-BWER of 4.7
under various load conditions.
Another advantage of the proposed bandwidth enhancing
techniques is that high Q inductors are not needed since both
the low-pass and bandpass portions employ low-Q filters. More
precisely, all of the inductors are sitting either in series or in
parallel with a needed resistor, therefore, the loss in the induc-
tors can be compensated by reducing the loss of the explicit
resistors.
Moreover, compared to a single-stage circuit, higher
AG-BWER can be achieved using multi-stage bandwidth-en-
hanced buffers/amplifiers. This is because the frequency
response of a resistively loaded differential amplifier starts
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011
TABLE II
DESIGN STEPS
dropping from DC (cf. Fig. 13(b)), whereas the frequency
response of the proposed circuit is relatively flat between DC
and the upper corner frequency [5]. The cascaded amplifier
with resistive load provides times the bandwidth of
each stage [1], where is the number of stages. In contrast,
when cascaded, the bandwidth of the proposed circuit is still
approximately equal to that of each stage. This results in (12)
and will be verified in the following section.
(12)
VI. CIRCUITS DESIGN
Table II summarizes a step-by-step design procedure using
the above analysis. To account for ripples that may appear on
the magnitude response due to parasitics, retuning of the filters’
parameters is necessary. For example, to compensate for pas-
sive losses that degrade the Q of the BP portion, the termination
resistor in needs to be re-adjusted.
Depending on different orders of filters being chosen, the
proposed BW-enhancing network can assume various topolo-
gies. In choosing the order of filters for LP and BP portions,
the number of inductors is of great importance to accommodate
on-chip integration. From the area and complexity perspective,
the preferable network employs only one inductor for each of
the LP and the BP portions, resulting in a second- or third-order
LPF and a second-order BPF.
The designs of several prototype single/two-stage circuits
were presented in [6] to show the applicability of the proposed
technique under various load conditions. In this paper, we
present two new high-performance multi-stage circuits.
Some applications need tapered buffer chain instead of a
single buffer to provide high bandwidth, capability to drive
large loads, and low input capacitance at the same time. As
shown in Fig. 14, a three-stage buffer chain has been designed,
fabricated, and measured. The circuit is designed to drive a 0.38
pF capacitor (input capacitance of the 50 driver) while has
only 47 fF input capacitance. Active inductors and symmetric
transformers are used to save area.
A four-stage amplifier has been designed, fabricated, and
measured. The amplifier provides high gain and high band-
width, while consuming relatively low power. The circuit is
based on the proposed BW-enhancement technique incorpo-
rating a third-order LPF and a second-order BPF. All the stages
are the identical, as shown in Fig. 15.
Fig. 16(a) and (b) show the frequency responses of the
four-stage amplifier, simulated in SpectreRF. The magnitude
PI et al.: A SYNTHESIS-BASED BANDWIDTH ENHANCEMENT TECHNIQUE FOR CMOS AMPLIFIERS: THEORY AND DESIGN 399

Fig. 14. Proposed area-saved bandwidth-enhanced buffer chain with second-order LPF and second-order BPF.

Fig. 15. Proposed bandwidth-enhanced four-stage amplifier with third-order LPF and second-order BPF.

Fig. 16. (a) Magnitude and (b) phase responses of the proposed bandwidth-enhanced four-stage amplifier at the output of each stage.

response at the output of each stage is shown in Fig. 16(a), ver-
ifying an earlier observation that the bandwidth of the proposed
circuit does not significantly drop with increasing number of
stages. The phase response of the amplifier is approximately
linear within its bandwidth, as shown in Fig. 16(b).
VII. TIME-DOMAIN BEHAVIOR
High-speed data communication, as one of the main applica-
tions of the proposed technique, requires not only a broad band-
width, but also a well-behaved time-domain response. To cap-
ture temporal behavior of the BW-enhanced amplifiers, a simple
model is developed. Naturally, the time-domain behavior of the
BW-enhanced amplifiers circuit is quite different from that of
the resistively loaded counterpart.
The magnitude responses of the proposed circuit, shown in
Fig. 16(a), depict a nearly flat response within the pass-band
and a sharp roll-off at frequencies beyond the bandwidth. With
a nearly linear phase response within the pass-band, as shown
400
Fig. 17. Die photo of the three-stage buffer chain and the four-stage amplifier.
in Fig. 16(b), it can be concluded that the frequency-domain
behavior of the proposed circuit is roughly similar to that of
an ideal low-pass filter. So its step response becomes close to
a sine integral function, with delay of , rise time of ,
and local maximums and minimums at which
can be used to minimize ISI.
This model is also a good approximation for other two-port
bandwidth-enhancement techniques, including shunt-series
peaking and series-shunt peaking, because these techniques
also have such sharp roll-off at frequencies beyond the band-
width. At higher and higher frequencies beyond the bandwidth,
more and more current is driven into and the current fol-
lowing into the load capacitor drops at 20 dB/decade or
40 dB/decade, depending on the impedance sitting between
the two ports, whereas in one-port case it is approaching a
constant. Thus, the stop-band gain drops by 40 dB/decade or
60 dB/decade in two-port case.
VIII. MEASUREMENT RESULTS
The two new circuits depicted in Figs. 14 and 15 were fabri-
cated in a 0.18 m CMOS process, with the die photos shown
in Fig. 17. The die area of the three-stage buffer is 0.88 mm
including the pad ring, while the four-stage amplifier consumes
1.24 mm .
Frequency-domain measurements were carried out using
Agilent E8361A network analyzer. The frequency response
of the 50 driver was de-embedded from the measurement
results. Time-domain measurements were carried out using
an Anritsu MP1800A signal quality analyzer, an Anritsu
MP1803A multiplexer, and an Agilent 86100C sampling oscil-
loscope.
The measured frequency response of the three-stage buffer
chain is shown in Fig. 18. The high frequency peaking is caused
by the modeling inaccuracy on the quality factor of the sym-
metric transformers.
Fig. 19 shows both measured and simulated frequency re-
sponse of the bandwidth-enhanced four-stage amplifier. The
measured DC gain is 18.5 dB and 3-dB bandwidth is mea-
sured at 28 GHz. The four-stage amplifier draws 29 mA current
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011
Fig. 18. Measured frequency response of the three-stage buffer chain.
Fig. 19. Simulated and measured frequency response of the bandwidth-en-
hanced four-stage amplifier.
from a 1.8 V power supply while the 50 driver consumes
9 mA.
For the step response measurement, the data source was set
to have large amplitude to emulate the infinite slew rate of step
input. The output waveform with a long run of zero followed by
a long run of one was measured. Fig. 20 shows the measured
step response of the amplifier, compared with the simulated one
and the prediction of the time-domain analysis. Here the am-
plitude scale and the time offset of the measured step response
have been adjusted to fit the simulated one, since they depend on
the measurement setup and are hard to predict. From the figure
we can see that all the three are similar, verifying the analysis in
Section VII. The only significant difference is at the first over-
shoot, where the measured step response has lower overshoot
level. This can be attributed to the channel loss and the clipping
behavior of the 50 driver.
The measured eye-diagram of the measurement setup itself
at 25 Gb/s data-rate is shown in Fig. 21(a). The measured
eye-diagrams of the four-stage bandwidth-enhanced amplifier
at 25 Gb/s and 32 Gb/s data rates are shown in Fig. 21(b) and (c),
respectively. Part of the jitter is caused by the channel loss,
and another portion is due to the lack of precision time-base
reference module for the oscilloscope.
PI et al.: A SYNTHESIS-BASED BANDWIDTH ENHANCEMENT TECHNIQUE FOR CMOS AMPLIFIERS: THEORY AND DESIGN 401

TABLE III
COMPARISON OF BANDWIDTH-ENHANCED AMPLIFIERS

Theoretical

Fig. 20. Measured, simulated, and modeled step responses of the four-stage
amplifier.

Table III summarizes the measured performance of the four-

stage amplifier, compared with other recently published work.

IX. CONCLUSION
A synthesis-based bandwidth enhancement technique for
passively loaded amplifier and buffers was introduced. It
achieves a BWER of 4.84, which is close to the theoretical
limit for balanced load condition. Further theoretical analysis
of the imbalanced case was carried out to extend this technique
to general load conditions. A complete step-by-step design
methodology was then developed, and design insights were pro-
vided. A simplified time-domain analysis was also presented.
Using the proposed technique, two prototype circuits were
designed and fabricated in a 0.18 m CMOS process. Measure-
ment results showed significant performance enhancement.

ACKNOWLEDGMENT
The authors would like to thank Jazz Semiconductor for chip
fabrication, and Anritsu and Agilent for measurement equip-
ment. The authors would also like to thank Dr. Hui Pan and the
anonymous reviewers for their valuable suggestions on the man-
uscript.
Fig. 21. Measured (a) eye-diagram of the measurement setup at 25 Gb/s.
REFERENCES (b) output eye-diagram of the four-stage amplifier at 25 Gb/s and (c) 32 Gb/s.
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Deyi Pi (S’06–M’09) received the B.E. degree from
Tsinghua University, Beijing, China, in 2005, and the
M.S. degree from the University of California, Irvine,
in 2007, both in electrical engineering.
He interned in the Mixed Signal Engineering De-
partment of Broadcom Corporation, Irvine, CA, in
summer 2006 and 2007. He is now with the same
group working on high-speed transceivers.
Mr. Pi was a recipient of the 2007 AMD/CICC
Student Scholarship Award and a co-recipient of the
2008 ISLPED Low Power Design Contest Award. He
was a Gold Medal winner of the National Olympiad in Informatics, China.
Byung-Kwan Chun (S’09) received the B.S. de-
gree in metallurgy and materials engineering from
Hanyang University, Korea, in 1999 and the M.S.
degree in electrical engineering from the University
of Southern California, Los Angeles, in 2002. Since
2006, he has been pursuing the Ph.D. degree at
Nanoscale Communication IC Lab in electrical
engineering, University of California, Irvine.
From 2002 to 2006, he was with the Samsung
Electronics as an engineer in the DRAM Design
Group, where he worked on the design and devel-
opment of Advanced High Speed DRAMs such as Multi Media DRAM and
Rambus DRAM and many kinds of Synchronous DRAMs such as DDR-II,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 2, FEBRUARY 2011
III. He interned in the Wireless Connectivity Group of Broadcom Corporation,
Irvine, CA, in summer and fall 2008. His research interests include high-fre-
quency and low-power integrated circuits design for wireless communications.
Payam Heydari (M’00–SM’07) received the B.S.
and M.S. degrees (Honors) in electrical engineering
from Sharif University of Technology, Tehran,
Iran, in 1992 and 1995, respectively. He received
the Ph.D. degree from the University of Southern
California, Los Angeles, in 2001.
He is currently a Full Professor of Electrical En-
gineering at the University of California, Irvine. He
is the director of the Nanoscale Communication IC
(NCIC) Lab. During the summer of 1997, he was with
Bell Labs, Lucent Technologies, where he worked on
noise analysis in high-speed CMOS integrated circuits. He worked at IBM T. J.
Watson Research Center on gradient-based optimization and sensitivity analysis
of custom ICs during the summer of 1998. His research interests include design
of ultra-high frequency analog/RF/mixed-signal integrated circuits. Results of
the research in the NCIC Lab have appeared in more than 80 peer-reviewed
journal and conference papers.
Dr. Heydari is the co-recipient of the 2009 Business Plan Competition First
Place Prize Award and Best Concept Paper Award both from Paul Merage
School of Business at UC-Irvine. He is the recipient of the 2010 Faculty of
the Year Award from UC-Irvine’s Engineering Student Council (ECS), the
2009 School of Engineering Fariborz Maseeh Best Faculty Research Award,
the 2007 IEEE Circuits and Systems Society Guillemin–Cauer Award, the
2005 IEEE Circuits and Systems Society Darlington Award, the 2005 National
Science Foundation (NSF) CAREER Award, the 2005 Henry Samueli School
of Engineering Teaching Excellence Award, the Best Paper Award at the 2000
IEEE Int’l Conference on Computer Design (ICCD), and the 2001 Technical
Excellence Award from the Association of Professors and Scholars of Iranian
Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty in the
EECS Department of the University of California, Irvine. His research on novel
low-power multi-purpose multi-antenna RF front-ends received the Low-Power
Design Contest Award at the 2008 IEEE Int’l Symposium on Low-Power
Electronics and Design (ISLPED).
Dr. Heydari is the Guest Editor of IEEE JOURNAL OF SOLID-STATE
CIRCUITS. He currently serves on the Technical Program Committees of Com-
pound Semiconductor IC Symposium (CSICS), Custom Integrated Circuits
Conference (CICC) and ISLPED. He served as the Associate Editor of IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS I from 2006 to 2008. He was the
Local Arrangement Chair of the 2004–2005 ISLPED, and the Student Design
Contest Judge for the 2003 DAC/ISSCC Design Contest Award. He served
on the Technical Program Committees of and Int’l Symposium on Quality
Electronic Design (ISQED), IEEE Design and Test in Europe (DATE) and
International Symposium on Physical Design (ISPD).