A Novel Space-Vector PWM Computations for A
Dual Three-Level T-Type Converter Applied to An
Open End-Winding Induction Machine
Aboubakr Salem,
Electrical Power & Machines Dept.
Faculty of Engineering, Helwan University.
Cairo, Egypt
aboubakr.salem.hu@gmail.com
Abstract—Space-vector pulse-width modulation (SVPWM)
computations are complex particularly for multilevel converters.
This paper introduces a novel SVPWM computation method for
multilevel converters. General formulas for the region identifi-
cation as well as for PWM intervals calculation are proposed.
Then, the proposed formulas are applied to the advanced dual
three-level T-type converter topology. The operation of this
advanced topology applied to an open end winding induction
machine (OEWIM) is discussed in more details. A simulation
study for the proposed AC drive system is performed by using
MatlabTM /Simulink⃝R
. A hardware implementation based on a
field-programmable gate array (FPGA) for the advanced topology
supplying an OEWIM is presented, discussed and analysed.
The computation algorithm is built within the FPGA digital
controller. A comparison between experimental and simulation
results is performed. It is observed that the simulation and
the experimental results are agreed and verified the proposed
algorithm.
Index Terms—SVPWM, Multilevel converter, harmonic anal-
ysis.
I. I NTRODUCTION
The two-level voltage source inverter (VSI) is a cheap con-
verter and has spread in industry particularly low-voltage AC
drive applications. However, this converter produces a large
harmonic content to the connected machine, which increases
the machine losses and also affects its lifetime [1]. This
problem can be solved by using a harmonic filter to reduce the
output harmonic content. However, this solution is considered
expensive and increases the converter size. Also, the connected
filter will have its own losses [2]–[6]. Another solution is to
increase the frequency of the steering pulses, which is the
switching frequency of the pulse-width modulation (PWM)
technique. However, this way increases the converter switching
loss [5], [6]. The multilevel VSI is a better alternative to the
two-level VSI in AC drive and renewable energy integration
applications. It has the advantage of delivering AC power
including low harmonic content and reducing the stress on the
semiconductor switches. Moreover, it can reduce the coupling
filter size which is used for grid-tie converter in renewable
energy applications [7]–[11].
The most well known multilevel converters are the diode-
clamped converter (DCC), the flying capacitor converter
(FCC), and the cascaded H-bridge (CHB) converter. Each
one of these converters has its own advantages and draw-
backs [12]–[14]. However, a common drawback of multilevel
converters is the large amount of semiconductors used in
978-1-4673-9063-7/16/$31.00 ⃝IEEE
c
Frederik De Belie, and Jan Melkebeek,
Electrical Energy System & Automation Dept.
Faculty of Engineering & Architecture,
Ghent University.
Gent, Belgium
the power circuit. This problem has motivated researchers to
develop more advanced multilevel VSI circuits which have
a lower number of semiconductors to reduce the converter
complexity and cost. Some enhancements have been developed
for the multilevel converter power circuits.
The T-type three-level converter is one of the advanced DCC
topologies, that has the advantages of a lower amount of
switching devices and a higher efficiency compared to con-
ventional neutral point clamped (NPC) converters [15]–[18]. In
[19], [20], modified five-level T-type converters with a reduced
number of switches are introduced. In [5], [19], the five-
level T-type as well as the dual three-level T-type advanced
converter topologies have been studied and compared to the
conventional five-level DCC. It has been proved that the
two T-type topologies have higher efficiency compared to
the conventional DCC. For this purpose, the dual three-level
T-type converter is studied in this paper to test the novel
SVPWM computations.
There are several techniques can be used to control multi-
level converter; i.e. sinusoidal PWM, selective-harmonic elim-
ination PWM, space-vector control and space vector PWM
(SVPWM). The last technique has been introduced in the mid-
80s [21]. Its advantages include a good utilization of the DC
link voltage and generating waveforms with low harmonic
distortion. As a result, the SVPWM technique is of interest
for AC drive applications [22]–[27]. The main problem of the
SVPWM is the complexity of the required calculations partic-
ularly for multilevel converters with high number of voltage
levels. Several calculating techniques have been introduced in
order to simplify the SVPWM calculations in [28]–[30]. A
different technique will be introduced, discussed and verified
practically in this study.
The target of this paper is to propose a simple method for
the SVPWM computations for multilevel converters. Then,
proposing a generalized model for N-level converter SVPWM
computation. Moreover, studying this technique for the dual
three-level T-type converter advanced topology when supply-
ing an open-end winding induction machine (OEWIM). For
this purpose, a novel technique for the voltage vector operating
region is proposed. Then, the switching time periods are
calculated using a general formula for any region within the
vector diagram. A switching pattern is designed to reduce the
converter switching-stress. An evaluation for the converter and
the proposed algorithm is performed in this study by analysing on the converter switching states, the space vector is calculated
the output waveforms and its harmonic contents at different by using (1) [21], [31].
switching frequency values i.e. 2.5 kHz, 5 kHz, and 10 kHz
in order to show the effect of this frequency on the voltage 2
V= (v ′ + ej2𝜋/3 .vVV′ + e–j2𝜋/3 .vWW′ ) (1)
and current harmonic contents. 3 UU
II. O PERATION OF A D UAL T HREE -L EVEL T- TYPE For a three-level T-type converter, the number of possible
T OPOLOGY switching states is 27. By applying the space-vector relation
It is important to analyse the performance of the dual to the 27 switching states (i.e. state 1:27). By applying these
T-type converter topology in a complete AC drive system. switching states to the space vector relation (1), the vector
An induction machine (IM) mechanically connected to a DC diagram of the three-level T-type converter can be represented
machine is selected as load. This setup allows to measure the as in Fig. 2. This vector diagram consists of 19 different
performance of the system at different loading conditions. Due vectors i.e. O, a1 – A6 , b1 – b12 . This vector diagram can be
to the limited space, the study in this paper will focus on described by (2) where 𝛼 is the sector angle.
the operation of the proposed AC drive system at full load.
Fig. 1 shows the wiring diagram for the dual T-type converter vax = 0.5 e(–i𝛼) ;x = 1 : 6
topology, supplied by isolated DC sources, and connected to an (–i𝛼)
vbx = 1 e ; x = 1 : 2k – 1; k = 1 : 6 (2)
OEWIM. The following subsection describes the operation of √ ( )
the proposed converter topology by using SVPWM technique. 3 –i(𝛼+ 𝜋 )
vby = e 6 ; y = 2m; m = 1 : 6
The possible switching states and the output voltages of phase- 2
U are summarised in Table 1.
Unlike the conventional five-level converter which has
Table 1: The possible switching states and the output voltage
for a single phase of a dual three-level T-type converter. b5 b4 b3
12
11 10
Converter-1 Converter-2 Connected points VUU′ b6 13 a3 a29 b2
Q3U , Q4U Q1U′ , Q2U′ P-N’ + Vdc 14 2 8
Q3U , Q4U Q4U′ , Q2U′ P-O’ + Vdc /2 b7 15 a4
3
o1 a17 b
1
Q2U , Q4U Q1U′ , Q2U′ O-N’ 16 4 5 6 24
23
Q3U , Q4U Q3U′ , Q4U′ P-P’ 17 a5 a6
Q2U , Q4U Q2U′ , Q4U′ O-O’ 0 b8 b12
18 20 22
Q1U , Q2U Q1U′ , Q2U′ N-N’ 19 21
Q2U , Q4U Q3U′ , Q4U′ O-P’ - Vdc /2 b9 b10 b11
Q1U , Q2U Q2U′ , Q4U′ N-O’
Q1U , Q2U Q3U′ , Q4U′ N-P’ - Vdc Fig. 2. Vector diagram for three-level converter.

P
i1 converter-1 125 switching states, the dual three-level T-type topology is
Q3U Q3V Q3W
Vdc/4 Q4U Q2U considered as a five-level converter and has 729 switching
U
Q4V Q2V iu states (which results from squaring the 27 switching states of
i2 V
O each three-level T-type converter), and produces 61 different
Q4W Q2W iv
W vectors, i.e. O, A1 –A6 , B1 –B12 , C1 –C18 , D1 –D18 as described
Vdc/4
iw in Fig.3. These vectors can be described by (3); where 𝛼 is
N i3 Q1U Q1V Q1W the sector angle which equals 0, 𝜋3 , 2𝜋 3𝜋 5𝜋
3 , 𝜋, 2 , and 2 for
Three-phase sectors 1, 2, 3, 4, 5 and 6 respectively.
open-end winding IM
P'
i' 1 Q3U' Q3V' Q3W' D9 D8 D7 D6 D5
Vdc/4 Q4U' Q2U'
D10 C7 C4 D4
U'
i' 2 Q4V' Q2V'
O' V' D11 D3
Q4W' Q2W'
Vdc/4 W' D12 D2

i' 3 Q1U' Q1V' Q1W' converter-2 D13 1 D1

N'

D14 D24
Fig. 1. Dual T-type multilevel converter C C18

D15 17 D23

III. SVPWM T ECHNIQUE A PPLIED TO A D UAL D16 C13 15 16

D22
T HREE -L EVEL T- TYPE C ONVERTER
D17 D18 D19 D20 D21
For multilevel converters, the number of possible switching
states for an m-level three-phase converter equals m3 . Based Fig. 3. Vector-diagram for Five-level dual T-type converter
 vAx = 0.25 e(–i𝛼) ;x = 1 : 6 An if-else statement for the region identifier for sector 1
(–i𝛼) is described by a flow chart as shown in Fig. 5- Fig. 7.
vBx = 0.5 e ; x = 1 : 11; odd only
( 𝜋
) The Md is the modulation index (the absolute value of the
vBy = 0.5 e –i(𝛼+ 6 ) ; y = 2 : 12; even only vector V), h is the vector V projection on the vertical axis and
vCx = 0.75 e(–i𝛼) ; x = 1, 4, 7, 10, 13, 16 hr =|oa1 |sin( 𝜋3 )=0.433. The other regions can be determined in
( 𝜋
) the same way. For the sector identification, a simple function
vCy = 0.6614 e –i(𝛼+ 9 ) ; y = 2, 5, 8, 11, 14, 17 is used to compare the angle 𝜃 to the values of 𝜋/3, 2𝜋/3, 𝜋,
( )
2𝜋 (3) 4𝜋/3 and 5𝜋/3 which are the angles of the six sectors.
vCz = 0.6614 e –i(𝛼+ 9 ) ; z = 3, 6, 9, 12, 15, 18
vDx = 1 e(–i𝛼) ; x = 1, 5, 9, 13, 17, 21
( 𝜋
) 58 57
vDy = 0.9014 e –i(𝛼+ 12.95 ) ; y = 2, 6, 10, 14, 18, 22 D5 27
√ ( ) locus for x5 locus for x2 26 V z t3 V y t2
3 –i(𝛼+ 𝜋 ) 61
vDz = e 6 ; z = 3, 7, 11, 15, 19, 23 locus for x3 60 locus for x4 V
2 ( ) 29 59 56
𝜋 locus for x1 28 58 locus for x6
vDj = 0.9014 e –i(𝛼+ 3.95 ) ; j = 4, 8, 12, 16, 20, 24 A2 9 27 57 25
55

8 7 26 56 Vx
1
V t1
By analysing the vector-diagram and its corresponding 25 55
O A1 D1
switching states, it is observed that the ’A’ vectors can be Θ
(a) (b)
achieved by 216 switching states, the set of ’B’ vectors can
be achieved by 264 switching states, the set of ’C’ vectors Fig. 4. (a) Region-border calculation for sector-1, (b)
can be achieved by 156 switching states, and the set of D Example for one-region intervals calculation
vectors can be achieved by 48 switching states. Therefore, the
total number of switching states which produce a non-zero
vector is 684. The zero-vector O can be achieved by 45 passive
switching states. Another view, the hexagonal vector diagram
in Fig. 3 can be divided in six equilateral triangles (which are
called sectors): (OD1 D5 ), (OD5 D9 ), (OD9 D13 ), (OD13 D17 ),
(OD17 D21 ) and (OD21 D1 ). Each of these sectors includes
16 smaller triangles which called regions. After defining
the vector diagram of the proposed converter topology, the
next subsections describe the proposed SVPWM computation
method.
1) Region and Sector Identification: The complexity of
the SVPWM calculations is a result of the high number of
voltage levels particular as to the region identification. In the
sequel we proposed a general form for multilevel converter
region identification and sector identification. To determine the
triangular region in which a vector is located, it is essential
to determine the region borders that can be computed by the
straight lines xi ; for i=1:m+1; where m is the number of levels.
The loci for xi are shown in Fig.4-a. The value of xi can be
calculated as the intersection between the rotating vector V Fig. 5. Region identifier function, part 1
and the region borders as a function of the vector angle 𝜃. For
example, the locus of x1 is the straight line A1 – A2 . The loci 2) Time Interval Calculation: In this subsection, a general
values for the region boundaries of a five-level converter can formula is used to calculate the pulse-width time intervals for
be calculated by: any region within the hexagon. Assume a vector V located
in a specific region that has a boundary vectors Vx , Vy and
[x1 x3 x5 ] = K csc(𝜋/3 – 𝜃), [x2 x4 x6 ] = K csc(2𝜋/3 – 𝜃) Vz as shown in Fig. 4-b. The voltage-second relation during
√ a switching period Tc can be written as a function of the
; K = 3/2 [|OA1 ||OB1 ||OC1 |] (4) surrounding vectors and corresponding time durations as
A general form for the region boundaries for an m level follows [31]:
converter can be described by:
V.Tc = Vx .t1 + Vy .t2 + Vz .t3 (6)
[x1 x3 ......xm ] = K csc(𝜋/3 –𝜃) , [x2 x4 ......xm+1 ] = K csc(2𝜋/3 –𝜃)
√
3 where Tc = t1 + t2 + t3 = 1/2 Ts , and where Ts is the inverse of
;K = [1 2 ....m – 1] (5)
2(m – 1) the switching frequency. By analysing (6) in Cartesian form,

Fig. 6. Region identifier function, part 2
The first bullet is important to reduce the switching stress, and
hence the converter switching loss. This is obtained by keeping
two phases out of three at their previous switching states and
alter the third phase only. The second bullet is important to
cancel the even harmonic contents in the generated voltage
waveforms. The third bullet is the criterion to keep the dual
three-level T-type topology at a minimum switching stress and
to reduce the converter switching loss. By analysing the 729
switching states of this converter, it is concluded that there
are common switching states which can be used to keep one
converter is working at a common switching state, while the
other converter is varying its switching state. This is valid for
dual converters. Two regions switching patterns are show in
Fig. 8.

Vector C1 D2 C2 C1 C1 C2 D2 C1 Vector C4 D4 D5 C 4 C 4 D5 D4 C4
Intervals t1/2 t2 t3 t1/2 t1/2 t3 t2 t1/2 Intervals t1/2 t2 t3 t1/2 t1/2 t3 t2 t1/2
State 19 19 19 19 19 19 19 19 State 13 22 25 26 26 25 22 13
U
2 2 2 2 2 2 2 2
ωt U 1 2 2 2 2 2 2 1
V ωt
0 0 0 0 0 0 0 0 ωt V 1 1 2 2 2 2 1 1
ωt
W
0 0 0 0 0 0 0 0 ωt W 0 0 0 1 1 0 0 0 ωt
State 5 6 15 18 18 15 6 5 State 3 3 3 3 3 3 3 3
U' U'
2 2 2 2 2 2 2 2
0 0 1 1 1 1 0 0
ωt ωt
V' 2 2
V'
1 1 1 1 1 1
ωt
0 0 0 0 0 0 0 0 ωt
W' 2 2 2 2 2 2
W'
1 1 ωt 0 0 0 0 0 0 0 0
ωt
Tc Tc Tc Tc
Ts Ts
(a) (b)
Fig. 8. Pulses for (a) region no. 56 switching-pattern, (b)
region no. 61 during Ts time interval.

Fig. 7. Region identifier function, part 3

t1 , t2 , and t3 can be computed by:
⎡ ⎤ ⎡ ⎤–1⎡ ⎤ mented based on IXKR 40N60C discrete metal-oxide semi-
t1 ℝe{Vx } ℝe{Vy } ℝe{Vz } V cos(𝜃)Tc
⎣t2 ⎦ = ⎣𝕀m{Vx } 𝕀m{Vy } 𝕀m{Vz }⎦ ⎣ V sin(𝜃)Tc ⎦ (7)
t3 1 1 1 Tc
where ℝe and 𝕀m are the symbols of the real and imaginary
parts of a vector respectively. The time intervals t1 , t2 , t3 are
used to construct the switching pattern of a SVPWM. The
following subsection discusses how the switching-pattern is
constructed by using these time intervals.
3) Switching Pattern Design: In the switching pattern de-
sign for the dual T-type converter, there are four important
conditions to be taken into account during the switching state
selection:
∙ Only one phase is switched during state transition to
reduce the number of commutations,
∙ Construct a mirrored pattern over a switching period to
cancel the even harmonic content.
∙ Alter the switching state of one T-type converter only
during 1/6 of the fundamental electric period to reduce
the switching stress as well as switching loss.
IV. S IMULATION AND E XPERIMENTAL R ESULTS
To verify the theoretical study and the simulation results,
a test-setup for a dual three-level T-type converter is imple-
conductor field-effect transistors (MOSFETs). The converter is
supplied by isolated DC power supplies. The SVPWM modu-
lation technique is programmed on an FPGA type VERTIX2.
This digital controller is preferred here as the required I/O-
pins for PWM include 24 channels, while most DSPs have a
lower number of I/O-pins assigned for PWM channels and for
digital I/O channels. Moreover, the FPGA has the advantage
of performing parallel computations and sharing resources
which results in a high number of operations each clock cycle.
Within the FPGA program, the switching state selection is
implemented by using a look-up table.
In this test setup, the input and output voltages and currents
of the converter are measured. Differential voltage units are
designed and implemented to measure the voltage signals.
Furthermore, the current signals are measured by using LEM
modules current transducers. The power calculation is per-
formed by transmitting the measured signals to FPGA. By
using the Chipscope facility in the FPGA, the signals are
transmitted to a personal computer at sampling rate 333.35
KS/S (333,350 sample per second). It is observed that the
 (a) Mesaured voltage, 2.5 kHz (g) Simulated voltage, 2.5 kHz
implemented program on the FPGA takes around 100 ns to 10 10
find the vector location, calculate the pulse-width intervals and

% Hf

% Hf
5 5
to output the desired pattern.
The results for a dual three-level T-type converter can be 0 0
0 50 100 150 200 0 50 100 150 200
summarised as follows. The measured and simulated voltages harmonic order harmonic order
and currents are shown in Fig. 9. This figure shows that the (b) Mesaured current, 2.5 kHz (h) Simulated current, 2.5 kHz
2 1
current ripple decreases by increasing the switching frequency.

% Hf
% Hf
A harmonic analysis is performed on the full-load measured 1 0.5
voltages and currents and the harmonic analysis at 2.5 kHz, 0 0
5 kHz and 10 kHz switching frequencies are performed and 0 50 100 150 200 0 50 100 150 200
harmonic order harmonic order
summarised in Fig. 10 for both measured and simulated
(c) Mesaured voltage, 5 kHz (i) Simulated voltage, 5 kHz
waveforms as shown in Fig. 10- a,b,g,h, It has been observed
10 10
that the voltage harmonic orders around the order number 50

% Hf

% Hf
(corresponding to 𝜔=2.5 kHz) have relatively high amplitudes 5 5
(maximum amplitude is 5%) compared to the fundamental 0 0
voltage value. The corresponding current harmonic amplitude 0 50 100 150 200 0 50 100 150 200
harmonic order harmonic order
is 0.9% of the fundamental current value. For the harmonic (d) Mesaured current, 5 kHz (j) Simulated current, 5 kHz
1 1
orders greater than or equal 2𝜔, the current harmonic contents

% Hf
% Hf
are damped more due to the machine impedance. A similar 0.5 0.5
remark is observed for the harmonic spectra at 𝜔=5 kHz and 0 0
𝜔=10 kHz. A summary for the THD factors is listed in Table 0 50 100 150 200 0 50 100 150 200
harmonic order harmonic order
2. The results clarify that the THD factors for the measured
(e) Mesaured voltage, 10 kHz (k) Simulated voltage, 10 kHz
signals are well matched the simulation results and with a 10 10
small error. This error results from the semiconductor turn-on
% Hf

% Hf
5 5
and turn-off delay.
0 0
0 50 100 150 200 0 50 100 150 200
v
UU'
[V] 20i
U
[A] harmonic order harmonic order
(f) Mesaured current, 10 kHz (l) Simulated current, 10 kHz
(a) Measured, 2.5 kHz (a) Simulated, 2.5 kHz 1
200 1
200

% Hf
% Hf

0 0 0.5 0.5

-200 -200
0.02
0 0
0 0.01 t [s] 0.02 0 0.01 t [s] 50 100 150 200
0 0 50 100 150 200
(b) Measured, 5 kHz (b) Simulated, 5 kHz harmonic order harmonic order
200 200

0 0 Fig. 10. Dual T-type converter harmonic analysis for the

-200
0 0.01 t [s] 0.02
-200
0.02
measured and simulated voltage and current
0 0.01 t [s]
(c) Measured, 10 kHz (c) Simulated, 10 kHz
200 200

0 0 has been discussed and applied to the proposed topology.

-200 -200 The computation details of the SVPWM region identification,
0 0.01 t [s] 0.02 0 0.01 t [s] 0.02
Fig. 9. Measured voltage and current of a dual three-level interval calculations is simplified and discussed as well. The
T-type converter. SVPWM is implemented using an FPGA and consumes what
is less than 100 ns in order to deliver the pulses to the
converter. Moreover, according to the analysis, simulation and
Table 2: Dual T-type voltage and current THD factors at experimental results, the topology of dual T-type converter
different switching frequencies. yields more switching states which gives the ability to reduce
the switching stress and hence expected to reduce the converter
Switching frequency [kHz] 2.5 5 10
Measured voltage THD [%] 12.12 10.21 8.61 switching loss. The comparison between simulation results
Simulated voltage THD [%] 10.82 8.13 7.54 and experimental results validates the advanced topology as
Measured current THD [%] 0.94 0.45 0.35 well as the SVPWM calculating algorithm for the AC drive
Simulated current THD [%] 0.75 0.36 0.25 applications.

V. C ONCLUSION R EFERENCES

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