EECS240 – Spring 2013

Lecture 2: CMOS Technology and

Passive Devices

Lingkai Kong
EECS

Today’s Lecture
•  EE240 CMOS Technology

•  Passive devices
•  Motivation
•  Resistors
•  Capacitors
•  (Inductors)

•  Next time: MOS transistor modeling

1
EE240 Process
•  45nm 1P9M CMOS
•  Minimum channel length: 50nm
•  1 level of polysilicon
•  9 levels of metal (Cu)
•  1V supply
•  Models for this process not “real”
•  Other processes you might see
•  Shorter channel length (28nm / 1V, 20nm / 1V)
•  Bipolar, SiGe HBT
•  SOI
•  FinFET

Process Options
•  Available for many processes

•  Add features to “baseline process”

•  E.g.
•  Silicide block option
•  “High voltage” devices (2.5V & 3.3V, >10V)
•  Low VTH devices
•  Capacitor option (2 level poly, MIM)
•  …

2
CMOS Cross Section

Metal p- substrate p+ diffusion

Poly n- well n+ diffusion

Dimensions

³90nm
1.4nm

50nm

0.6mm

700mm

Drawing is not to scale!"

3
CMOS Process Overview

Why Talk About Passives?

4
Resistors

What are the Options in CMOS?

Metal p- substrate p+ diffusion

Poly n- well n+ diffusion

10

5
Resistors: Options
•  Poly resistors
•  Diffusion resistors
•  N-Well resistors
•  Metal resistors
•  Transistor as resistors
•  …

11

N-Well Resistor

12

6
N-Well Resistor?
•  How much does N-well resistor vary?

13

Silicide Block Option

•  Non-silicided layers have significantly
larger sheet resistance

Type Silicided Non-Silicided

N+ Poly ~5Ω ~100Ω
P+ Poly ~5Ω ~180Ω
N+ Diffusion ~5Ω ~50Ω
P+ Diffusion ~5Ω ~100Ω

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7
Poly Resistor

15

Diffusion Resistor
•  Applied voltage
p- substrate p+ diffusion modulates depletion
width
n- well n+ diffusion
(cross-section of
V1 V2 VB
conductive channel)
•  Well acts as a shield
R

V1 − V2
R=
I
⎡ ⎛ V + V2 ⎞⎤
≈ Ro ⎢1 + TC (T − 25o ) + VC (V1 − V2 ) + BC ⎜ 1 − VB ⎟⎥
⎣ ⎝ 2 ⎠⎦
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8
Temperature and Voltage Coefficient

Layer R/☐ [Ω/☐]

TC [ppm/oC] VC [ppm/V] BC [ppm/V]
@ T = 25 oC
N+ poly 100 -800 50 50
P+ poly 180 200 50 50
N+ diffusion 50 1500 500 -500
P+ diffusion 100 1600 500 -500
N-well 1000 -1500 20,000 30,000

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Compensation

18

9
Resistors: Specs
•  Resistivity – sheet resistance
•  Linearity (Voltage Dependency)
•  Temperature Coefficient
•  Parasitic
•  Variability and Matching
•  Stress
•  Electromigration (EM)
•  …

19

Systematic Variations from Layout

•  Example:

2R
?
•  Use unit element instead:


2R

R

20

10
Better Unit Element

21

Common Centroid and Dummies

Example: R1 : R2 = 1 : 2" gradient"
Dummy à"

0.5 * R2 + ΔR"

R1"

0.5 * R2 - ΔR"

Dummy à"

22

11
 Resistor Layout (cont.)
Serpentine layout for large values:"

Better layout (mitigates offset due to thermoelectric effects):"

See Hastings, “The art of analog layout,” Prentice Hall, 2001."

23

MOSFETs as Resistors
•  Triode region (“square
law”):
W ⎛ V ⎞
I D = µCox ⎜VGS − VTH − DS ⎟VDS for VGS − VTH > VDS
L ⎝ 2 ⎠
•  Small signal resistance:
1 ∂I W
= D = µCox (VGS − VTH − VDS )
R ∂VDS L
1
R≈ for VGS − VTH >> VDS
W
µCox (VGS − VTH )
L
•  Voltage coefficient:
1 ∂R 1
VC = =
R ∂VDS VGS − VTH − VDS
24

12
MOS Resistors
Example: R = 1 MΩ
•  Large R-values realizable in
small area
•  Very large voltage
R≈
W
1
coefficient
(VGS − VTH )
µCox
L •  Applications:
W 1
= •  MOSFET-C filters:
L µCox R (VGS − VTH )
(linearization)
1 1 Ref: Tsividis et al,
= =
µA 200
100 2 × 1MΩ × 2 V “Continuous-Time MOSFET-C
V
Filters in VLSI,” JSSC, pp.
15-30, Feb. 1986.
1
VC V
DS = 0V
=
VGS − VTH •  Biasing: (>1GΩ)
1
Ref: Geen et al, “Single-Chip
= = 0.5V −1 Surface-Micromachined
2V
Integrated Gyroscope with 50o/
hour Root Allen Variance,”
ISSCC, pp. 426-7, Feb. 2002. 25

Resistor Summary
•  No or limited support in standard CMOS
•  Costly: large area (compared to FETs)
•  Nonidealities:
•  Large run-to-run variations
•  Temperature coefficient
•  Voltage coefficients (nonlinear)

•  Avoid them when you can

•  Especially in critical areas, e.g.
•  Amplifier feedback networks
•  Electronic filters
•  A/D converters
•  We will get back to this point
26

13
 Capacitors

Capacitors
•  Simplest capacitor:

substrate"

•  What’s the problem with this?

28

14
Capacitors
•  “Improved” capacitor:

substrate"
•  Is this only 1 capacitor?

29

Capacitor Options

30

15
Capacitor Options
Type C [aF/µm2] VC [ppm/V] TC [ppm/
oC]

Gate 10,000 Huge Big

Poly-poly 1000 10 25
(option)
Metal-metal 50 20 30

Metal-substrate 30

Metal-poly 50

Poly-substrate 120

Junction caps ~ 1000 Big Big

31

MOS Capacitor

•  High non-linearity,
temperature coefficient

•  But, still useful in many

applications, e.g.:
•  (Miller)
compensation
capacitor
•  Bypass capacitor
(supply, bias)

32

16
Capacitor Layout

•  Unit elements"
•  Shields:"
•  Etching"
•  Fringing fields"
•  “Common-centroid”"
•  Wiring and interconnect
parasitics"

Ref.: Y. Tsividis, “Mixed Analog-Digital VLSI

Design and Technology,” McGraw-Hill,
1996."

33

MIM Capacitors
•  Some processes have MIM cap as add-on
option
•  Separation between metals is much thinner
•  Higher density

•  Used to be fairly popular

•  But not as popular now that have many metal layers
anyways

34

17
Capacitor Geometries
•  Horizontal parallel plate
•  Vertical parallel plate
•  Combinations

Ref: R. Aparicio and A. Hajimiri, “Capacity Limits and Matching

Properties of Integrated Capacitors,” JSSC March 2002, pp.
384-393.

35

“MOM” Capacitors

•  Metal-Oxide-Metal capacitor. Free with modern CMOS.

•  Use lateral flux (~Lmin) and multiple metal layers to realize
high capacitance values

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18
MOM Capacitor Cross Section

•  Use a wall of metal and

vias to realize high
density

•  More layers – higher

density
•  May want to chop off lower
layers to reduce Cbot

•  Reasonably good
matching and accuracy
37

Distributed Effects
•  Can model IC resistors
as distributed RC
circuits.

•  Could use transmission

line analysis to find
equivalent 2-port
parameters.

•  Inductance negligible
for small IC structures
up to ~10GHz.
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19
Effective Resistance

•  High frequency resistance depends on W, e.g.:

•  W=1µ 10kΩ resistor works fine at 1GHz
•  W=5µ 10kΩ resistor drops to 5kΩ at 1 GHz

•  May need distributed model for accurate freq

response
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Capacitor Q

•  Current density drops as you go farther

from contact edge…

40

20
Double Contact Strucutre

•  If contact on both edges,

•  R drops 4X
•  Can be a good idea even if not hitting distributed
effects

41

Inductors

21
Passives: Inductors

43

What About Inductors?

•  Mostly not used in analog/mixed-signal design

•  Usually too big
•  More of a pain to model than R’s and C’s
•  But they do occasionally get used
•  Example inductor app.: shunt peaking
•  Can boost bandwidth by up to 85%!
•  Q not that important (L in series with R)
•  But frequency response may not be flat
44

22
Spiral Inductors

•  Used widely in RF circuits for small L

(~1-10nH).
•  Use top metal for Q and high self resonance
frequencies.
•  Very good matching and accuracy – if you model
them right 45

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