Parasitic Inductance Effect on Switching Losses for

a High Frequency Dc-Dc Converter

Thomas Meade†, Dara O’Sullivan∗ , Raymond Foley∗, Cristian Achimescu†, Michael Egan∗ and Paul McCloskey†
∗ Department of Electrical Engineering,
University College Cork,
Cork, Ireland
† Tyndall National Institute,

Lee Maltings,
Cork, Ireland
Email: paul.mccloskey@tyndall.ie

Abstract— This work examines the impact of packaging para- parallel wires is given in (2) for l > d, where d is the
sitics on the efficiency of a synchronous DC-DC buck converter. separation distance and l is the length.
An anaytical model of the losses in the converter is developed
and this is compared to practical results at switching frequencies   
in the range of 1-2 MHz. The effect that the packaging parasitic µ0 l 2l w+t
inductance has on efficiency is highlighted by predicting the
Lself = ln + 0.5 + 0.22 (1)
2π w+t l
expected losses from a converter with optimised packaging  
parasitics. µ0 l 2l d
Lmutual = ln − 1 + (2)
2π d l
I. I NTRODUCTION
It follows from (1), that to minimise the parasitic inductance
The steady decrease in IC system voltages along with the value, the length through which the current passes must be
sharp rise in power requirements result in significant current minimised and the cross sectional area through which current
being delivered from the power supply [1]. This trend coupled flows maximised.
with the increase in switching speeds of power semiconductor Simulations were carried out in order to determine whether
devices, due to the technology transfer from bipolar to MOS a strategy of placing wire-bonds in parallel was more effective
based devices and the reduction in Rds(on) means that the at reducing the parasitic inductance value as opposed to using
effect of packaging parasitics on power converter performance a block of copper occupying the same total cross sectional area
is increasingly significant. As switching speeds increase, the of the wire-bonds. It was found that while placing wire-bonds
limiting factor in power device performance is shifting from in parallel reduces the overall self inductance, the effect of
the silicon characteristics to the path inductance. This paper mutual inductance between the wires results in a higher overall
uses an analytical approach to model converter losses and inductance. The formula for calculating the overall inductance
efficiency. The effect of packaging inductance is included in for two wire-bonds in parallel with current flowing in the same
the model by incorporating inductance values extracted from direction is
the packaging geometry using Ansoft Q3D. The analytical
Lself + Lmutual
model of a discrete component converter, in the frequency Ltotal = . (3)
range of 1-2 MHz, is verified with practical efficiency results. 2
The model is then applied to predict the efficiency of a 3 MHz, In summary, packaging inductance is minimised by min-
1V, 20A converter using three different packaging techniques. imising current path length, maximising current path cross-
One technique is to use discrete devices on PCB, the next sectional area, and, where possible using a solid path, as
technique is to use an integrated power-train incorporating opposed to parallel paths. Such considerations have led to
wire-bonds and the final technique is to use an innovative innovative packaging techniques in power MOSFET design,
wire-bond-free power train. such as the DirectFET from International Rectifier [3].
III. MOSFET S WITCHING E QUATIONS
II. PACKAGING I NDUCTANCE
The circuit diagram of a synchronous buck converter with
The self inductance of a wire with rectangular cross section the main power loop parasitics included is shown in Fig.1. It is
can be derived using electromagnetic field theory and ‘geom- important to note that the loop includes the input decoupling
etry mean distance’ as in [2]. The equation for self inductance capacitor and its associated parasitic inductance. The parasitic
is given in (1), where l is the length of the wires, w and t inductances shown are those which contribute to the switching
are the width and thickness of the rectangular cross section, losses of the converter. In recent integrated converter power
respectively. The equation for mutual inductance between two trains [4], the inductances LS1 and LS2 have been effectively

978-1-4244-1874-9/08/$25.00 ©2008 IEEE 3

 Io
Ld1 Ls1 Ld2 IDS
Current
&
Voltage
VD High Side Ld3
Driver
+ Io
- Cin Low Side Cout Load
Driver VDS
Ld4 Ls2 VGS

VGH

Fig. 1. Buck converter circuit with included parasitic inductance t

t1 t2 t3 t4
Time Time Time Time
Interval 1 Interval 2 Interval 3 Interval 4

LD
Fig. 3. Current and voltage waveforms during MOSFET turn-on

CGD
time interval ends when the gate to source voltage equals the
RG + V threshold voltage.
CDS D
-  
−t
CGS RG (CGD +CGS )
VGS (t) = VGH × 1 − e (6)
VGH

LS 2) Time interval 2: In this time interval VGS (t) is greater

than Vth . Drain current, IDS (t) now rises. The change in
switching loop current induces a voltage across the parasitic
inductance and causes the drain to source voltage, VDS (t)
(which in idealised switching waveforms [8] remains constant)
to fall. Writing equations around the switching loop as in [5]
Fig. 2. Equivalent circuit for the main transition period
yields:

δ 2 VGS (t) dVGS (t)

eliminated from the gate drive loop by connecting the source VGS (t) = A +B + VGS (t) (7)
dt2 dt
terminal of the MOSFET directly to the driver inside an
where
integrated driver-MOSFET package, thus reducing the switch-
A = RG gf s CGD (LD + LS ) (8)
ing losses. In the analytical model developed, this source
inductance is included in the analysis but can be given a zero B = RG (CGD + CGS ) + LS gf s . (9)
value in the drive loop equations as the application requires.
In order to examine the effect of the parasitic inductances on Solving (7) and piecing it together with the equation for
the switching losses of the high side MOSFET, the parasitic VGS (t) in time interval 1 [Eqn. (6)], yields:
inductances are grouped into two lumped values, with −(t−t1 )
VGS (t) = VB1 − VB2 e T1
LD = Ld1 + Ld2 + Ld3 + Ld4 + Ls2 (4) 
sin ω1 (t − t1 )

× cos ω1 (t − t1 ) + if 4A − B 2 ≥ 0
and ω1 T 1
LS = LS1 . (5) (10)

Each switching sequence, either from the off to the on state and
or vice versa is divided into a number of separate intervals, VB2
VGS (t) = VB1 −
for which different conditions and constraints apply [5] [6]. T 2 − T3
The non-linear characteristics of the internal MOSFET capac-
 
−(t−t1 ) −(t−t1 )

itances [7] are included in the analysis. × T2 e T2

− T3 e T3
if 4A − B 2 < 0 (11)

A. Upper MOSFET Turn On Waveforms where

4A − B 2
Fig. 3 shows current and voltage waveforms during the turn ω12 = , (12)
4A2
on of the upper MOSFET. This has four distinct time intervals,
described below. 2A
T1 = , (13)
1) Time interval 1: In this time period the gate voltage B
rises to its threshold value. No drain current flows as long as 2A
T2 = √ , (14)
the gate voltage is less than the threshold voltage Vth . The B + B 2 − 4A

4
and
2A
T3 = √ . (15) Current
B − B 2 − 4A &
IDS
Voltage
VGH is the applied gate voltage and gf s is the forward
transconductance of the MOSFET. During turn-on
Vpeak
VB1 = VGH (16) VDS
and
VGS
VB2 = VGH − Vth , (17)

while during the turn-off transient

t
t1 t2 t3 t4
VB1 = 0 (18) Time Time Time Time
Interval 1 Interval 2 Interval 3 Interval 4
and
Io Fig. 4. Current and voltage waveforms during MOSFET turn-off
VB2 = − (19)
gf s + Vth
where I0 is the full load current. IDS (t) and VDS (t) of the
MOSFET for this time period can be calculated using (20) and  
Ls
(21) based on VGS (t). This time interval comes to an end at VGS (t) = VGH − VGS (t2 ) − VD
L + LS
time t2 when IDS (t) rises to I0 or VDS (t) falls to I0 RDSon ,  −(t−t2 )
D (25)
whichever occurs first. × 1 − e RG (CGD +CGS ) + VGS (t2 )

IDS (t) = gf s (VGS (t) − Vth ) (20) 4) Time interval 4: In this time interval the gate to source
voltage completes its charge to the level of applied drive
dIDS (t) voltage VGH .
VDS (t) = VD − (LD + LS ) (21)
dt VGS (t) = (VGH − VGS (t3 ))
3) Time interval 3: In this time interval either VDS (t)
 −(t−t3 )

RG (CGD +CGS )
completes its fall or IDS (t) completes its rise. Consider first × 1−e + VGS (t3 ) (26)
the drain voltage completing its fall, IDS (t) having risen to
I0 . Since the drain current is constant, VGS (t) must also be B. Upper MOSFET Turn Off Waveforms
constant:
A similar analysis may be performed during the turn-off
I0 transition of the upper MOSFET, using the waveforms shown
VGS (t) = Vth + . (22) in Fig. 4.
gf s
1) Time interval 1: In time interval 1, the gate source
The drain to source voltage in this time period is given by: voltage, VGS (t) falls at a rate determined by the time constant
RG (CGD + CGS ). There is no change to the drain current
VGH − (Vth + gIf0s )
!
VDS (t) = VDS (t2 ) − (t − t2 ) (23) or drain to source voltage until the value of VGS (t) falls to
RG CGD VGS(th) + I0 /gf s . This is the gate voltage needed to sustain
drain current I0 . The gate to source voltage during this period
where VDS (t2 ) is the drain to source voltage at the start of is given by:
this time period, and t2 is the time at which IDS rises to full
−t
load current. The time period ends at time t3 when VDS (t) VGS (t) = VGH e RG (CGS +CGD ) . (27)
completes its fall to I0 RDSon .
Consider now the situation where the current completes its rise This interval ends at time t1 when VGS (t) falls to a value of
during the third time interval,VDS (t) having already completed VGS(th) + gIf0s .
its fall. IDS (t) and VGS (t) are given by: 2) Time Interval 2: In this time period the drain to source
  voltage rises to VD , the applied dc input voltage. The drain
VD current remains constant at I0 and the gate to source voltage
IDS (t) = IDS (t2 ) + (t − t2 ) (24)
LD + LS stays constant at VGS(th) + gIf0s . The drain to source voltage
where VD is the applied dc input voltage and IDS (t2 ) is the during this time period rises according to the following equa-
drain to source current at the start of this time period, and t2 tion:
gf s VGS(th) + I0
 
in this case is the time at which the drain voltage drops to
VDS (t) = (t − t1 ). (28)
I0 RDSon . (1 + gf s RG )CGD + CDS

5
This time period comes to an end at time t2 when VDS (t) IV. S OURCES OF P OWER L OSS
rises to VD .
3) Time Interval 3: As with the second time interval during A. Crossover Switching Loss
turn-on, both the drain current and drain voltage change. A The turn-on switching loss can be calculated using the turn-
change in the drain current produces a change in the voltage on switching waveforms derived in Section III
across the parasitic inductances LS and LD . A current flow
through the capacitance CGD is produced. This current flow Z t3
restrains the rate of decrease of the gate voltage, which in Pon(loss) = FSW VDS (t) · IDS (t)dt (37)
turn restrains the original rate of change of drain current. The t1
gate to source voltage during this period is given by (29) or
where FSW is the switching frequency of the converter.
(30). During this time interval IDS (t) falls from I0 to zero
Similarly, the turn-off switching losses are calculated from
according to (20) and VDS (t) changes in accordance with (21).
This time interval comes to an end at time t3 when VGS (t) Z t3
falls to the threshold voltage VGS(th) . Pof f (loss) = FSW VDS (t) · IDS (t)dt. (38)
t1
−(t−t2 )
VGS (t) = VB1 − VB2 e T1 B. Conduction Loss
 
sin ω1 (t − t2 )
× cos ω1 (t − t2 ) + if 4A − B 2 ≥ 0 The upper MOSFET conduction loss is given by:
ω1 T 1
(29)
∆I02
 
2
Pcond−upper = I0 + DRDS(on−upper) (39)
12
VB2
VGS (t) = VB1 −
 T2 − T3  where ∆I0 is the ripple of the load current I0 , D is the duty
−(t−t2 ) −(t−t2 ) cycle and RDS(on−upper) is the is the on-state resistance of
× T2 e T2
− T3 e T3
if 4A − B 2 < 0 (30)
the top switch.
The lower MOSFET conduction loss is given by:
T1 , T2 , T3 and ω1 are as given previously for turn-on interval
2. Also
∆I02
 
VB1 = 0 (31) 2
Pcond−lower = I0 + (1 − D)RDS(on−lower) . (40)
12
and
C. Gate Drive Loss
VB2 = −(I0 /gf s + VGS(th) ). (32)
Most of the switch losses associated with charging and
4) Time interval 4: At the end of time interval 3, the drain discharging the MOSFET gate are dissipated in the driver IC
current has fallen to zero, but the drain voltage VDS (t3 ) is since the source and sink resistances of the driver IC are much
greater than the circuit voltage VIN . The drain capacitance greater than the MOSFET’s internal gate resistance. The gate
CDS “rings” with the stray circuit inductance. The stray circuit drive loss of the upper MOSFET is given, as in [9], by:
resistance Rl damps the oscillation. The drain voltage is given
by: PG−upper = Qg VGH F sw. (41)
−(t−t3 )
VDS (t) = VIN + (VDS (t3 ) − VIN )e T4
cos(ω4 (t − t3 )) A similar equation holds for the gate drive of the lower
(33) MOSFET.
where
2LD D. Reverse Recovery and Ringing Turn On
T4 = (34)
Rl
The reverse recovery and ringing power loss is calculated
and as in [7], via
p
2 R2
4LD CDS − CDS  
ω4 = l
. (35) 1
2LD CDS PRRR(on) = FSW VD QRR(lower) + Qoss(lower) VD
2
(42)
The gate voltage decays to zero with time constant RG (CGD +
where QRR(lower) is the reverse recovery charge for the lower
CGS ). The gate to source voltage is given by:
MOSFET, which is dependant on the loop inductance [7], and
−(t−t3 ) Qoss(lower) is the charge stored in CGD + CDS of the lower
VGS (t) = VGS (t3 )e RG (CGD +CGS ) . (36) MOSFET.

6
 v"
2
#
∆ISW
u
(pp)
u
IIN (cap)RMS = t (I − IIN (avg) )2 + 2
· D + IIN
SW (pk)
12 (avg) · (1 − D) (46)

E. Reverse Recovery and Ringing Energy Turn Off 4.0 534 kHz
3.5 1.5 MHz
The reverse recovery ringing power loss during MOSFET 1.9 MHz
3.0

Power Loss (W)

turn-off is given by
2.5
1
2.0
PRRR(of f ) = FSW Qoss(V peak) Vpeak − Qoss(VD ) VD
2 1.5
(43)
1.0
where Qoss(V peak) is the charge stored in CGS + CGD of 0.5
the upper MOSFET when the voltage reaches its peak value, 0.0
Vpeak . Qoss(VD ) is the charge stored in CGS + CGD of the

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or ff
W Los
on
Co g T O
G duc n O

P
Ri uct Lo

G Dri Lo

Lo
ct Po
ci
D Up

ut pa c
upper MOSFET when the voltage reaches its steady state

pa
pu L
an on tion
value, VD .

C uc

du
r

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in
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d

In
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n
at
at
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F. Diode Conduction Loss

S
e we OS

io
Lo r M

ry
Re r
ve

dy
e
The average power loss in the synchronous diode is given

pp

Bo
U
by:

Pdiode = Vf r I0−v Td1 FSW + Vf r I0−p Td2 FSW (44)
where Vf r is the forward voltage drop, Td1 and Td2 are the
dead-times when the diode is conducting, I0−v is the valley
value of the load current I0 and I0−p is the peak value of the
load current I0 .
G. Other Losses
Losses in the input and output capacitors as well as the
power inductor must also be considered to accurately model
the overall converter loss. The input capacitor power loss can
be calculated from
2 LS =1.65 nH. Oscilliscope plots of VGS and VDS during the
PIN (cap) = IIN (cap)RMS Resr−IN (cap) (45)
where the rms capacitor current, IIN (cap)RMS , is calculated
from (46) above and
Vout Iout
IIN (avg) = . (47)
ηVIN
ISW and η are the top-switch current and converter power-
train efficiency respectively. The ac component of the load
current generates a power loss in the output capacitors. This
is given by
2 Having validated the analytical model in a discrete-
POUT (cap) = ∆I0(RMS) Resr−OUT (cap) (48)
The power inductor losses comprise of hysteresis and eddy-
current losses in the core and winding resistive losses. Total
losses are calculated using a vendor-specified procedure [10]
for the inductor used in the design.
Fig. 5 shows the theoretical loss breakdown of the designed
converter operating at three different frequencies. The most
notable difference between the loss breakdowns as the fre-
quency is increased is the change in the switching loss of the
converter, and in particular, the upper MOSFET turn-off power
loss, Pof f .
rs
ve
Re
Fig. 5. Theoretical breakdown of power-converter losses at three different
frequencies
V. P RACTICAL D C - DC C ONVERTER
A practical DC-DC converter as shown in Fig. 8 was built in
order to verify the analytical power loss equations. The output
voltage is 1V, the input voltage is 12V and the inductor value
is 300 nH. The parasitic inductances were extracted from the
layout diagram, shown in Fig. 9, using the software package
Ansoft Q3D. The extracted inductances are LD =6.03 nH and
MOSFET turn-on and turn-off transitions with a 20 A output
current are shown in Figs. 6 and 7 respectively.
Graphs of the efficiency versus load current for three
different switching frequencies are shown in Fig. 10. These
results show good correlation between the analytical model
that has been developed (theoretical values) and the measured
practical values.
A. Effect of Parasitic Inductance on a 3 MHz converter
component converter, it is possible to utilise the model for
predicting the converter efficiency at higher switching frequen-
cies, and to examine the effect of using alternative packaging
technologies at these frequencies. A similar power converter
is modelled at a switching frequency of 3 MHz, with packag-
ing parasitic inductances corresponding to (a) discrete power
devices, (b) currently available wire-bonded power trains, and
(c) an innovative wire-bond-free packaging technique using
copper as the interconnect medium. A comparison between the
switching losses of the three converters is shown in Fig. 11. As
is evident from Fig. 11, a higher parasitic inductance slightly
reduces the turn-on switching losses (with LS = 0), but

7
 Fig. 6. MOSFET turn on voltage waveforms

Fig. 8. Buck converter as implemented

Fig. 7. MOSFET turn off voltage waveforms

Fig. 9. Layout diagram for the power stage of the converter

significantly increases the turn-off loss. The overall effect of
the changes in parasitic inductance on converter efficiency can
be seen in Fig. 12. Clearly, currently available wire-bonded
co-packaged power trains offer a significant advantage—in
terms of efficiency at a 3MHz switching frequency—over
designs using discrete components; however, the residual
parasitic inductance of even this approach limits the overall
converter efficiency. The plot predicts that the most appropriate
packaging strategy for a power converter at this frequency is
one which uses a wire-bond-free approach.
parasitic inductance on the switching losses has been examined
in detail. A loss model for a high frequency converter is
proposed in order to outline the impact of parasitic inductance
on efficiency and to highlight the deficiencies of using discrete
devices and a layout which are not optimised for minimum
parasitic inductance. The guidelines needed to reduce the
critical parasitic inductance values are also presented.

VI. C ONCLUSION
This paper has presented an analytical model for a buck
converter which has been verified experimentally. The effect of

8
 85
80
75 10

Power Loss (W)

70 8
Efficiency (%)

65
6
60
55
4
50 2 Discrete Power
Theoretical
Wire-bonded Devices
45
Practical 0 Power Train
40
P off Wire-bond-fre
0
P on e Packaging
0 2 4 6 8 10 12 14 16 18 20 22 24
Io (A)
Fig. 11. The effect of parasitic inductance on switching losses at 3MHz with
(a) FSW =534 kHz Io = 20 A
85
80
80
75
75
70
Efficiency (%)

65 70
60
65

Efficiency (%)
55
50 60
Theoretical
45
Practical 55
40
0
0 2 4 6 8 10 12 14 16 18 20 22 24 50
Io (A) Discrete Power Devices
45
Wire-bonded Power Train
(b) FSW =1.5 MHz Wire-bond-free Packaging
85
40
0
80 10 12 14 16 18 20 22 24 26 28 30
75
Io (A)
70
Efficiency (%)

65
Fig. 12. Efficiency comparison at 3 MHz for three packaging techniques
60
55
50
circuit simulation,” in Proc. Custom Int. Circuits Conf., May 2000, pp.
Theoretical
45
Practical
487–490.
40 [3] A. Sawle, M. Standing, T. Sammon, and A. Woodworth. Directfet -
0 a proprietary new source mounted power package for board mounted
0 2 4 6 8 10 12 14 16 18 20 22 24 power. International Rectifier. Surrey, England. [Online]. Available:
Io (A) http://www.irf.com/technical-info/whitepaper/directfet.pdf
[4] Philips PIP212-12M datasheet. [Online]. Available: http://www.nxp.
(c) FSW =1.9MHz com/acrobat/datasheets/PIP212-12M 4.pdf
[5] Y. Xiao, H. Shah, T. Chow, and R. Gutmann, “Analytical modeling
and experimental evaluation of interconnect parasitic inductance on
Fig. 10. Efficiency vs. load current MOSFET switching characteristics,” 2004, pp. 516–521.
[6] “Hexfet power MOSFET designer’s manual,” International Rectifier, ch.
11.
[7] Y. Rena, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of power
R EFERENCES MOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310–319,
Mar. 2006.
[8] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics
[1] D. Staffiere and M. Mankikar, “Power technology roadmap for IT power Converters, Applications and Design. John Wiley and Sons, ch. 22.
supplies,” in Proc. IEEE Appl. Power Electron. Conf., Mar. 2001, pp. [9] L. Balogh, “A design and application guide for high speed power
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