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-- Nombre:
-- Documento:
-- Fecha:
-- Proyecto:
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity design is
Port ( <entrada1> : in STD_LOGIC;
<entrada2> : in STD_LOGIC_VECTOR (3 downto 0);
<salida1> : out STD_LOGIC;
<salida2> : out STD_LOGIC_VECTOR (3 downto 0)
);
end design ;

architecture Behavioral of design is

component <NOMBRE>
Port ( <entrada1> : in STD_LOGIC;
<entrada2> : in STD_LOGIC_VECTOR (3 downto 0);
<salida1> : out STD_LOGIC;
<salida2> : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

component <NOMBRE>
Port ( <entrada1> : in STD_LOGIC;
<entrada2> : in STD_LOGIC_VECTOR (3 downto 0);
<salida1> : out STD_LOGIC;
<salida2> : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

-- Señales internas
signal <entrada1> : STD_LOGIC:= '0';
signal <entrada2> : STD_LOGIC_VECTOR (3 downto 0):= (others => '0');

begin

UO: <NOMBRE> port map (

entrada1 => entrada1,
entrada2 => entrada2,
salida1=> salida1
);

U1: <NOMBRE> port map (

entrada1 => entrada1,
entrada2 => entrada2,
salida1=> salida1
);

end Behavioral;