Symmetrical and Asymmetrical Conventional

Cascaded Multilevel Inverter With SPWM

Technique
Lipika Nanda Chitralekha Jena Sarita Samal
School of Electrical Engineering School of Electrical Engineering School of Electrical Engineering
KIIT University, Bhubaneswar KIIT University, Bhubaneswar KIIT University, Bhubaneswar
Odisha,INDIA Odisha,INDIA Odisha,INDIA
lnandafel@kiit.ac.in Chitralekha.jenafel@kiit.ac.in ssamalfel@kiit.ac.in
 Abstract - The classical topologies do solve the
challenges encountered with two-level conventional II.SYMMETRICAL CONFIGURATION OF
inverter. As the output voltage level increases, the AC CASCADED MLI
output waveform is better with less THD. However
cascaded multilevel inverter(CMLI) among all the On the basis of voltage magnitude DC source, CHB
classical topologies, is being preferred due to its is classified as symmetric and asymmetric
simple modularity and absence of diodes and configuration. In symmetric configuration, the
capacitors. CHB generates a good sinusoidal output magnitudes of DC sources are equal (V1 = V2 = V3)
waveform with little total harmonic distortion. configuration. CHB produces higher number of
Key words - Symmetrical, Asymmetrical, THD, voltage level as compared with symmetric
SPWM,Switching states configuration for same number of power switches.
I. INTRODUCTION The number of level generation depends on the
Multilevel Inverter is a power converter that emerged number of DC sources and switches placed in
onto the scene in the mid-1970s. Multilevel inverter was a cascaded multilevel inverter topology . If N is the
word synonymous with the early three-level converter. required level generation then 2(N-1) is the number
Resultant of its benefits, numerous topologies have arisen of power switches required and (N-1)/2 is the
ever since. Its introduction came about as the need for high number of isolated DC supply for cascaded
multilevel inverter. For example, to generate 5-level,
power and medium voltage by industrial applications grew.
2 bridges, i.e., 8 switches and 2 DC supply is
Connecting a single switch onto a medium voltage grid is
required. Similarly to generate 7-level, 12 switches,
not advisable; this is where multilevel inverter comes into i.e., 3 bridges and 3 separate DC sources are
play. With the numerous topologies developed, the concept required.
of MLI remains, synthesizing voltage waveforms in the As in symmetrical configuration all the DC sources
form of horizontally adding of the levels to give a higher are having the same values to generate first level V1
output waveform with better power quality. Quality of the must be connected to load. To obtain second level V1
output waveform improves as the number of level increases. and V2 both are connected to load. The working
principle of each topology is tabulated by switching
MLIs can be applicable almost everywhere now, in terms of schemes of the inverter. V1 = V2 = Vdc. In Figure 1,
industries. Adjustable speed drive motors are benefitting V1 = V2 has been considered to achieve 5-level
from MLIs, lesser faults. All various types of MLIs are
applicable as reactive power compensator and SVG.
generation and its switching states is presented in Table I. bridge configuration

Fig. 2. Three bridge configuration

TABLE I
SWITCHING STATES OF 5-LEVEL

Output voltage (V) Conducting switch

Vdc S1 , S 2 , S 6 , S 8 Fig.
1.
2Vdc S1 , S 2 , S 6 , S 5
Two
0 S4 , S 2 , S 6 , S 8

-Vdc S3 , S 4 , S 5 , S 7

-2Vdc S3 , S 4 , S 7 , S 8
In Fig. 1., V1= V2 = V3 has been considered to achieve 7-
level generation and its switching states is presented in
Table II.
 Output voltage (V) Conducting switch
Vdc S1 , S 2 , S 6 , S 8
2Vdc S5 , S 6 , S 4 , S 2
3Vdc S1 , S 2 , S 6 , S 5
0 S4 , S 2 , S 6 , S 8
-Vdc S3 , S 4 , S 5 , S 7
TABLE II -2Vdc S7 , S 8 , S 1 , S 3
-3Vdc S7 , S 8 , S 4 , S 3
Output voltage (V) Conducting switch
Vdc S1 , S 2 , S 6 , S 8 In Table II, V1 = Vdc and V2 = 2Vdc ( i.e., binary
2Vdc S5 , S 4 , S 6 , S 3 configuration) have been considered to achieve the 7-
3Vdc S5 , S 4 , S 6 , S 2 level generation. In this configuration maximum positive
4Vdc S1 , S 2 , S 6 , S 5 voltage obtained is 3Vdc and maximum negative voltage
0 S4 , S 2 , S 6 , S 8 is -3Vdc. Hence peak to peak load voltage is 6Vdc
-Vdc S3 , S 4 , S 5 , S 7
-2Vdc S1 , S 2 , S 7 , S 8
-3Vdc S7 , S 8 , S 3 , S 1
TABLE IV
-4Vdc S3 , S 4 , S 7 , S 8 9-LEVEL GENERATION BY TRINARY CONFIGURATION
SWITCHING STATES OF 7-LEVEL CHB
MLI
Output voltage Conducting switch
Vdc S1, S2, S6, S8, S10, S12
2Vdc S1, S2, S6, S5, S10, S12
3Vdc S1, S2, S6, S5, S10, S9
0 S4, S2, S6, S8, S10, S12
-Vdc S3, S4, S5, S7, S9, S11
-2Vdc S3, S4, S7, S8, S9, S11
-3dc S3, S4, S7, S8, S11, S12

III CONCEPT OF ASYMMETRICAL In Table IV , V1=Vdc and V2=3Vdc (i.e., trinary

CONFIGURATION OF CASCADED MLI configuration) have been considered to achieve the 9-
Two popular asymmetric source configurations level generation. In this configuration maximum
employed in multilevel inverters are, positive voltage obtained is 4Vdc and maximum
(i) Binary configuration: It consists of DC negative voltage is -4Vdc. Hence peak to peak load
sources having a geometric progression with a voltage is 8Vdc.
factor of 2 i.e., Table I also presents that in symmetrical
with N number of DC sources. For example for j = Configuration for two bridge configuration (i.e.,
1, Vdc1 = Vdc and for j=2, Vdc2= 2Vdc. Figure 1) produces 5-level. Table II signifies
Peak value of the output waveform can be asymmetrical configuration (i.e., binary configuration)
obtained by Vmax=Vdc1+Vdc2+…..+Vdc,j for two bridge configuration produces 7-level output
(ii)Trinary configuration: It consists of DC sources and Table IV refers to asymmetrical configuration
having a geometric progression with a factor of 3 i.e., (i.e., trinary configuration) for two bridge
configuration produces 9-level output. 15- level
with N number of DC sources. For example
generation by binary configuration has been achieved
for j = 1,Vdc1 = Vdc and for j=2 , Vdc2 = 3Vdc.
by 3 bridge configuration ( i.e., figure 2). Here
Peak value of the output waveform can be
V1=Vdc, V2 = 2Vdc, V3 = 4Vdc
obtained by Vmax=Vdc1+Vdc2+…..+Vdcj
Tables 3, 4 and 5 present binary and trinary TABLE V
operation of cascaded multilevel inverters with their 15-LEVEL GENERATION BY BINARY CONFIGURATION
switching states of the inverters.
TABLE III
7-LEVEL GENERATION BY BINARY CONFIGURATION
 Fig. 3. APOD PWM techniques
IV MODULATION TECHNIQUES
Phase shifted and level shifted modulations
schemes are the major classifications of carrier
based modulation for multilevel inverters. THD of
phase shifted modulation technique is more than
level shifted modulation techniques. Hence level
shifted PWM techniques are being chosen. For N
number of levels (N-1) of triangular carrier signals
are being taken out. All of them are having same
frequency and amplitude.
They are (i) Alternative phase opposition Fig. 4. IPD PWM techniques
disposition (ii) Phase opposition disposition and (iii)
Phase disposition. All the symmetrical and IV SIMULATION RESULT ANALYSIS
asymmetrical topologies are simulated using PD
PWM technique as it has the low harmonic Simulations are carried out in MATLAB-14
distortion. environment using resistive load. Both symmetrical
and asymmetrical configurations are tested and results
are tabulated in Table 6.
(i) Symmetrical configuration
(a) 5-Level generation
Symmetrical configuration for 5-level generation is
carried out at 10 kHz with load resistance of R = 20 Ω.
Output voltage with its FFT analysis is displayed in
Figure 5.

Output voltage (V) Conducting switch

Vdc S1, S2, S6, S8, S12, S10
2Vdc S5, S6, S4, S2, S12, S10
3Vdc S1, S2, S6, S5, S12, S10
4Vdc S4, S2, S6, S8, S9, S10
5Vdc S1, S2, S6, S8, S9, S10
6Vdc S4, S2, S6, S5, S9, S10
7Vdc S1, S2, S5, S6, S9, S10
0 S4, S2, S6, S8, S12, S10
-Vdc S4, S3, S5, S7, S9, S11
-2Vdc S1, S3, S7, S8, S9, S11
-3Vdc S3, S4, S7, S8, S11, S9
-4Vdc S1, S3, S5, S7, S12 , S11
-5Vdc S3, S4, S5, S7, S12, S11
-6Vdc S1, S3, S7, S8, S12, S11
-7Vdc S4, S3, S7, S8, S12, S11
 At 10 kHz output voltage and its THD
Fig.5 Load voltage and its FFT analysis(5 level)

analysis are obtained with resistive load of R

= 20 Ω. Three bridge configurations are
simulated with equal values of source
voltages and results are presented in Figure 6
(b) 7 Level generation
Fig.8(a). Load voltage and its FFT analysis(7
level)
It signifies that output voltage = 295 V and
THD = 18.14% in binary asymmetrical
configuration.

(b) 9-level generation

At 10 kHz output voltage and its THD analysis
are obtained with resistive load of R = 20 Ω.
Two bridge configuration simulated with
trinary valuesof source voltages V1 = 100 V,
V2 = 300V

Fig. 6. Load voltage and its FFT (7

evel)
It indicates the output voltage = 295 V,
THD = 18.14%, and V1 = V2 = V3 = 100
V
(ii)Asymmetrical configuration:
(a) 7-level generation
In asymmetrical configuration, the binary and
trinary configurations are simulated inMATLAB.
At 10 kHz output voltage and its THD analysis are Fig. 8(b). Load voltage and its FFT analysis(9
obtained with resistive load of R = 20 Ω. Two level)
bridge configuration is simulated with binary values Here output voltage = 399.4 V and
of source voltages V1 = 100 V, V2 = 200 V. THD=15.70% in trinary asymmetrical
configuration.
 (c) 15-level generation level 4
At 10 kHz, output voltage and its THD 15- 700. 7.39
analysis are obtained with resistive load of R level 2
= 20 Ω. Two bridge configuration simulated Both the Tables VI and VII present, the
with binary values of source voltages V1 = reduction of THD with increase in level.
100 V, V2 = 200 V, V3 =400 V.
VI CONCLUSION
From the simulation result, it is concluded
that by taking different switching states of
inverter output levels of asymmetrical MLI
can be increased without any increase in
components. So the output of asymmetrical
MLI has very less amount of harmonics i.e.,
output is smoother.

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