EE213M

Digital Circuits

Arun Tej M.
EE213M Digital Circuits

L15: Common Functional Blocks - 2

MUX with Enable Input

In addition to the data and select lines, some times an ‘enable’ line is also used in a mux. An ‘Enable’ input
is like a switch that activates or deactivates the mux.
For example:
When 𝐸𝑁 = 1, the mux will function normally. When 𝐸𝑁 = 0, the output of the mux will be zero.
When 𝐸𝑁 = 0, the mux will function normally. When 𝐸𝑁 = 1, the output of the mux will be zero.

Active high enable

𝐸𝑁 𝐸𝑁
Active low enable 𝑆 2𝑛 to 1 𝑆 2𝑛 to 1 𝑍
𝑍
MUX MUX
𝐼 𝐼

2𝑛 −1
General equation for the output of a MUX with 𝑛 𝑍 = ෍ 𝐸𝑁. 𝑚𝑘 . 𝐼𝑘
control inputs and active high enable input is 𝑘=0
MUX with Enable Input

𝐼0
𝐸𝑁 𝐴 𝐵 𝐶 𝑍
. .
. . 1 𝑋 𝑋 𝑋 0
. . 𝑍
0 0 0 0 𝐼0
𝐼𝑛−1 0 0 0 1 𝐼1
0 0 1 0 𝐼2
0 0 1 1 𝐼3
𝑆 𝐸𝑁 0 1 0 0 𝐼4
0 1 0 1 𝐼5
0 1 1 0 𝐼6
𝐸𝑁
0 1 1 1 𝐼7
𝑆 2 to 1
𝑛
𝑍
MUX
𝐼
Demultiplexer (DeMUX)

1 Input line 𝑚 Select lines 𝑛 = 2𝑚 Output lines

𝐷0
1 to 2𝑚 𝐷1
The input line will be connected to one of the output lines IN .
DeMUX .
depending on the value of select lines 𝑆 = 𝑆0 , 𝑆1 , … , 𝑆𝑚 .
𝐷𝑛−1
For example: …
𝑆 = 0 ⇒ 𝐼𝑁 → 𝐷0 ; 𝑆 = 1 ⇒ 𝐼𝑁 → 𝐷1 ; 𝑆 = 2 ⇒ 𝐼𝑁 → 𝐷2 and so on. 𝑆0 𝑆1 𝑆𝑚−1

The outputs that are not selected will be set to 0

𝐴 𝑃
𝐵 2𝑚 to 1 1 to 2𝑚 𝑄
𝐶 . . 𝑅
. MUX DeMUX .
. .

0 1 0 0 1 1
DeMUX Using Logic Gates

𝐼𝑛 𝑆0 𝐷0 𝐷1
1 to 2 𝐷0 = 𝑆0′ . 𝐼𝑛
0 0 0 0 𝐼𝑛
DeMUX
0 1 0 0 𝐷1 = 𝑆0 . 𝐼𝑛
1 0 1 0
1 1 0 1
𝑆0

𝑆0
𝐷0
𝐼𝑛
𝐷1
DeMUX Using Logic Gates

𝑆0
c
𝐷0 𝐷0 = 𝑆1′ . 𝑆0′ . 𝐼𝑛
𝑆1 c c c 𝐼𝑛 1 to 4 𝐷1 = 𝑆1′ . 𝑆0 . 𝐼𝑛
𝐼𝑛
DeMUX 𝐷2 = 𝑆1 . 𝑆0′ . 𝐼𝑛
c
𝐷1
𝐼𝑛 𝐷3 = 𝑆1 . 𝑆0 . 𝐼𝑛

𝐷2 𝑆1 𝑆0
𝐼𝑛
c
𝐷3
𝐼𝑛
Decoder

• Can be considered as a special case of DeMUX: Data input is always 1 ⇒ No need to specifically apply
• 𝑛 select lines as inputs and 2𝑛 output lines
• Depending on the applied input, exactly one of the output lines is set to 1. All others are set to 0.
• Reverse convention is followed in some cases (selected output line is set to 0 and other to 1).
Decoder

• Can be considered as a special case of DeMUX: Data input is always 1 ⇒ No need to specifically apply
• 𝑛 select lines as inputs and 2𝑛 output lines
• Depending on the applied input, exactly one of the output lines is set to 1. All others are set to 0.
• Reverse convention is followed in some cases (selected output line is set to 0 and other to 1).
• Sometimes, another input will be used to enable or disable a decoder
• Active Low and Active High conventions

𝐸 = 0 ⇒ Enable 𝐸 = 1 ⇒ Disable 𝑓0
𝐼0 𝑓1
𝐸 = 0 ⇒ Disable 𝐸 = 1 ⇒ Enable 𝐼1 𝑛 to 2𝑛
.. ..
. Decoder .
𝐼𝑛−1
𝑓2𝑛−1
𝐸
Decoder

𝑓0 𝐸 𝐼1 𝐼0 𝑓0 𝑓1 𝑓2 𝑓3
𝐼0
2-to-4 𝑓1
0 0 0 1 0 0 0
𝐼1 Decoder 𝑓2
0 0 1 0 1 0 0
𝑓3
𝐸 0 1 0 0 0 1 0
0 1 1 0 0 0 1
𝐸 = 0 Enable
1 𝑋 𝑋 0 0 0 0
𝐸 = 1 Disable

𝑓0 = 𝐼1′ . 𝐼0′ . 𝐸′

𝑓1 = 𝐼1′ . 𝐼0 . 𝐸′

𝑓2 = 𝐼1 . 𝐼0′ . 𝐸′

𝑓3 = 𝐼1 . 𝐼0 . 𝐸′
4-to-16 Decoder Using 2-to-4 Decoders
𝐼0 𝑓0
2-to-4 𝑓1
𝐼0 𝑓0 Decoder 𝑓2
𝐼1 4-to-16 𝐼1
..
𝑓3
𝐼2 Decoder .
𝐼3 𝑓15
𝐼0 𝑓4
𝐸
𝐼2 2-to-4 𝑓5
𝐸 = 0 Enable 2-to-4 Decoder 𝑓6
𝐼3 Decoder 𝐼1
𝐸 = 1 Disable 𝑓7

𝐼0 𝑓8
𝐸
𝐸 𝐼3 𝐼2 𝐼1 𝐼0 2-to-4 𝑓9
𝐼0 𝑓12 Decoder 𝑓10
0 0 0 0 0 𝑓0 𝐼1
2-to-4 𝑓13 𝑓11
0 1 0 0 1 𝑓9 Decoder 𝑓14
𝐼1 𝑓15
Decoder Using Switching Matrix Design

𝑓0 𝑓1 𝑓2 𝑓3

𝑎
𝑓4 𝑓5 𝑓6 𝑓7
𝑤
2-to-4 𝑏
Decoder 𝑓8 𝑓9 𝑓10 𝑓11
𝑥
𝑐
𝑓12 𝑓13 𝑓14 𝑓15
𝑤 𝑓0
𝑑
𝑥 4-to-16
𝑦 Decoder .. 𝑓 𝑔
. 𝑒 ℎ
𝑧 𝑓15
𝐸 𝑦 2-to-4
Decoder
𝑧
Advantages:
Only 2-input AND gates are required ⇒ Smaller gates, Less complicated gate design, Faster
Logic Functions Using Decoders

𝐴 𝐵 𝐶 𝐹
0 0 0 0
0 0 0 1
0 0 1 1
𝐶
0 0 1 0 𝐹 = ෍ 𝑚(1, 2, 5, 7)
0 0 3-to-8
1 0 𝐵 𝐹
Decoder
0 1 0 1
𝐴
0 1 1 0
0 1 1 1
Logic Functions Using Decoders
Decimal Decoder

Not all decoders have exactly 2𝑛 outputs.

For example, a decimal decoder will have 𝑛 = 4 inputs, but

only 10 outputs (corresponding to the numbers 0 − 9).
Decimal Decoder
Decimal Decoder
BCD to Seven Segment Decoder for Display

Numerical display – from 0 to 9

LEDs, LCDs etc.

Two types of displays (say, using LEDs) are usually available:

Common Anode: Negative terminals are available outside to be connected to voltage low i.e., 0
Common Cathode: Positive terminals are available outside to be connected to voltage high i.e., 1
BCD to Seven Segment Decoder for Display

Minimize each output function,

for ex., by using K-maps

𝑥1 𝑥2
𝑥3 𝑥4 00 01 11 10
00 1 1 𝑋 1

01 1 0 𝑋 1

11 1 1 𝑋 𝑋

10 1 0 𝑋 𝑋

𝑥2′ 𝑥3 𝑥4 𝑥3′ 𝑥4′

BCD to Seven Segment Decoder for Display

It can be implemented either as a conventional multi-output circuit

or using a single 4-to-16 line decoder plus seven OR gates.
 Sine Generator

• Trigonometric functions can either be generated sequentially or produced by combinational circuits.

• Combinational sine generators are used whenever the sine function must be evaluated fast and repeatedly.

• A combinational sine generator receives as its input the angle and as output produces the sine of that angle.

• The angle is given in radians converted to binary and the sine value is produced in binary.

• Naturally, the accuracy of the calculation is a function of the number of bits that describe the angles and
sine values.

• In practical applications, at least eight binary digits are required to describe the angles or sine values.

𝑥1 𝑧1
𝑥2 Sine 𝑧2
𝜃 sin(𝜃)
𝑥3 Generator 𝑧3
𝑥4 𝑧4
 𝜽 𝜽 𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 𝒛𝟏 𝒛𝟐 𝒛𝟑 𝒛𝟒
Sin 𝜽 Value
(degrees) (radians) 𝟐−𝟏 𝟐−𝟐 𝟐−𝟑 𝟐−𝟒 𝟐−𝟏 𝟐−𝟐 𝟐−𝟑 𝟐−𝟒
0 𝑜𝑟 180 0 or 𝜋 0 0 0 0 0 0 0 0 0 0
11.25 𝜋/16 0 0 0 1 0.195 0 0 1 1 0.187
22.5 2𝜋/16 0 0 1 0 0.382 0 1 1 0 0.375
33.75 3𝜋/16 0 0 1 1 0.555 1 0 0 0 0.500
45 4𝜋/16 0 1 0 0 0.707 1 0 1 1 0.687
56.25 5𝜋/16 0 1 0 1 0.831 1 1 0 1 0.812
67.5 6𝜋/16 0 1 1 0 0.923 1 1 1 0 0.875
78.75 7𝜋/16 0 1 1 1 0.980 1 1 1 1 0.937
90 8𝜋/16 1 0 0 0 1 1 1 1 1 0.937
101.25 9𝜋/16 1 0 0 1 0.980 1 1 1 1 0.937
112.5 10𝜋/16 1 0 1 0 0.923 1 1 1 0 0.875
123.75 11𝜋/16 1 0 1 1 0.831 1 1 0 1 0.812
135 12𝜋/16 1 1 0 0 0.707 1 0 1 1 0.687
146.25 13𝜋/16 1 1 0 1 0.555 1 0 0 0 0.500
157.5 14𝜋/16 1 1 1 0 0.382 0 1 1 0 0.375
168.75 15𝜋/16 1 1 1 1 0.195 0 0 1 1 0.187
𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 𝒛𝟏 𝒛𝟐 𝒛𝟑 𝒛𝟒
0 0 0 0 0 0 0 0 𝑧1 = ෍ 𝑚(3,4,5,6,7,8,9,10,11,12,13)
0 0 0 1 0 0 1 1
0 0 1 0 0 1 1 0 𝑧2 = ෍ 𝑚(2,5,6,7,8,9,10,11,14)
0 0 1 1 1 0 0 0
𝑧3 = ෍ 𝑚(1,2,4,6,7,8,9,10,12,14,15)
0 1 0 0 1 0 1 1
0 1 0 1 1 1 0 1
𝑧4 = ෍ 𝑚(1,4,5,7,8,9,11,12,15)
0 1 1 0 1 1 1 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 1
1 0 1 0 1 1 1 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 1 1
1 1 0 1 1 0 0 0
1 1 1 0 0 1 1 0
1 1 1 1 0 0 1 1