DIGITAL LOGIC DESIGN

LAB ASSIGNMENT
TASK-5

Multiplexer, Demultiplexer, Encoder, Decoder, Full adder/subtractor

NAME: BASUPALLY KARTHIK REDDY

REG. NUMBER :20BEC0512

Objective:
To design and verify the following circuits using Testbench on Modelsim:
• 4:1 Mux
• 1:4 Demultiplexer
• 4:2 Encoder
• 4:4 Decoder
• Full Adder
• Full Subtractor
 1. 4:1 Mux :

TRUTH TABLE:

CIRCUIT:
OUTPUT WAVEFORM:
 2. 1:4 Demux :

TRUTH TABLE:

CIRCUIT:
OUTPUT WAVEFORM:
 3. 4:2 Encoder :

TRUTH TABLE:

CIRCUIT:
OUTPUT WAVEFORM:

4. 2:4 Decoder :

TRUTH TABLE:

CIRCUIT:
OUTPUT:
 5. Full Adder:

TRUTH TABLE:

DESIGN:
OUTPUT WAVEFORM:
 6. Full Subtractor :

TRUTH TABLE:

DESIGN:

CODE:
Output: