QUESTION NUMBER

SUB.CODE
SUB.NAMEDept-Year DATE TYPE
1 EE8551 MPMC 3-EEE 1/22/2021 MC
2 EE8551 MPMC 3-EEE 1/22/2021 MC
3 EE8551 MPMC 3-EEE 1/22/2021 MC
4 EE8551 MPMC 3-EEE 1/22/2021 MC
5 EE8551 MPMC 3-EEE 1/22/2021 MC
6 EE8551 MPMC 3-EEE 1/22/2021 MC
7 EE8551 MPMC 3-EEE 1/22/2021 MC
8 EE8551 MPMC 3-EEE 1/22/2021 MC
9 EE8551 MPMC 3-EEE 1/22/2021 MC
10 EE8551 MPMC 3-EEE 1/22/2021 MC
11 EE8551 MPMC 3-EEE 1/22/2021 MC
12 EE8551 MPMC 3-EEE 1/22/2021 MC
13 EE8551 MPMC 3-EEE 1/22/2021 MC
14 EE8551 MPMC 3-EEE 1/22/2021 MC
15 EE8551 MPMC 3-EEE 1/22/2021 MC
16 EE8551 MPMC 3-EEE 1/22/2021 MC
17 EE8551 MPMC 3-EEE 1/22/2021 MC
18 EE8551 MPMC 3-EEE 1/22/2021 MC
19 EE8551 MPMC 3-EEE 1/22/2021 MC
20 EE8551 MPMC 3-EEE 1/22/2021 MC
21 EE8551 MPMC 3-EEE 1/22/2021 MC
22 EE8551 MPMC 3-EEE 1/22/2021 MC
23 EE8551 MPMC 3-EEE 1/22/2021 MC
24 EE8551 MPMC 3-EEE 1/22/2021 MC
25 EE8551 MPMC 3-EEE 1/22/2021 MC
26 EE8551 MPMC 3-EEE 1/22/2021 MC
27 EE8551 MPMC 3-EEE 1/22/2021 MC
28 EE8551 MPMC 3-EEE 1/22/2021 MC
29 EE8551 MPMC 3-EEE 1/22/2021 MC
30 EE8551 MPMC 3-EEE 1/22/2021 MC
31 EE8551 MPMC 3-EEE 1/22/2021 MC
32 EE8551 MPMC 3-EEE 1/22/2021 MC
33 EE8551 MPMC 3-EEE 1/22/2021 MC
34 EE8551 MPMC 3-EEE 1/22/2021 MC
35 EE8551 MPMC 3-EEE 1/22/2021 MC
36 EE8551 MPMC 3-EEE 1/22/2021 MC
37 EE8551 MPMC 3-EEE 1/22/2021 MC
38 EE8551 MPMC 3-EEE 1/22/2021 MC
39 EE8551 MPMC 3-EEE 1/22/2021 MC
40 EE8551 MPMC 3-EEE 1/22/2021 MC
41 EE8551 MPMC 3-EEE 1/22/2021 MC
42 EE8551 MPMC 3-EEE 1/22/2021 MC
43 EE8551 MPMC 3-EEE 1/22/2021 MC
44 EE8551 MPMC 3-EEE 1/22/2021 MC
45 EE8551 MPMC 3-EEE 1/22/2021 MC
 QUESTION
In 8085, 16-bit address bus, which can address upto?
____________ is also 16 bit register works like stack, which is always incremented / devremented by 2 during push & pop operations.
__________ signal indicates that another master is requesting the use of of the address and data buses
Which of the following is true about control and status signals?
MOV A,B is an example?
Which one of the following addressing technique is not used in 8085?
Handshaking mode of data transfer is
The program counter in a 8085 microprocessor is a 16-bit register, because
The instruction JNC 16 bit refers to jump to 16 bit address if ?
Direction flag is used with
The number of output pins of a 8085 processor are
The register which holds the information about the nature of results of arithmetic of logic operations is called as
In a 8085 microprocessor system with memory-mapped I/O, which of the following is true?
Ready pin of microprocessor is used
A bus connected between the CPU and the main memory that permits transfer of information between main memory and the CPU is know
At the beginning of a fetch cycle, the contents of the program counter are
In 8085, the address for TRAP interrupt is
Among the given instructions, the one which affects maximum of flags is
What is the bit addressing range of addressable individual bits over the on chip RAM?
Which register is used to store the output generated BY viersmser
Which form of instructions also belong to the category of logical instructions in addtion to bitwise logical instructions?
Which of the following is the bit of the IE used to enable Tx and Rx interrupt?
Which among the single operand instructions complement the accumulator without affecting any of the flags?
Which port does not represent quasi-bi directional nature of I/O ports in accordance to the pin configuration of 8051?
What kind of PSW flags remain unaffected by the data transfer instructions?
What pins are configured as an output (ie logic 0), then the single port pins can receive a current of ?
What is the following are features of 8255A?
The upper 128 bytes of an internal data memory drom 80H through FFh usually represent ____________
Output of the assembler in machine codes is referred to as
The 8051 controller has ____________ parell I/O ports?
The difference between 8085 instructions RST n and PCHL is
When a peripheral is connected to the microprocessor in input/output mode, the data transfer takes place between
The content of accumulator are 70H. Initially all flags are zero. What will be values of CY and S after executing instruction RLC?
In 8085 microprocessor, ALE signal is made high to
While execution of I/O instruction takes place, the 8 bit address of the port is placed on
What happens when the pins of port 0 and port2 are switched to internal ADD R and ADDR / DATA bus respectively while accessing an ex
Which signal from CPU has an ability to respond the clocking value of D flip flop (bit latch) from the internal bus?
Which kind of instructions usually affect the program counter?
In 8085, On execution of the following segment of instructions in sequence MVI A,91H; XRI 91H ; Which one of the following is correct?
In 8279 status word, when data is read then which of the following pins are set to low & in write to the display RAM then which of the follo
In 8085, to disable the whole interrupt system (except TRAP)
For a microprocessor system using I/O mapped IO the following is NOT true
Which flags represent the LSB and MSB of PSW respectively?
Which amoung the below stated registers does not belong to the category of SFR?
What is the divisional range of program memory for internal and external memory portions respectively when enable access pin is held hi
 option1
16KB
flag register
HOLD
Used to identify the nature of operation
immediate addressing mode
register indirect
synchronous data transfer
it has to fetch two 8-bit data ata time
sign flag is set
string instruction
40
Accumulator
devices have 8-bit address line
to introduce direct memory access
DMA bus
transferred to memory address register
0024h
RAL
00h to FF h
Special function register
single operand instructions
IE.D2
CLR
port 0 ( pins 32-39)
auxillary carry flag
5mA
consists of 3-8 bit IO portd (ie. PA,PB and PC)
general purpose registers
source program
2
RST n is equivalent to a sub routine call while PCHL is equivalent to unconditional branch
any register and I/O device
CY=0 , S=0
enable the data bus to be used as low order address bus
lower address bus
ports cannot be used as general purpose inputs / outputs
write-to-read signal
POP
ACC=00H, CY=0,AF=1 and ZF=0
A0,CS,RD & A0,CS,WR
DO instruction may be used
memory space available is greater
parity flag & carry flag
TCON & TMOD
0000H-0FFFH & 1000H-FFFFH
 option2
32KB
stack register
READY
3 control signal and 3 status signal
register addressing mode
immediate
asynchronous mode
there are 16 address lines
carry flag is reset
stack instruction
26
condition code register
arithmetic and logic operations can be directly performed with I/O dat
to indicate that the microprocessor is ready to receive outputs
memory bus
incremented by one
002ch
POP PSW
01h to 7Fh
timer register
rotate instruction
IE.D3
SETB
port 1(pins 1-8)
overflow flag
8mA
address/data bus must be externally demux'd
special function register
object program
3
RST n uses direct addressing while PCHL uses register indirect address
memory and I/O device
CY=1,S=1
to latch data D0-D7 from the data bus
higher address bus
ports start sinking more current than sourcing
write-to-latch signal
CALL & RETURN
ACC=00H,CY=0,AF=0,ZF=1
A0,CS,WR & A0,CS,RD
the INTERRUPT instruction used
not all data transfer instructions are available
parity flag & auxiliary carry flag
TH0 & TL0
0000H-1000H & 0FFFH - FFFFH
 option3
64KB
temporary register
HLDA
three status signals are IO/M, A0 & S1
direct addressing mode
register
interrupt driven data transfer
it counts 16bit at a time
aero flag is set
arithmetic instruction
27
process status register
there can be maximum of 256 input devices and 256 output devices
to introduce wait state
address bus
transferred to address bus
0034h
XRA A
ooH to 7Fh
accumulator and I/O device
swap instruction
IE.D4
CPL
port 2 (pins 21-28)
parity flag
15mA
TTL compatible
stack pointer
macro program
4
RST n is a software interrupt while PCHL simulates a hardware interrupt
accumulator and I/O device
CY=1,S=0
to disable data bus
data bus
ports cannot be further used as high impedancei input
read-to-write signal
CALL & JUMP
ACC=91H,CY=0,AF=1 and ZF=1
A0,RD & CS,WR
DI instruction be used
IO and memory address spaces are distinct
carry flag & overflow flag
P0 & P1
0001H-0FFFH & 01FFH-FFFFH
 option4 answer mark
128KB option3 1
program counter option2 1
INTA option1 1
all the above option4 1
indirect addressing mode option2 1
relative option4 1
level mode of DMA data transfer option1 1
it facilltates the user storing 16 bit data temporarily option2 1
parity flag is reset option2 1
branch instruction option1 1
19 option3 1
flag register option4 1
devices are accessed using IN and OUT instructions option2 1
to indicate that the microprocessor is ready to receive inputs option3 1
conrol bus option2 1
transferred to memory data register option1 1
003ch option1 1
DCR A option3 1
80h to FF h option3 1
stack pointer option2 1
all the above option4 1
IE.D5 option4 1
all the above option3 1
port 3 (pins 10-17) option1 1
all the above option4 1
10mA option4 1
all the above option4ss 1
program counter option2 1
symbolic addressing option2 1
5 option 1
RST n resets the processor while PCHL restarts the processor option1 2
HL register and I/O device option3 2
CY=0 ,S=1 option4 2
to achieve all the functions listed above option1 2
lower as well as higher order address bus option4 2
all the above option1 2
read-to-latch signal option2 2
PUSH option2 2
ACC=91H, CY=0,AF=1 and ZF=0 option2 2
CS,RD & A0,CS option1 2
EI instruction be used option3 2
IO address space is greater option4 2
carry flag & auxiliary carry flag option1 2
SP & PC option4 2
none of the above option1 2
option2