Ejemplo 1 ---------------

-- Package.-------- generic map (

LIBRARY ieee ; WIDTH => WORD_WIDTH
USE ieee.std_logic_1164.all; )
port map (
PACKAGE pack_ejemplo is --inputs
---Declaracion de las constantes utilizadas en el proyecto------- rstn => rstn,
constant WORD_WIDTH : integer := 8; -- ancho de palabra utilizado clk => clk,
----------------------------------------------------------------- ena => ena,
component registro D => A,
---------------------------- --outputs
GENERIC( Q => s_A_r
WIDTH: integer );
); ---------------
PORT( reg_B: registro
rstn : IN STD_LOGIC; ---------------
clk : IN STD_LOGIC; generic map (
ena : IN STD_LOGIC; WIDTH => WORD_WIDTH
D : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0); )
port map (
--inputs
Q : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0) rstn => rstn,
); clk => clk,
end component; ena => ena,
---------------------------- D => B,
component sumador --outputs
---------------------------- Q => s_B_r
GENERIC( );
WIDTH: integer ---------------
); Suma_A_B: sumador
PORT( ---------------
A : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0); generic map (
B : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0); WIDTH => WORD_WIDTH
)
port map (
S : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
--inputs
);
A => s_A_r,
end component;
B => s_B_r,
end pack_ejemplo;
--outputs
--------------------------------------------------------- S => S
-- sumador de ancho de palabra variable---------------------------------- );
LIBRARY ieee ; END struct;
USE ieee.std_logic_1164.all; ---------------------------------------------------------
USE ieee.std_logic_arith.all; -- registro con enable de ancho de palabra variable
use ieee.std_logic_unsigned.all; ---------------------------------------------------------
ENTITY sumador IS
GENERIC( LIBRARY ieee ;
WIDTH: integer USE ieee.std_logic_1164.all;
);
PORT( ENTITY registro IS
A : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0); GENERIC(
B : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0); WIDTH: integer
);
S : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0) PORT(
); rstn : IN STD_LOGIC;
END sumador; clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
ARCHITECTURE struct OF sumador IS D : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
BEGIN
S <= A + B; Q : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
END struct; );
END registro;
Ejemplo2
-- version 0 17 Marzo 2002 ARCHITECTURE behav OF registro IS
----------------------------- BEGIN
LIBRARY ieee ; ---------------
library pepe; D_registro:
USE ieee.std_logic_1164.all; ---------------
use pepe.pack_ejemplo.all; PROCESS(clk,rstn,D) --generacion de los D-FF
ENTITY ejemplo IS BEGIN
PORT( IF (rstn='0') THEN
rstn : IN STD_LOGIC; Q <= (OTHERS => '0');
clk : IN STD_LOGIC; ELSIF (clk'event AND clk='1') THEN
ena : IN STD_LOGIC; IF (ena='1') THEN
A : IN STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0); Q <= D;
B : IN STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0); END IF;
S : OUT STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0) END IF;
); END PROCESS D_registro;
END ejemplo; END behav;

ARCHITECTURE struct OF ejemplo IS

signal s_A_r : STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0); --salida de

registro donde se almacena A
signal s_B_r : STD_LOGIC_VECTOR(WORD_WIDTH-1 downto 0); --salida de
registro donde se almacena A
BEGIN
---------------
reg_A: registro