EC20B1042 B Srinidhi

Code converter

G[3] = bin[3]
G[2] = bin[3] ^ bin[2]
G[1] = bin[2] ^ bin[1]
G[0] = bin[1] ^ bin[0]

bin[3] = G[3]
bin[2] = G[3] ^ G[2]
bin[1] = G[3] ^ G[2] ^ G[1]
bin[0] = G[3] ^ G[2] ^ G[1] ^ G[0]

E0=B0'
E1=B1B0+B1'B0'
E2=B2'B1+B2'B0+B2B1'B0'
E3=B3+B2B1+B2B0

B1=E1'E0+E1E0'
B2=E2'E1'+E2'E0'+E2E1E0
B3=E3E2+E3E1E0

Design source:

module mag_comp(output [3:0] Y, input [3:0] A, input [1:0] V);

reg [3:0] Y;
always@(A or V)
begin
case(V)
2'b00:
begin
Y[3] = A[3];
Y[2] = A[3]^A[2];

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 EC20B1042 B Srinidhi

Y[1] = A[2]^A[1];
Y[0] = A[1]^A[0];
end
2'b01:
begin
Y[3] = A[3];
Y[2] = A[3]^A[2];
Y[1] = A[3]^A[2]^A[1];
Y[0] = A[3]^A[2]^A[1]^A[0];
end
2'b10:
begin
Y[3] = A[3]|(A[2]&A[1])|(A[2]&A[0]);
Y[2] = A[2]^(A[1]|A[0]);
Y[1] = ~(A[1]^A[0]);
Y[0] = ~A[0];
end
2'b11:
begin
Y[3] = (A[3]&A[2]&~A[1]&~A[0])|(A[3]&~A[2]&A[1]&A[0]);
Y[2] = (~A[3]&A[2]&A[1]&A[0])|(~A[2]&(~A[1]|~A[0]));
Y[1] = (A[3]&A[2]&A[1]&A[0])|((~A[3]|~A[2])&(A[1]^A[0]));
Y[0] = ~A[0];
end
default: Y = 0;
endcase
end
endmodule

Test bench:

module tmc();

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 EC20B1042 B Srinidhi

reg Y;
wire A,V;
mag_comp cc(Y,A,V);

initial
begin
A=4'b0001;V=2'b00;
#10 A=4'b0110;V=2'b01;
#10 A=4'b1001;V=2'b10;
#10 A=4'b1110;V=2'b11;
#10 $finish;
end
endmodule

Magnitude comparator

module mag_comp(output R,G,BL, input [3:0] A, B);

wire [3:0] X;
assign X[3] = ~(A[3]^B[3]);
assign X[2] = ~(A[2]^B[2]);
assign X[1] = ~(A[1]^B[1]);
assign X[0] = ~(A[0]^B[0]);
assign R = X[3]& X[2]& X[1]& X[0];
assign G = (A[3]&~B[3])|(X[3]& A[2]&~B[2]) |(X[2]& A[1]&~B[1]) |(X[1]&
A[0]&~B[0]);
assign BL = (~A[3]&B[3])|(X[3]& ~A[2]&B[2]) |(X[2]& ~A[1]&B[1]) |(X[1]&
~A[0]&B[0]);
Endmodule

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 EC20B1042 B Srinidhi

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 EC20B1042 B Srinidhi

Result:

All Code converters and magnitude comparators have been

implemented using logic gates using Multisim and verified
them using truth tables.

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