B Srinidhi EC20B1042

7.1 Even Parity Generator

Even Parity = A ⊕ B ⊕ C ⊕ D

Page 2 of 14
 B Srinidhi EC20B1042

7.2 Odd Parity generator

Odd Parity = A ⊙ B ⊙ C ⊙ D

Page 3 of 14
 B Srinidhi EC20B1042

7.3. 2x1 MUX

Gates -

Y = S’D0 + SD1

Page 4 of 14
 B Srinidhi EC20B1042
IC

Page 5 of 14
 B Srinidhi EC20B1042

7.4 4x1 MUX

Y = S0‘ S1‘ D0 + S0‘ S1 D0 + S0 S1‘ D0 + S0 S1 D0

Page 6 of 14
 B Srinidhi EC20B1042
IC -

Page 7 of 14
 B Srinidhi EC20B1042

7.5 8x1 MUX

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S1.S3.A7

IC -

Page 8 of 14
 B Srinidhi EC20B1042
Gates

Page 9 of 14
 B Srinidhi EC20B1042

7.6 16x1 MUX

Y=A0.S0'.S1'.S2'.S3' +A1.S0'.S1'.S2'.S3 +A2.S0'.S1'.S2.S3' +A3.S0'.S1'.S2.S3 +A4.S0'.S1.S2'.S3' +A5.S0'.S1.S2'.S3 +A6.S0'.S1.S2.S3'

+A7.S0'.S1.S2.S3 +A8.S0.S1'.S2'.S3' +A9.S0.S1'.S2'.S3 +Y10.S0.S1'.S2.S3 '+A11.S0.S1'.S2.S3 +A12 S0.S1.S2'.S3' +A13.S0.S1.S2'.S3
+A14.S0.S1 .S2.S3' +A15.S0.S1.S2'.S3

Page 10 of 14
B Srinidhi EC20B1042

Page 11 of 14
B Srinidhi EC20B1042

Page 12 of 14
B Srinidhi EC20B1042

Page 13 of 14
 B Srinidhi EC20B1042

Result:
All Parity generators and Multiplexers comparators have been
implemented using logic gates using Multisim and verified them
using truth tables.

Page 14 of 14