Professional Documents
Culture Documents
1 1
KSWAA/KTWAA
Liverpool 10M/10MG
2
Sunderland 10M/10MG 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 1 of 45
A B C D E
A B C D E
Compal Confidential
Model Name : KSWAA/KTWAA Fan Control Intel Penryn Processor Thermal Sensor Clock Generator
File Name : LA-4981P APL5607 EMC1402-1 SLG8SP556VTR
page 4 uPGA-478 Package page 4 page 16
1
(Socket P) page 4,5,6
1
CRT FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)
page 19
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
page 17
VGA MXM/B LCD Conn. Intel Cantiga Dual Channel
page 18 BANK 0, 1, 2, 3 page 14,15
ATI M92XT,64bit with 128M/256MB PCIE-Express 16X GM45/PM45/GL40 1.5V DDR3 800/1066
ATI M96,128bit with 256M/512MB GM47/GM49
EC HDMI CEC Controller HDMI Conn. Level Shifter uFCBGA-1329
SMBUS R5F211A4SP page 20 page 20
page 20 page 7,8,9,10,11,12,13
USB/B FP/B
PCIeMini Card USB port 0,1 USB port 8
WiMax page 25 page 26
2 2
USB port 7
page 27
DMI x 4 C-Link BT conn Int. Camera
PCIeMini Card USB USB port 5 USB port 11
WLAN 5V 480MHz USB page 26 page 18
PCIe port 4 PCIe 1x [2,4,5] 5V 480MHz
page 27
1.5V 2.5GHz(250MB/s)
3.3V 33 MHz
LPC BUS HD Audio 3.3V/1.5V 24.576MHz/48Mhz
page 36,37,38,39
FP/B for 17" 40,41,42
page 25 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/22 Deciphered Date 2012/07/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 2 of 45
A B C D E
A B C D E
VIN Adapter power supply (19V) ON ON ON OFF S1(Power On Suspend) LOW HIGH HIGH HIGH
1 1
B+ AC or battery power rail for power circuit. ON ON ON ON
S3 (Suspend to RAM) LOW LOW HIGH HIGH
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH
+1.05VS 1.05V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF OFF G3 LOW LOW LOW LOW
+1.8VS 1.8V power rail for VRAM ON ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3VL 3.3V always on power rail ON ON ON ON
+3V_SB 3.3V power rail for LAN ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF BTO Option Table
+3VS 3.3V switched power rail ON OFF OFF OFF
+3VS_HDP 3.3V power rail for G-sensor ON OFF OFF OFF
Function Express Card/ PCMCIA Bluetooth RJ11 Camera 3D Sensor
+5VALW 5V always on power rail ON ON ON OFF
2 +5VL 5V always on power rail ON ON ON ON (E) (A) (B) (R) (X) (S) 2
description
+5V_SB 5V power rail for SB ON ON OFF OFF
explain Express Card PCMCIA Bluetooth MDC Camera 3D Sensor
+5VS 5V switched power rail ON OFF OFF OFF
+VSB VSB always on power rail ON ON ON OFF BTO NEW@ PCM@ BT@ MDC@ CAM@ GSENSOR@
+RTCVCC RTC power ON ON ON ON
Function HDMI
External PCI Devices
description (Y)
DEVICE PCI DEVICE ID IDSEL# REQ/GNT# PIRQ
CARD BUS D4 AD20 1 A/B explain Intel(UMA) ATI VGA/B COMMON
3 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 3 of 45
A B C D E
5 4 3 2 1
@
7 H_A#[3..16] +3VS
JCPUA
H_A#3 J4 H1
A[3]# ADS# H_ADS# 7
ADDR GROUP_0
H_A#4 L5 E2
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# 7
H_A#6
0.1U_0402_16V4Z
K5 A[6]# 1
H_A#7 M3 H5
A[7]# DEFER# H_DEFER# 7 C1
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 U1
A[9]# DBSY# H_DBSY# 7 2
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 1 8
A[12]# VDD SMCLK EC_SMB_CK2 17,33
CONTROL
D H_A#13 L2 D20 H_IERR# R1 1 2 56_0402_5% +1.05VS D
H_A#14 A[13]# IERR# H_INIT# H_THERMDA
P4 A[14]# INIT# B3 H_INIT# 22 2 DP SMDATA 7 EC_SMB_DA2 17,33
H_A#15 P1 C2
H_A#16 A[15]# H_THERMDC
R1 A[16]# LOCK# H4 H_LOCK# 7 1 2 3 DN ALERT# 6 1 2 +3VS
M1 2200P_0402_50V7K R2 10K_0402_5%
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET# CPU_THERM# 4 5 @ Reserve for source control
RESET# H_RESET# 7 THERM# GND
7 H_REQ#0 K3 REQ[0]# RS[0]# F3 H_RS#0 7
H2 F4 R3
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7 if use XDP,these resistor are 51ohm
7 H_REQ#2 K2 REQ[2]# RS[2]# G3 H_RS#2 7 +3VS 1 2
J3 G2 +1.05VS 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
7 H_REQ#4 L1 REQ[4]#
Address:0100_1100 EMC1402-1
G6 XDP_TDO 1 2 Address:0100_1101 EMC1402-2
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 R14 54.9_0402_1%
A[17]# HITM# H_HITM# 7
H_A#18 U5 XDP_TMS 1 2
H_A#19 A[18]# R4 54.9_0402_1%
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1
H_A#20 W6 AD3 XDP_TDI 1 2
H_A#21 A[20]# BPM[1]# R5 54.9_0402_1%
U4 AD1
H_A#22 Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4
+5VS
FAN Control Circuit
XDP/ITP SIGNALS
H_A#23 U1 AC2 XDP_TCK 1 2
H_A#24 A[23]# PRDY# R6 54.9_0402_1%
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK XDP_TRST# 1 2 1A
H_A#26 A[25]# TCK XDP_TDI R7 54.9_0402_1% 1SS355_SOD323-2
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO
A[27]# TDO PAD T13
1
H_A#28 W5 AB5 XDP_TMS +1.05VS 1 2
H_A#29 A[28]# TMS XDP_TRST# R8 @ 56_0402_5%
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# 1 2 2 D1
A[30]# DBR# XDP_DBRESET# 23
H_A#31 V4 R9 56_0402_5% @
A[31]#
2
JFAN
B
H_A#32 W3 C3
2
H_A#33 AA4 A[32]# 10U_0805_10V4Z +FAN1
A[33]# THERMAL 1
1 1
E
C H_A#34 AB2 H_PROCHOT# 3 1 2 C
A[34]# OCP# 23 2
1
C
H_A#35 AA3 D21 H_PROCHOT# Q6 2 3
A[35]# PROCHOT# H_THERMDA @ MMBT3904_SOT23 U2 3
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC PROCHOT# PU: 68Ohm near CPU and MVP6. 1 8 D2 C4 4
H_A20M# THERMDC EN GND @ @ 1000P_0402_25V8J GND
22 H_A20M# A6 A20M# 56Ohm near CPU if no used. 2 VIN GND 7 5 GND
1
ICH
H_FERR# A5 C7 +FAN1 3 6
22 H_FERR# H_THERMTRIP# 8,22
2
H_IGNNE# FERR# THERMTRIP# VOUT GND
22 H_IGNNE# C4 IGNNE# 33 EN_DFAN1 4 VSET GND 5 ACES_85204-0300N
1 BAS16_SOT23-3 @
H_STPCLK# D5 10mil APL5607KI-TRG_SO8
22 H_STPCLK# STPCLK#
H_INTR C6 H CLK C5
22 H_INTR LINT0
H_NMI B4 A22 H_THERMDA, H_THERMDC routing together, 10U_0805_10V4Z R10 10K_0402_5%
22 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16 2
H_SMI# A3 A21 2 1 +3VS
22 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 16 Trace width / Spacing = 10 / 10 mil
M4 RSVD[01] FAN_SPEED1 33
N5 RSVD[02] 2
T2 RSVD[03]
V3 C6
RSVD[04]
RESERVED
B2 RSVD[05] 0.01U_0402_16V7K
1 @
D2 RSVD[06]
D22 RSVD[07]
Reserve for D3 RSVD[08]
debug F6 RSVD[09]
close to South
Bridge
Penryn
H_FERR# 2 1
B C596 @ 180P_0402_50V8J B
H_SMI# 2 1
C597 @ 180P_0402_50V8J
H_INIT# 2 1
C598 @ 180P_0402_50V8J
H_NMI 2 1
C599 @ 180P_0402_50V8J
H_A20M# 2 1
C600 @ 180P_0402_50V8J
H_INTR 2 1
C601 @ 180P_0402_50V8J
H_IGNNE# 2 1
C602 @ 180P_0402_50V8J
H_STPCLK# 2 1
C603 @ 180P_0402_50V8J
Reserve for
debug
close to CPU
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 4 of 45
5 4 3 2 1
5 4 3 2 1
@
JCPUD
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
7 H_D#[0..15] @ A16 R5
H_D#[32..47] 7 VSS[005] VSS[086]
JCPUB A19 R22
H_D#0 H_D#32 VSS[006] VSS[087]
E22 D[0]# D[32]# Y22 A23 VSS[007] VSS[088] R25
H_D#1 F24 AB24 H_D#33 AF2 T1
H_D#2 D[1]# D[33]# H_D#34 VSS[008] VSS[089]
E26 D[2]# D[34]# V24 B6 VSS[009] VSS[090] T4
DATA GRP 0
D H_D#3 G22 V26 H_D#35 B8 T23 D
DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VSS[010] VSS[091]
F23 D[4]# D[36]# V23 B11 VSS[011] VSS[092] T26
H_D#5 G25 T22 H_D#37 B13 U3
H_D#6 D[5]# D[37]# H_D#38 VSS[012] VSS[093]
E25 D[6]# D[38]# U25 B16 VSS[013] VSS[094] U6
H_D#7 E23 U23 H_D#39 B19 U21
H_D#8 D[7]# D[39]# H_D#40 VSS[014] VSS[095]
K24 D[8]# D[40]# Y25 B21 VSS[015] VSS[096] U24
H_D#9 G24 W22 H_D#41 B24 V2
H_D#10 D[9]# D[41]# H_D#42 VSS[016] VSS[097]
J24 D[10]# D[42]# Y23 C5 VSS[017] VSS[098] V5
H_D#11 J23 W24 H_D#43 C8 V22
H_D#12 D[11]# D[43]# H_D#44 VSS[018] VSS[099]
H22 D[12]# D[44]# W25 C11 VSS[019] VSS[100] V25
H_D#13 F26 AA23 H_D#45 C14 W1
H_D#14 D[13]# D[45]# H_D#46 VSS[020] VSS[101]
K22 D[14]# D[46]# AA24 C16 VSS[021] VSS[102] W4
H_D#15 H23 AB25 H_D#47 C19 W23
D[15]# D[47]# VSS[022] VSS[103]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 C2 VSS[023] VSS[104] W26
7 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 7 C22 VSS[024] VSS[105] Y3
7 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 7 C25 VSS[025] VSS[106] Y6
7 H_D#[16..31] H_D#[48..63] 7 D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
H_D#16 N22 AE24 H_D#48 D8 AA2
H_D#17 D[16]# D[48]# H_D#49 VSS[028] VSS[109]
K25 D[17]# D[49]# AD24 D11 VSS[029] VSS[110] AA5
H_D#18 P26 AA21 H_D#50 D13 AA8
H_D#19 D[18]# D[50]# H_D#51 VSS[030] VSS[111]
R23 D[19]# D[51]# AB22 Resistor placed within D16 VSS[031] VSS[112] AA11
H_D#20 L23 AB21 H_D#52 D19 AA14
D[20]# D[52]# 0.5" of CPU pin.Trace VSS[032] VSS[113]
DATA GRP 1
H_D#21 M24 AC26 H_D#53 D23 AA16
DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VSS[033] VSS[114]
L22 D[22]# D[54]# AD20 should be at least 25 D26 VSS[034] VSS[115] AA19
H_D#23 M23 AE22 H_D#55 E3 AA22
H_D#24 P25
D[23]# D[55]#
AF23 H_D#56 mils away from any other E6
VSS[035] VSS[116]
AA25
H_D#25 D[24]# D[56]# H_D#57 VSS[036] VSS[117]
P23 D[25]# D[57]# AC25 toggling signal. E8 VSS[037] VSS[118] AB1
H_D#26 P22 AE21 H_D#58 E11 AB4
C H_D#27 T24
D[26]# D[58]#
AD21 H_D#59 COMP[0,2] trace width is E14
VSS[038] VSS[119]
AB8 C
D[27]# D[59]# VSS[039] VSS[120]
+1.05VS Close to H_D#28 R24 D[28]# D[60]# AC22 H_D#60 18 mils. COMP[1,3] trace E16 VSS[040] VSS[121] AB11
CPU pin H_D#29 L25 AD23 H_D#61 E19 AB13
H_D#30 T25
D[29]# D[61]#
AF22 H_D#62 width is 4 mils. E21
VSS[041] VSS[122]
AB16
AD26 D[30]# D[62]# VSS[042] VSS[123]
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 5 of 45
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
Near CPU CORE regulator
330U_X_2VM_R6M 330U_X_2VM_R6M +CPU_CORE
1 1 1 1
D D
+CPU_CORE +CPU_CORE +CPU_CORE
@
JCPUC
A7 AB20 330U_6.3V_M_R15 330U_6.3V_M_R15 1 1 1 1 1 1 1 1
VCC[001] VCC[068] C19 C20 C21 C22 C23 C24 C25 C26
A9 VCC[002] VCC[069] AB7
A10 AC7 1 1 1 1 Place these capacitors on L8
VCC[003] VCC[070] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A12 VCC[004] VCC[071] AC9
+ + + + 2 2 2 2 2 2 2 2
A13 VCC[005] VCC[072] AC12
A15 AC13 C79 C80 C81 C82
VCC[006] VCC[073]
A17 VCC[007] VCC[074] AC15
2 2 2 2 need to change P/N
A18 VCC[008] VCC[075] AC17
+CPU_CORE
A20 VCC[009] VCC[076] AC18
B7 AD7 330U_6.3V_M_R15 330U_6.3V_M_R15
VCC[010] VCC[077]
B9 VCC[011] VCC[078] AD9
B10 VCC[012] VCC[079] AD10 1 1 1 1 1 1 1 1
B12 AD12 reserve for test C27 C28 C29 C30 C31 C32 C33 C34
VCC[013] VCC[080] Place these capacitors on L8
B14 VCC[014] VCC[081] AD14 please co-layout with C7~C10
B15 AD15 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[015] VCC[082] 2 2 2 2 2 2 2 2
B17 VCC[016] VCC[083] AD17
B18 VCC[017] VCC[084] AD18
B20 VCC[018] VCC[085] AE9
C9 VCC[019] VCC[086] AE10
+CPU_CORE
C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17 1 1 1 1 1 1 1 1
C17 AE18 C35 C36 C37 C38 C39 C40 C41 C42
VCC[024] VCC[091] Place these capacitors on L8
C18 VCC[025] VCC[092] AE20
C D9 AF9 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
VCC[026] VCC[093] 2 2 2 2 2 2 2 2
D10 VCC[027] VCC[094] AF10
D12 VCC[028] VCC[095] AF12
D14 VCC[029] VCC[096] AF14
D15 VCC[030] VCC[097] AF15
D17 VCC[031] VCC[098] AF17 Mid Frequence Decoupling
D18 VCC[032] VCC[099] AF18
E7 AF20 +1.05VS
VCC[033] VCC[100]
E9 VCC[034] 4.5A
E10 G21 330U_6.3V_M_R15
VCC[035] VCCP[01]
E12 VCC[036] VCCP[02] V6 1 1 Place these inside socket cavity on L8
E13 J6 +1.05VS (North side Secondary)
VCC[037] VCCP[03] + +
E15 VCC[038] VCCP[04] K6
E17 M6 C43 C146
VCC[039] VCCP[05] @
E18 VCC[040] VCCP[06] J21 1 1 1 1 1 1
2 2 C44 C45 C46 C47 C48 C49
E20 VCC[041] VCCP[07] K21
F7 VCC[042] VCCP[08] M21
F9 N21 330U_X_2VM_R6M 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VCC[043] VCCP[09] 2 2 2 2 2 2
F10 VCC[044] VCCP[10] N6 reserve for test
F12 VCC[045] VCCP[11] R21
F14 VCC[046] VCCP[12] R6
F15 VCC[047] VCCP[13] T21
F17 VCC[048] VCCP[14] T6
F18 VCC[049] VCCP[15] V21
F20 VCC[050] VCCP[16] W21
AA7 VCC[051] Near pin B26
AA9 VCC[052] VCCA[01] B26 +1.5VS
AA10 VCC[053] VCCA[02] C26 1 1
AA12 C51
B VCC[054] C50 B
AA13 VCC[055] VID[0] AD6 CPU_VID0 43
AA15 AF5 CPU_VID1 43 0.01U_0402_16V7K 10U_0805_6.3V6M
VCC[056] VID[1] 2 2
AA17 VCC[057] VID[2] AE5 CPU_VID2 43
AA18 VCC[058] VID[3] AF4 CPU_VID3 43
AA20 VCC[059] VID[4] AE3 CPU_VID4 43
AB9 VCC[060] VID[5] AF3 CPU_VID5 43
AC10 VCC[061] VID[6] AE2 CPU_VID6 43
AB10 VCC[062]
AB12 VCC[063]
AB14 AF7 VCCSENSE VCCSENSE 43
VCC[064] VCCSENSE
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE 43
VCC[067] VSSSENSE
Penryn
.
+CPU_CORE
within 500mils.
H_A#[3..35] 4
5 H_D#[0..63] U3A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
D H_D#7 F6 R16 H_A#11 D
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12
H_D#_33 H_ADS# H_ADS# 4
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
C H_D#36 Y12 A9 C
H_D#_36 H_BNR# H_BNR# 4
HOST
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# 4
H_D#38 Y7 G12
H_D#_38 H_BREQ# H_BR0# 4
H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# 4
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# 4
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK 16
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 16
H_D#43 AA9 J11
H_D#_43 H_DPWR# H_DPWR# 5
H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AD11 H9
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AD10 E12
H_D#_46 H_HITM# H_HITM# 4
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# 4
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# 4
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
Layout Note: AA3 H_D#_52
H_D#53 AD3 J8
H_RCOMP / +H_VREF / H_SWNG H_D#_53 H_DINV#_0 H_DINV#0 5
H_D#54 AD7 L3
H_D#_54 H_DINV#_1 H_DINV#1 5
trace width and spacing is 10/20 H_D#55 AE14 Y13
H_D#_55 H_DINV#_2 H_DINV#2 5
H_D#56 AF3 Y1
H_D#_56 H_DINV#_3 H_DINV#3 5
within 100 mils from NB H_D#57 AC1
H_D#58 H_D#_57
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 5
H_D#59 AC3 M7
+1.05VS +1.05VS H_D#_59 H_DSTBN#_1 H_DSTBN#1 5
H_D#60 AE11 AA5
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5
H_D#61 AE8 AE6
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5
H_D#62 AG2 H_D#_62
1
H_D#63 AD6 L9
H_D#_63 H_DSTBP#_0 H_DSTBP#0 5
R22 M8
B H_DSTBP#_1 H_DSTBP#1 5 B
R21 221_0402_1% AA6
H_DSTBP#_2 H_DSTBP#2 5
1K_0402_1% H_SWNG C5 AE5
H_SWING H_DSTBP#_3 H_DSTBP#3 5
H_SWING=0.3125*VCCP H_RCOMP E3
1 2
2 2 H_CPUSLP#
B6 H_RS#0 4
2
H_RS#_0
H_RS#_1 F12 H_RS#1 4
Near B3 pin +H_VREF A11 C8
H_AVREF H_RS#_2 H_RS#2 4
B11 H_DVREF
CANTIGA ES_FCBGA1329
GM45R3@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 7 of 45
5 4 3 2 1
5 4 3 2 1
1
000 = FSB1067 N36 RSVD2 SA_CK_1 AT21 DDRA_CLK1 14
R33 AV24 R26
RSVD3 SB_CK_0 DDRB_CLK0 15
0 = DMI x 2 T33 AU20 1K_0402_1%
COMPENSATION
RSVD4 SB_CK_1 DDRB_CLK1 15
CFG5 Internal pull-up 1 = DMI x 4 *(Default) AH9 RSVD5
AH10 AR24 DDRA_CLK0# 14
2
RSVD6 SA_CK#_0 +SM_RCOMP_VOH
0 = iTPM Host Interface is enabled can support disble by SW. AH12 RSVD7 SA_CK#_1 AR21 DDRA_CLK1# 14
CFG6 Internal pull-up 1 = iTPM Host Interface is Disabled *(Default) AH13 RSVD8 SB_CK#_0 AU24 DDRB_CLK0# 15
K12 RSVD9 SB_CK#_1 AV20 DDRB_CLK1# 15 1 1
1
0 = Intel Management Engine Crypto Transport Layer Security AL34 2.2U_0603_6.3V6K
RSVD10 C54 C55
AK34 RSVD11 SA_CKE_0 BC28 DDRA_CKE0 14
(TLS) cipher suite with no confidentiality AN35 AY28 DDRA_CKE1 14
0.01U_0402_16V7K R27
D RSVD12 SA_CKE_1 2 2 3.01K_0402_1% D
CFG7 Internal pull-up AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 15 SM_DRAMRST# would be
1 = Intel Management Engine Crypto TLS cipher suite with T24 BB36 DDRB_CKE1 15 needed for DDR3 only
2
RSVD14 SB_CKE_1
confidentiality *(Default) BA17 DDRA_SCS0# 14
SA_CS#_0 +SM_RCOMP_VOL
SA_CS#_1 AY16 DDRA_SCS1# 14
0 = Lane Reversal Enable B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# 15 For Cantiga 80 Ohm
1
CFG9 Internal pull-up 1 = Normal Operation *(Default) B2 RSVD16 SB_CS#_1 AR13 DDRB_SCS1# 15 1 1
RSVD
0 = PCIe Loopback Enable BD17 C56 C57 R28
SA_ODT_0 DDRA_ODT0 14
CFG10 Internal pull-up 1 = Disable*(Default) AY17 0.01U_0402_16V7K 1K_0402_1%
SA_ODT_1 DDRA_ODT1 14 2 2
AY21 BF15 DDRB_ODT0 15
2
RSVD20 SB_ODT_O +1.5V +1.5V
01 = All Z Mode Enabled SB_ODT_1 AY13 DDRB_ODT1 15
CFG[13:12] 00 = Reserved
10 = XOR Mode Enabled BG22 SMRCOMP R29 1 2 80.6_0402_1%
SM_RCOMP
2
Internal pull-up 11 = Normal Operation*(Default) BG23 BH21 SMRCOMP# R30 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R31
BF23 RSVD23
0 = Dynamic ODT Disabled BH18 BF28 +SM_RCOMP_VOH 1K_0402_1%
RSVD24 SM_RCOMP_VOH +SM_RCOMP_VOL
CFG16 Internal pull-up 1 = Dynamic ODT Enabled *(Default) BF18 RSVD25 SM_RCOMP_VOL BH28
20mil
1
0 = Normal Operation AV42 +SM_VREF SM_PWROK R101 1 2
SM_VREF DDR3_SM_PWROK 42
CFG19 Internal pull-down 1 = DMI Lane Reversal Enable SM_PWROK R32 @ 2 0_0402_5% 0_0402_5%
*(Default) SM_PWROK AR36 1
2
BF17 SM_REXT R33 1 2 499_0402_1% 1
SM_REXT R34
CFG20 0 = Only PCIE or [SDVO/DP/HDMI] is operational. * (Default) SM_DRAMRST# BC36 SM_DRAMRST# 14,15
C58
Internal pull-down 1K_0402_1%
(PCIE/SDVO select) 1 = PCIE/[SDVO/DP/HDMI] are operating simu. 0.1U_0402_16V4Z
CLK_DREF_96M 2 @
B38 CLK_DREF_96M 16
1
DPLL_REF_CLK CLK_DREF_96M# CLK_DREF_96M PM@
DPLL_REF_CLK# A38 CLK_DREF_96M# 16 1 2
E41 CLK_DREF_SSC R575 0_0402_5%
DPLL_REF_SSCLK CLK_DREF_SSC 16
F41 CLK_DREF_SSC# CLK_DREF_96M# 1 PM@ 2
DPLL_REF_SSCLK# CLK_DREF_SSC# 16
R576 0_0402_5%
CLK
F43 CLK_DREF_SSC 1 PM@ 2
PEG_CLK CLK_MCH_3GPLL 16
E43 R577 0_0402_5%
C PEG_CLK# CLK_MCH_3GPLL# 16 C
CLK_DREF_SSC# 1 PM@ 2
R578 0_0402_5%
1
R36 2 1 1K_0402_5% MCH_CLKSEL1 R25 AE48 +3VS
5,16 CPU_BSEL1 CFG_1 DMI_RXP_2 DMI_ITX_MRX_P2 21
R37 2 1 1K_0402_5% MCH_CLKSEL2 P25 AH40 R38
5,16 CPU_BSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 21
P20 Lane reversal 1K_0402_5%
T14 PAD CFG_3
T15 PAD P24 CFG_4 DMI_TXN_0 AE35 DMI_MTX_IRX_N0 21
1
R39 2@ 2.21K_0402_1% MCH_CFG_5
DMI
1 C25 AE43 DMI_MTX_IRX_N1 21
2
R40 MCH_CFG_6 CFG_5 DMI_TXN_1
1 2@ 2.21K_0402_1% N24 CFG_6 DMI_TXN_2 AE46 DMI_MTX_IRX_N2 21
R41 R42
R43 1 2@ 2.21K_0402_1% MCH_CFG_7 M24 AH42 54.9_0402_1% 1K_0402_5%
CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 21
2
CFG
B
E21 CFG_8
R44 1 2@ 2.21K_0402_1% MCH_CFG_9 C23 AD35 DMI_MTX_IRX_P0 21
2
CFG_9 DMI_TXP_0
E
R45 1 2@ 2.21K_0402_1% MCH_CFG_10 C24 AE44 MCH_TSATN# 3 1 MCH_TSATN_EC# 33
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 21
C
N21 AF46 Q7
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 21
R46 1 2@ 2.21K_0402_1% MCH_CFG_12 P21 AH43 MMBT3904_SOT23-3
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 21
R47 1 2@ 2.21K_0402_1% MCH_CFG_13 T21 CFG_13
R20 CFG_14
M20 CFG_15
+3VS R48 1 2@ 2.21K_0402_1% MCH_CFG_16 L21 CFG_16
H21 CFG_17
P29
GRAPHICS VID
T16 PAD CFG_18
R49 1 2 4.02K_0402_1% MCH_CFG_19 R28
R50 1 2@ 4.02K_0402_1% MCH_CFG_20 T28
CFG_19
CFG_20 GFX_VID_0 B33 Strap Pin Table
GFX_VID_1 B32
B GFX_VID_2 G33 SDVO_CTRLDATA 0 = SDVO interface disabled *(Default) B
GFX_VID_3 F33 (Internal pull-down) 1 = SDVO interface enabled
23 PM_SYNC# R51 1 2 0_0402_5% PM_SYNC#_R R29 E33
PM_SYNC# GFX_VID_4
+3VS 1 2 PM_EXTTS#_R 5,22,43 H_DPRSTP# B7 PM_DPRSTP# DDPC_CTRLDATA 0 = Digital display (iHDMI/DP) interface disabled
R52 10K_0402_5% (Internal pull-down) 1 = Digital display (iHDMI/DP) interface enabled
N33 PM_EXT_TS#_0 *(Default)
PM
2
BG48 AH37 R57
NC_1 CL_CLK CL_CLK0 23
Use VGATE for GMCH_PWROK BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0 23
ME
1
R58 @ 0_0402_5% NC_4 CL_RST# +CL_VREF R61 PM@
BH47 NC_5 CL_VREF AH34 should be
1 2 BG47 +CL_VREF=0.355V 0_0402_5%
23,33 ICH_PWROK NC_6 0.35 V
2
R59 0_0402_5% BE47 1 R62 PM@
NC_7 C59 R60 0_0402_5%
BH46 NC_8 DDPC_CTRLCLK N28
NC
1
NC_11 SDVO_CTRLDATA +3VS
BH43 NC_12 CLKREQ# K36 CLKREQ_3GPLL# 16
MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 8 of 45
5 4 3 2 1
5 4 3 2 1
D D
14 DDR_A_D[0..63] 15 DDR_B_D[0..63]
U3D U3E
DDR_A_D0 AJ38 BD21 DDR_B_D0 AK47 BC16
SA_DQ_0 SA_BS_0 DDR_A_BS0 14 SB_DQ_0 SB_BS_0 DDR_B_BS0 15
DDR_A_D1 AJ41 BG18 DDR_B_D1 AH46 BB17
SA_DQ_1 SA_BS_1 DDR_A_BS1 14 SB_DQ_1 SB_BS_1 DDR_B_BS1 15
DDR_A_D2 AN38 AT25 DDR_B_D2 AP47 BB33
SA_DQ_2 SA_BS_2 DDR_A_BS2 14 SB_DQ_2 SB_BS_2 DDR_B_BS2 15
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 14 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_B_D5 AJ48 AU17
SA_DQ_5 SA_CAS# DDR_A_CAS# 14 SB_DQ_5 SB_RAS# DDR_B_RAS# 15
DDR_A_D6 AM44 AY20 DDR_B_D6 AM48 BG16
SA_DQ_6 SA_WE# DDR_A_WE# 14 SB_DQ_6 SB_CAS# DDR_B_CAS# 15
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_WE# 15
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 DDR_A_DM[0..7] 14 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
SA_DQ_14 SA_DM_1 SB_DQ_14 DDR_B_DM[0..7] 15
DDR_A_D15 AU42 AY41 DDR_A_DM2 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D16 SA_DQ_15 SA_DM_2 DDR_A_DM3 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AV39 SA_DQ_16 SA_DM_3 AU39 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D17 AY44 BB12 DDR_A_DM4 DDR_B_D17 BC44 BD40 DDR_B_DM2
DDR_A_D18 SA_DQ_17 SA_DM_4 DDR_A_DM5 DDR_B_D18 SB_DQ_17 SB_DM_2 DDR_B_DM3
BA40 SA_DQ_18 SA_DM_5 AY6 BG43 SB_DQ_18 SB_DM_3 BF35
DDR_A_D19 BD43 AT7 DDR_A_DM6 DDR_B_D19 BF43 BG11 DDR_B_DM4
DDR_A_D20 SA_DQ_19 SA_DM_6 DDR_A_DM7 DDR_B_D20 SB_DQ_19 SB_DM_4 DDR_B_DM5
AV41 SA_DQ_20 SA_DM_7 AJ5 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D21 AY43 DDR_B_D21 BC41 AP1 DDR_B_DM6
B
SA_DQ_21 SB_DQ_21 SB_DM_6
A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
SA_DQ_22 DDR_A_DQS[0..7] 14 SB_DQ_22 SB_DM_7
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D23 BF41
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D24 SB_DQ_23
AY37 SA_DQ_24 SA_DQS_1 AT44 BG38 SB_DQ_24 DDR_B_DQS[0..7] 15
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D25 BF38 AL47 DDR_B_DQS0
SA_DQ_25 SA_DQS_2 SB_DQ_25 SB_DQS_0
MEMORY
C DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1 C
MEMORY
AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48
DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4
DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6
DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
BD13 SA_DQ_32 DDR_A_DQS#[0..7] 14 BH14 SB_DQ_32 SB_DQS_7 AN6
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
DDR_A_D34 SA_DQ_33 SA_DQS#_0 SB_DQ_33
BC11 SA_DQ_34 SA_DQS#_1 AT43 DDR_A_DQS#1 DDR_B_D34 BH11 SB_DQ_34 DDR_B_DQS#[0..7] 15
DDR_A_D35 BA12 BA44 DDR_A_DQS#2 DDR_B_D35 BG8 AL46 DDR_B_DQS#0
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0
SYSTEM
DDR_A_D36 BD37 DDR_A_DQS#3 DDR_B_D36 AV47 DDR_B_DQS#1
SYSTEM
DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 9 of 45
5 4 3 2 1
5 4 3 2 1
+3VS U3C
within 500 mils
1 2 1 GM@ 2 LCTLA_CLK L32
R499GM@ 0_0402_5% R64 10K_0402_5% L_BKLT_CTRL PEG_COMP 1
33 UMA_ENBKL G32 L_BKLT_EN PEG_COMPI T37 2 +1.05VS
1 GM@ 2 LCTLB_DATA LCTLA_CLK M32 T36 R65 49.9_0402_1%
R66 10K_0402_5% LCTLB_DATA L_CTRL_CLK PEG_COMPO
GM@ UMA_LCD_EDID_CLK
M33
UMA_LCD_EDID_CLK K33 L_CTRL_DATA 10mils
1 2 18 UMA_LCD_EDID_CLK L_DDC_CLK
R67 2.2K_0402_5% 18 UMA_LCD_EDID_DATA UMA_LCD_EDID_DATAJ33 H44 PCIE_GTX_C_MRX_N0
GM@ UMA_LCD_EDID_DATA UMA_ENVDD L_DDC_DATA PEG_RX#_0 PCIE_GTX_C_MRX_N1
1 2 1 2 18 UMA_ENVDD M29 L_VDD_EN PEG_RX#_1 J46
R500PM@ 0_0402_5% R68 2.2K_0402_5% L44 PCIE_GTX_C_MRX_N2
R69 1 GM@ PEG_RX#_2
2 LVDS_IBG C44 LVDS_IBG PEG_RX#_3 L40 PCIE_GTX_C_MRX_N3
D 2.37K_0402_1% Spacing=20mil B43 N41 PCIE_GTX_C_MRX_N4 D
R501 1 GM@ LVDS_VBG PEG_RX#_4
2 0_0402_5% E37 LVDS_VREFH PEG_RX#_5 P48 PCIE_GTX_C_MRX_N5
L_DDC_DATA R502 1 GM@ 2 0_0402_5% E38 N44 PCIE_GTX_C_MRX_N6
LVDS_VREFL PEG_RX#_6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N[0..15]
PEG_RX#_7 T43 PCIE_GTX_C_MRX_N[0..15] 17
0 = LFP Disable PCIE_GTX_C_MRX_N8
*(Default) 18 UMA_LCD_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P[0..15]
1 = LFP Card Present; PCIE disable 18 UMA_LCD_TXCLK+ C40 LVDSA_CLK PEG_RX#_9 Y43
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P[0..15] 17
18 UMA_LCD_TZCLK- B37 LVDSB_CLK# PEG_RX#_10 Y48
A37 Y36 PCIE_GTX_C_MRX_N11 PCIE_MTX_C_GRX_N[0..15]
18 UMA_LCD_TZCLK+ LVDSB_CLK PEG_RX#_11 PCIE_MTX_C_GRX_N[0..15] 17
LVDS
AA43 PCIE_GTX_C_MRX_N12
R64 PM@ PEG_RX#_12 PCIE_GTX_C_MRX_N13 PCIE_MTX_C_GRX_P[0..15]
18 UMA_LCD_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37 PCIE_MTX_C_GRX_P[0..15] 17
0_0402_5% E46 AC47 PCIE_GTX_C_MRX_N14
18 UMA_LCD_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
R66 PM@ G40 AD39 PCIE_GTX_C_MRX_N15
18 UMA_LCD_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
0_0402_5% A40
R67 PM@ LVDSA_DATA#_3 PCIE_GTX_C_MRX_P0
PEG_RX_0 H43
0_0402_5% H48 J44 PCIE_GTX_C_MRX_P1
18 UMA_LCD_TXOUT0+ LVDSA_DATA_0 PEG_RX_1
R68 PM@ D45 L43 PCIE_GTX_C_MRX_P2
18 UMA_LCD_TXOUT1+ LVDSA_DATA_1 PEG_RX_2
GRAPHICS
0_0402_5% F40 L41 PCIE_GTX_C_MRX_P3
18 UMA_LCD_TXOUT2+ LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
PEG_RX_5 P47
A41 N43 PCIE_GTX_C_MRX_P6
18 UMA_LCD_TZOUT0- LVDSB_DATA#_0 PEG_RX_6
H38 T42 PCIE_GTX_C_MRX_P7
18 UMA_LCD_TZOUT1- LVDSB_DATA#_1 PEG_RX_7
G37 U42 PCIE_GTX_C_MRX_P8
18 UMA_LCD_TZOUT2- LVDSB_DATA#_2 PEG_RX_8
J37 Y42 PCIE_GTX_C_MRX_P9
LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10
PEG_RX_10 W47
B42 Y37 PCIE_GTX_C_MRX_P11
18 UMA_LCD_TZOUT0+ LVDSB_DATA_0 PEG_RX_11
G38 AA42 PCIE_GTX_C_MRX_P12
18 UMA_LCD_TZOUT1+ LVDSB_DATA_1 PEG_RX_12
F37 AD36 PCIE_GTX_C_MRX_P13
18 UMA_LCD_TZOUT2+ LVDSB_DATA_2 PEG_RX_13
K37 AC48 PCIE_GTX_C_MRX_P14
LVDSB_DATA_3 PEG_RX_14 PCIE_GTX_C_MRX_P15
PCI-EXPRESS
PEG_RX_15 AD40
C C
J41 PCIE_MTX_GRX_N0 C611 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
R70 PM@ PEG_TX#_0
1 GM@ 2 TV_COMPS PEG_TX#_1 M46 PCIE_MTX_GRX_N1 C612 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
0_0402_5% R70 75_0402_1% TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C613 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
R71 PM@ TVA_DAC PEG_TX#_2
1 GM@ 2 TV_LUMA TV_LUMA H25 TVB_DAC PEG_TX#_3 M40 PCIE_MTX_GRX_N3 C614 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
0_0402_5% R71 75_0402_1% TV_CRMA K25 M42 PCIE_MTX_GRX_N4 C615 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
R72 PM@ TVC_DAC PEG_TX#_4
1 GM@ 2 TV_CRMA PEG_TX#_5 R48 PCIE_MTX_GRX_N5 C616 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
TV
0_0402_5% R72 75_0402_1% H24 N38 PCIE_MTX_GRX_N6 C617 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C618 1
PEG_TX#_7 T40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
U37 PCIE_MTX_GRX_N8 C619 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PEG_TX#_8 PCIE_MTX_GRX_N9 C620 1
PEG_TX#_9 U40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
C31 Y40 PCIE_MTX_GRX_N10 C621 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C622 1
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
AA37 PCIE_MTX_GRX_N12 C623 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C624 1
PEG_TX#_13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
R73 PM@ 1 2 UMA_CRT_B AD43 PCIE_MTX_GRX_N14 C625 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
0_0402_5% R73 GM@ 150_0402_1% PEG_TX#_14 PCIE_MTX_GRX_N15 C626 1
PEG_TX#_15 AC46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
R74 PM@ 1 2 UMA_CRT_G
0_0402_5% R74 GM@ 150_0402_1% UMA_CRT_B E28 J42 PCIE_MTX_GRX_P0 C627 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
19 UMA_CRT_B CRT_BLUE PEG_TX_0
R75 PM@ 1 2 UMA_CRT_R L46 PCIE_MTX_GRX_P1 C628 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
0_0402_5% R75 GM@ 150_0402_1% UMA_CRT_G PEG_TX_1 PCIE_MTX_GRX_P2 C629
19 UMA_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
M39 PCIE_MTX_GRX_P3 C630 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PEG_TX_3
VGA
UMA_CRT_R J28 M43 PCIE_MTX_GRX_P4 C631 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
19 UMA_CRT_R CRT_RED PEG_TX_4
R47 PCIE_MTX_GRX_P5 C632 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
+3VS PEG_TX_5 PCIE_MTX_GRX_P6 C633
G29 CRT_IRTN PEG_TX_6 N37 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
T39 PCIE_MTX_GRX_P7 C634 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
UMA_CRT_CLK UMA_CRT_CLK PEG_TX_7 PCIE_MTX_GRX_P8 C635
1 2 19 UMA_CRT_CLK H32 CRT_DDC_CLK PEG_TX_8 U36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
R76 GM@ 4.7K_0402_5% UMA_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C636 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
19 UMA_CRT_DATA CRT_DDC_DATA PEG_TX_9
R78 PM@ 1 2 UMA_CRT_DATA UMA_CRT_HSYNC J29 Y39 PCIE_MTX_GRX_P10 C637 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
B 19 UMA_CRT_HSYNC CRT_HSYNC PEG_TX_10 B
0_0402_5% R77 GM@ 4.7K_0402_5% 2 1UMA_CRT_IREF E29 Y46 PCIE_MTX_GRX_P11 C638 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
R78 GM@ 1.02K_0402_1% CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C639
PEG_TX_12 AA36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
1 2 UMA_CRT_HSYNC AA39 PCIE_MTX_GRX_P13 C640 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
R503 PM@ 0_0402_5% UMA_CRT_VSYNC L29 PEG_TX_13 PCIE_MTX_GRX_P14 C641
19 UMA_CRT_VSYNC CRT_VSYNC PEG_TX_14 AD42 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
1 2 UMA_CRT_VSYNC AD46 PCIE_MTX_GRX_P15 C642 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
R504 PM@ 0_0402_5% PEG_TX_15
CANTIGA ES_FCBGA1329
GM45R3@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 10 of 45
5 4 3 2 1
5 4 3 2 1
U3F
DDR3,1066MHz,4140mA +NB_VCCAXG
VCC_AXG_NTCF_1 W28
+1.5V AP33 V28
VCC_SM_1 VCC_AXG_NCTF_2
DDR PWR AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26
10U_0805_10V4Z BH32 V26 VCC CORE (Core+IMEL+HSIO)
VCC_SM_3 VCC_AXG_NCTF_4
BG32 W25
BF32
VCC_SM_4 VCC_AXG_NCTF_5
V25
W/Ext GFX: 3060mA
VCC_SM_5 VCC_AXG_NCTF_6
1 BD32 VCC_SM_6 VCC_AXG_NCTF_7 W24 W/Int GFX: 2400mA
1 1 1 BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
D + BB32 W23 +1.05VS NB Core,Intel Management Engine Link U3G D
VCC_SM_8 VCC_AXG_NCTF_9
VCC
C78 C69 C70 C71 BA32 V23
VCC_SM_9 VCC_AXG_NCTF_10 220U_6.3V_M_R15 0.22U_0402_10V4Z 0.1U_0402_16V4Z
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21 AG34 VCC_1
2 2 2 2
AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21 1 1 AC34 VCC_2
330U_6.3V_M_R15 AV32 AK21 1 1 1 1 AB34
VCC_SM_12 VCC_AXG_NCTF_13 + + VCC_3
AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21 AA34 VCC_4
10U_0805_10V4Z 0.1U_0402_16V4Z AT32 V21 C72 C73 C74 C75 C76 C77 Y34
SM
VCC_SM_14 VCC_AXG_NCTF_15 GM@ VCC_5
AR32 U21 V34
VCC CORE
VCC_SM_15 VCC_AXG_NCTF_16 2 2 2 2 2 2 VCC_6
AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20 U34 VCC_7
AN32 AK20 220U_6.3V_M_R15 10U_0805_10V4Z 0.22U_0402_10V4Z AM33
VCC_SM_17 VCC_AXG_NCTF_18 VCC_8
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 Intel: VCC -- 220U*2, ESR 12mOhm AK33 VCC_9
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AJ33 VCC_10
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AG33 VCC_11
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AF33 VCC_12
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
BD29 VCC_SM_25 VCC_AXG_NCTF_26 AG19 AE33 VCC_13
BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19 AC33 VCC_14
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 AA33 VCC_15
BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19 Y33 VCC_16
AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19 W33 VCC_17
GFX NCTF
POWER
AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19 V33 VCC_18
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 U33 VCC_19
AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19 AH28 VCC_20
AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19 AF28 VCC_21
AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17 AC28 VCC_22
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AA28 VCC_23
VCC_AXG_NCTF_37 AH17 AJ26 VCC_24
VCC_AXG_NCTF_38 AG17 AG26 VCC_25
VCC_AXG_NCTF_39 AF17 AE26 VCC_26
BA36 VCC_SM_36/NC VCC_AXG_NCTF_40 AE17 AC26 VCC_27
C
BB24 AC17 AH25 +1.05VS C
VCC_SM_37/NC VCC_AXG_NCTF_41 VCC_28
VCC
BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17 AG25 VCC_29
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AF25 VCC_30
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 AG24 VCC_31 VCC_NCTF_1 AM32
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AJ23 VCC_32 VCC_NCTF_2 AL32
AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16 AH23 VCC_33 VCC_NCTF_3 AK32
VCC_AXG_NCTF_47 AL16 AF23 VCC_34 VCC_NCTF_4 AJ32
AK16 T32 AH32
POWER
VCC_AXG_NCTF_48 VCC_35 VCC_NCTF_5
VCC_AXG_NCTF_49 AJ16 VCC_NCTF_6 AG32
VCC_AXG_NCTF_50 AH16 VCC_NCTF_7 AE32
9600mA VCC_AXG_NCTF_51 AG16 VCC_NCTF_8 AC32
VCC_AXG_NCTF_52 AF16 VCC_NCTF_9 AA32
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_10 Y32
AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16 VCC_NCTF_11 W32
For layout placement un-mound C123 and mound C84 AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16 VCC_NCTF_12 U32
AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16 VCC_NCTF_13 AM30
Int. Graphic AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_14 AL30
AC24 VCC_AXG_6 VCC_AXG_NCTF_58 W16 VCC_NCTF_15 AK30
+1.05VS +NB_VCCAXG AA24 V16 AH30
VCC_AXG_7 VCC_AXG_NCTF_59 VCC_NCTF_16
Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16 VCC_NCTF_17 AG30
10U_0805_10V4Z 0.47U_0603_10V7K 0.1U_0402_16V4Z AE23 AF30
VCC_AXG_9 VCC_NCTF_18
1 AC23 VCC_AXG_10 VCC_NCTF_19 AE30
1 1 1 1 1 1 AB23 AC30
NCTF
+ VCC_AXG_11 VCC_NCTF_20
AA23 VCC_AXG_12 VCC_NCTF_21 AB30
C225 C85 C86 C87 C88 C89 C90 AJ21 AA30
220U_6.3V_M_R15 GM@ GM@ GM@ GM@ GM@ GM@ VCC_AXG_13 VCC_NCTF_22
AG21 VCC_AXG_14 VCC_NCTF_23 Y30
2 GM@ 2 2 2 2 2 2
AE21 VCC_AXG_15 VCC_NCTF_24 W30
10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z AC21 V30
VCC_AXG_16 VCC_NCTF_25
AA21 VCC_AXG_17 VCC_NCTF_26 U30
VCC
Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm Y21 VCC_AXG_18 VCC_NCTF_27 AL29
VCC
VCC_AXG_41 VCC_SM_LF1
PJ30 T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
1 1 2 2 VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5 CANTIGA ES_FCBGA1329
JUMP_43X39 @ PAD T3 AJ14 AM10 VCCSM_LF6 GM45R3@
VCC_AXG_SENSE VCC_SM_LF6
PJ31 PAD T4 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7
1 1 C93 1 1 C95 1 1 C96 1
1 2 0.22U_0603_10V7K 0.47U_0603_10V7K 1U_0402_6.3V4Z
1 2
JUMP_43X39 @ C91 C92 C94 C97
0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.22U_0603_10V7K 2 2 1U_0402_6.3V4Z 2
A PJ32 A
1 2 CANTIGA ES_FCBGA1329
1 2 GM45R3@
JUMP_43X39 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 11 of 45
5 4 3 2 1
5 4 3 2 1
CRT
D 10U_0805_10V4Z 10U_0805_10V4Z D
2 1 2 1 +3VS_TVCRT_DACBG A25 VCCA_DAC_BG VTT_7 U10
10U_FLC-453232-100K_0.25A_10%
1 10U_FLC-453232-100K_0.25A_10%
1 T10 Intel: VTT 270U*1 ESR 12mOhm
C110 PM@ C112 PM@ VTT_8
1 1 1 1 B25 VSSA_DAC_BG VTT_9 U9
C108 + 0_0805_5% C109 + 0_0805_5% T9
220U_B2_2.5VM C110 C111 220U_B2_2.5VM C112 C113 VTT_10
VTT_11 U8
@ GM@ GM@ Pin F47 @ GM@ GM@ Pin L48 T8
2 2 2 2 2 2 VTT_12
VTT
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS_DPLLA F47 VCCA_DPLLA64.8mA VTT_13 U7
VTT_14 T7
+1.05VS_DPLLB L48 VCCA_DPLLB64.8mA VTT_15 U6
VTT_16 T6
PLL
+1.05VS +1.05VS_AHPLL +1.05VS +1.05VS_MPLL +1.05VS_AHPLL AD1 VCCA_HPLL 24mA VTT_17 U5
VTT_18 T5
R83 R84 +1.8V_TXLVDS
+1.05VS_MPLL AE1 VCCA_MPLL 139.2mA VTT_19 V3
2 1 2 1 LVDS VTT_20 U3
KC FBM-L11-160808-121LMT
1 0603 1 MBK2012121YZF_0805 1 1 13.2mA V2
VTT_21
A PEG A LVDS
1 2 C117 +1.8V_TXLVDS J48 U2
C115 C116 C114 R85 0.5_0805_1% C118 C118 PM@ VCCA_LVDS VTT_22
VTT_23 T2
4.7U_0805_10V4Z 10U_0805_10V4Z Pin AE12 1000P_0402_50V7K 0_0402_5% J47 V1
2 0.1U_0402_16V4Z
2 2 GM@ VSSA_LVDS VTT_24
Pin J48 VTT_25 U1
+1.05VS
Pin AD1 0.1U_0402_16V4Z GND to J47 414uA +1.05VS_AXF
+1.5VS_PEG_BG AD48 NB I/O R86
VCCA_PEG_BG
1 2
2 1 0_0603_5%
+1.5VS_PEG_BG +1.05VS_PEGPLL
50mA C119
PCIe&DMI +1.05VS_PEGPLL AA48 C120
VCCA_PEG_PLL 1U_0402_6.3V4Z 10U_0805_10V4Z
1 2 @
+1.5VS 1 2 1
R87 0_0603_5% 1 DDR3,1066MHz,747.5mA
C121 Pin B22
C122 0.1U_0402_16V4Z DDR3,800MHz,575mA
0.1U_0402_16V4Z
2
2
PCIe&DMI AR20 VCCA_SM_1
POWER
Pin AD48 Pin AA48 DDR3 +1.05VS_A_SM AP20 VCCA_SM_2 +1.5V_SM_CK
C +1.05VS AN20 DDR2 +1.5V C
R88 VCCA_SM_3 R89
AR17 VCCA_SM_4 Host Interface I/O and HSIO
A SM
1 2 4.7U_0805_10V4Z AP17 440mA 1 2
VCCA_SM_5
1 0_0805_5% 1 1 1 AN17 VCCA_SM_6 VCC_AXF_1 B22 +1.05VS_AXF 1 1 0_0805_5%
AXF
AT16 VCCA_SM_7 VCC_AXF_2 B21
C123 + C124 C125 C126 AR16 A21 C127 R90 C128
220U_D2_4VM_R15 VCCA_SM_8 VCC_AXF_3 0.1U_0402_16V4Z 1_0805_1% 10U_0805_10V4Z
AP16 VCCA_SM_9
@ 2 2 2 2 2 @
2
DDR3,1066MHz,149.5mA C129
10U_0805_10V4Z 1U_0402_6.3V4Z Pin BF21
Pin AR20 DDR3,800MHz,143.75mA 1 2
VCC_SM_CK_1 BF21 +1.5V_SM_CK
SM CK
DDR3,1066MHz,37.95mA BH20 10U_0805_10V4Z
VCC_SM_CK_2
BG20
DDR3 DDR3,800MHz,28.75mA VCC_SM_CK_3
BF20 +1.8V_TXLVDS +1.8V
+1.05VS +1.05VS_A_SM_CK VCC_SM_CK_4 R91 GM@
AP28 VCCA_SM_CK_1 LVDS
R92 AN28 1 2
0.1U_0402_16V4Z VCCA_SM_CK_2
11 2 AP25 VCCA_SM_CK_3 1 1 0_0603_5%
0_0603_5% 1 1 1 AN25 118.8mA
C155 VCCA_SM_CK_4 C130 PM@ C130 C131
AN24 VCCA_SM_CK_5 VCC_TX_LVDS K47 +1.8V_TXLVDS
A CK
1U_0402_6.3V4Z C132 C133 C134 AM28 0_0402_5% 1000P_0402_50V7K 10U_0805_10V4Z
2 VCCA_SM_CK_NCTF_1 2 GM@ 2 GM@
AM26 VCCA_SM_CK_NCTF_2
10U_0805_10V4Z 2 2
2.2U_0603_6.3V4Z 2
AM25 105.3mA Pin K47
VCCA_SM_CK_NCTF_3
+3VS_TVCRT_DAC AL25 VCCA_SM_CK_NCTF_4 VCC_HV_1 C35 +3VS
TV +1.5VS +1.5VS_HDA Pin AP28 AM24 B35
VCCA_SM_CK_NCTF_5 VCC_HV_2
HV
R94 HDMI's HDA AL24 A35
0.01U_0402_25V4Z VCCA_SM_CK_NCTF_6 VCC_HV_3 D3
1 2 AM23 VCCA_SM_CK_NCTF_7
1 1 0_0402_5% 1 AL23 +3VS 2 R93 1 1 2 +1.05VS
IHDMI@ VCCA_SM_CK_NCTF_8 10_0603_5%
1782mA 1
C135 C136 C138 V48 +1.05VS C137 CH751H-40PT_SOD323-2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC_PEG_1 0.1U_0402_16V4Z
2 2
Pin B24 Pin A32 VCC_PEG_2 U48
IHDMI@ 2
PEG
VCC_PEG_3 V47
2
Pin C35
B
79mA VCC_PEG_4 U47
B
B24 VCCA_TV_DAC_1 VCC_PEG_5 U46
+3VS_TVCRT_DAC A24 VCCA_TV_DAC_2
TV
+1.5VS +1.5VS_TVDAC +1.5VS +1.5VS_QDAC
50mA 456mA
R95 TV R96 TV +1.5VS_HDA A32 AH48 +1.05VS
VCC_HDA VCC_DMI_1 +1.05VS
HDA
2 1 0.1U_0402_16V4Z 2 1 0.01U_0402_25V4Z AF48 PCIe&DMI
VCC_DMI_2
DMI
0_0603_5% 1 1 1 0_0603_5% 1 1 AH47
VCC_DMI_3 10U_0805_10V4Z
VCC_DMI_4 AG47
C139 C140 C141 C142 C143 35mA 1 1
@ 10U_0805_10V4Z Pin M25 0.1U_0402_16V4Z Pin L282 +1.5VS_TVDAC M25
2 2 2 2 VCCD_TVDAC
D TV/CRT
C144 C145
0.01U_0402_25V4Z +1.5VS_QDAC L28 VCCD_QDAC500uA 2
10U_0805_10V4Z 2
157.2mA Pin V48
+1.05VS_DHPLL AF1 VCCD_HPLL
50mA A8 VTTLF1
+1.05VS +1.05VS_DHPLL VTTLF1 VTTLF2
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VTTLF2 L1
VTTLF
R98
VTTLF3 AB2 VTTLF3 +1.05VS PCIe&DMI
1 2 60.31mA 1 1 1
0_0402_5% 2 M38 VCCD_LVDS_1
LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 12 of 45
5 4 3 2 1
5 4 3 2 1
U3I U3J
VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1
VSS SCB
VSS_82 VSS_181 VSS_280 VSS_SCB_4
U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46
NC
VSS_97 VSS_196 VSS_295 NC_35
AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
GM45R3@ NC_40
NC_41 C48
NC_42 B48
CANTIGA ES_FCBGA1329
GM45R3@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 13 of 45
5 4 3 2 1
5 4 3 2 1
+V_DDR3_DIMM_REF
1
JDDRL
2
DDR3 SO-DIMM A DDR_A_DQS[0..7] 9
DDR_A_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_A_D4
DDR_A_D5
REVERSE TYPE DDR_A_DQS#[0..7] 9
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
5 DQ0 DQ5 6
1 1 DDR_A_D1 7 8 DDR_A_D[0..63] 9
DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10
CD1
CD2
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0 DDR_A_DM[0..7] 9
13 VSS VSS 14
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16 DDR_A_MA[0..14] 9
DDR_A_D3 17 18 DDR_A_D7
DQ3 DQ7
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D 23 DQ9 DQ13 24 D
25 VSS VSS 26
close to JDDRH.1 DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS1# DM1
29 DQS1 RESET# 30 SM_DRAMRST# 8,15 +1.5V
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
1
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20 RD1
DDR_A_D17 DQ16 DQ20 DDR_A_D21 1K_0402_1%
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46 DDR_A_DM2
2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48 +V_DDR3_DIMM_REF
49 50 DDR_A_D22
VSS DQ22
1
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23 RD2
53 DQ19 VSS 54
55 56 DDR_A_D28 1K_0402_1%
DDR_A_D24 VSS DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60
2
DQ25 VSS DDR_A_DQS#3
61 VSS DQS3# 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_MA10 107 108 1 1
A10/AP BA1 DDR_A_BS1 9
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
9 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 9 1 1 1 1 1 1 1 1 1 1
CD13
CD14
CD15
CD16
+ CD17 + CD45
CD7
CD8
CD9
CD10
CD11
CD12
111 VDD VDD 112
113 114 @
9 DDR_A_WE# WE# S0# DDRA_SCS0# 8
9 DDR_A_CAS# 115 CAS# ODT0 116 DDRA_ODT0 8 2 2 2 2 2 2 2 2 2 2 2 2
117 VDD VDD 118
DDR_A_MA13 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDRA_ODT1 8
8 DDRA_SCS1# 121 S1# NC 122
123 124 RD4
VDD VDD +DDR_VREF_CA_DIMMA 330U_B2_2.5VM_R15M
125 TEST VREF_CA 126 1 2
127 128 0_0402_5% reserve for test
DDR_A_D32 VSS VSS DDR_A_D36
129 DQ32 DQ36 130
DDR_A_D33 DDR_A_D37
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
131 DQ33 DQ37 132
133 VSS VSS 134
B DDR_A_DQS#4 DDR_A_DM4 B
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1
DQS4 VSS DDR_A_D38
139 VSS DQ38 140 CD4 Layout Note:
CD3
DDR_A_D34 141 142 DDR_A_D39
DDR_A_D35 DQ34 DQ39 Place near JDDRL.203 & JDDRL.204
143 DQ35 VSS 144
DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5 +0.75VS
153 DM5 DQS5 154 close to JDDRH.126
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS VSS 162
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DDR_A_D48 163 164 DDR_A_D52
DQ48 DQ52
10U_0805_6.3V6M
DDR_A_D49 165 166 DDR_A_D53 1 1 1 1 1
DQ49 DQ53
CD22
167 VSS VSS 168
DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
DDR_A_D54 2 2 2 2 2
173 VSS DQ54 174
CD18
CD19
CD20
CD21
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55
177 DQ51 VSS 178
179 180 DDR_A_D60
DDR_A_D56 VSS DQ60 DDR_A_D61
181 DQ56 DQ61 182
DDR_A_D57 183 184
DQ57 VSS DDR_A_DQS#7
185 VSS DQS7# 186
DDR_A_DM7 187 188 DDR_A_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62
A DQ58 DQ62 A
DDR_A_D59 193 194 DDR_A_D63
RD3 1 DQ59 DQ63
2 195 VSS VSS 196
10K_0402_5% 197 198
SA0 EVENT# PM_EXTTS# 8,15
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 15,16,23,27
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
203 204
1 1 +0.75VS VTT VTT +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
1
CD6
CD5 205 206 2009/07/22 2012/07/22 Title
GND1 BOSS1 Issued Date Deciphered Date
RD5
2 2
207 GND2 BOSS2 208
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2
FOX_AS0A626-U2RN-7F B
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 14 of 45
5 4 3 2 1
A B C D E
+V_DDR3_DIMM_REF
1
JDDRH
2
DDR3 SO-DIMM B DDR_B_DQS[0..7] 9
DDR_B_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_B_D4
DDR_B_D5
REVERSE TYPE DDR_B_DQS#[0..7] 9
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
5 DQ0 DQ5 6
1 1 DDR_B_D1 7 8 DDR_B_D[0..63] 9
DQ1 VSS DDR_B_DQS#0
9 VSS DQS0# 10
CD23
CD24
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0 DDR_B_DM[0..7] 9
13 VSS VSS 14
2 2 DDR_B_D2 DDR_B_D6
15 DQ2 DQ6 16 DDR_B_MA[0..14] 9
DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7
19 VSS VSS 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
1 23 DQ9 DQ13 24 1
25 VSS VSS 26
close to JDDRL.1 DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1
29 DQS1 RESET# 30 SM_DRAMRST# 8,14
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_MA10 107 108 1
A10/AP BA1 DDR_B_BS1 9
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
9 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 9 1 1 1 1 1 1 1 1 1 1
CD38
CD37
CD36
CD35
+ CD39
CD29
CD30
CD31
CD32
CD33
CD34
111 VDD VDD 112
113 114 330U_B2_2.5VM_R15M
9 DDR_B_WE# WE# S0# DDRB_SCS0# 8
115 116 @
9 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 8 2 2 2 2 2 2 2 2 2 2 2
117 VDD VDD 118
DDR_B_MA13 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDRB_ODT1 8
8 DDRB_SCS1# 121 S1# NC 122
123 124 RD7
VDD VDD +DDR_VREF_CA_DIMMB
125 TEST VREF_CA 126 1 2
127 128 0_0402_5%
DDR_B_D32 VSS VSS DDR_B_D36
129 DQ32 DQ36 130
DDR_B_D33 DDR_B_D37
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
131 DQ33 DQ37 132
133 VSS VSS 134
3 DDR_B_DQS#4 DDR_B_DM4 3
135 DQS4# DM4 136
DDR_B_DQS4 137 138 1 1
DQS4 VSS DDR_B_D38
139 VSS DQ38 140 CD28 Layout Note:
CD27
DDR_B_D34 141 142 DDR_B_D39
DDR_B_D35 DQ34 DQ39 Place near JDDRH.203 & JDDRH.204
143 DQ35 VSS 144
DDR_B_D44 2 2
145 VSS DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5 +0.75VS
153 DM5 DQS5 154 close to JDDRL.126
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DDR_B_D48 163 164 DDR_B_D52
DQ48 DQ52
10U_0805_6.3V6M
DDR_B_D49 165 166 DDR_B_D53 1 1 1 1 1
DQ49 DQ53
CD44
167 VSS VSS 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
DDR_B_D54 2 2 2 2 2
173 VSS DQ54 174
CD40
CD41
CD42
CD43
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS 178
179 180 DDR_B_D60
DDR_B_D56 VSS DQ60 DDR_B_D61
181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS DDR_B_DQS#7
185 VSS DQS7# 186
DDR_B_DM7 187 188 DDR_B_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
4 DQ58 DQ62 4
DDR_B_D59 193 194 DDR_B_D63
RD8 1 DQ59 DQ63
2 195 VSS VSS 196
10K_0402_5% 197 198
SA0 EVENT# PM_EXTTS# 8,14
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 14,16,23,27
1 RD9
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
+1.05VS_CK505 +3VS_CK505
R108 80mA R107 250mA
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS +3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 0_0805_5% 1
C213
1
C214
1
C215
1
C216
1
C217
1
C218
1
C219
0_0805_5% 1
C206
1
C207
1
C208
1
C209
1
C210
1
C211
1
C212
13 PCI_1 SRC_9 44
R115 1 2 33_0402_5% CLK_DDR 14 45
34 CLK_PCI_DDR PCI_2 SRC_9#
3 R129 1 3
2 33_0402_5% CLK_CARDBUS 15 PCI_3
31 CLK_PCI_PCM
SRC_10 50
R113 1 2 33_0402_5% CLK_EC 16
33 CLK_PCI_EC PCI_4/SEL_LCDCL
SRC_10# 51
R112 1 2 33_0402_5% CLK_ICH 17
21 CLK_PCI_ICH PCIF_5/ITP_EN
SRC_11 48
18 VSS_PCI SRC_11# 47
+3VS
3 VSS_REF
CLKREQ_SATA# CLKREQ_SATA#
0 = SRC8/SRC8# (100MHz) 22 VSS_48 CLKREQ_3# 37 CLKREQ_SATA# 23 2
R125
1
10K_0402_5%
CLK_ICH CLKREQ_WLAN# CLKREQ_WLAN#
1 = ITP/ITP# (266MHz) 26 VSS_IO CLKREQ_4# 41 CLKREQ_WLAN# 27 2
R124
1
10K_0402_5%
CLKREQ_NEW# CLKREQ_NEW#
0 = Enable DOT96 & SRC1(UMA) 69 VSS_CPU CLKREQ_6# 58 CLKREQ_NEW# 27 2
R119
1
10K_0402_5%
CLK_EC CLKREQ_3GPLL# CLKREQ_3GPLL#
1 = Enable SRC0 & 27MHz(DIS) 30 VSS_PLL3 CLKREQ_7# 65 CLKREQ_3GPLL# 8 2
R118
1
10K_0402_5%
34 43 CLKREQ_9 CLKREQ_9 2 1
VSS_SRC CLKREQ_9# R123 10K_0402_5%
59 49 CLKREQ_10 CLKREQ_10 2 1
+3VS +3VS VSS_SRC SLKREQ_10# R126 10K_0402_5%
42 46 CLKREQ_11 CLKREQ_11 2 1
VSS_SRC CLKREQ_11# R120 10K_0402_5%
1
73 THERMAL_PAD USB_1/CLKREQ_A# 21
R121 R122
10K_0402_5% 10K_0402_5%
4 4
@ PM@ SLG8SP556VTR_QFN72_10X10
2
CLK_ICH CLK_EC
1
R127 R128
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
GM@ 2009/07/22 2012/07/22 Title
Issued Date Deciphered Date
SCHEMATIC MB A4982
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 16 of 45
A B C D E F G H
5 4 3 2 1
PCIE_MTX_C_GRX_N[0..15] PCIE_GTX_C_MRX_N[0..15]
10 PCIE_MTX_C_GRX_N[0..15] 10 PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_P[0..15]
10 PCIE_MTX_C_GRX_P[0..15] 10 PCIE_GTX_C_MRX_P[0..15]
D D
JMXMA JMXMB
@ @
160mil(4A) L28 2 1 B+
KC FBM-L11-201209-221LMAT_0805
PM@ 2 160mil(4A) 1 1
L27 2 1 C222 C482 C483
KC FBM-L11-201209-221LMAT_0805 PM@ PM@ PM@
1 1 PM@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C224 C223 1
0.1U_0603_25V7K 2 2
PM@ PM@
680P_0402_50V7K 68P_0402_50V8J
2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 17 of 45
5 4 3 2 1
5 4 3 2 1
LCD/PANEL BD. Conn. please link to VGA Conn. then link to LVDS Conn.
1
LCD_TXOUT0+ 0_0402_5% 2 GM@ 1 R629
+3VS 17 LCD_TXOUT0+ UMA_LCD_TXOUT0+ 10
R621 R622 LCD_TXOUT0- 0_0402_5% 2 GM@ 1 R631
17 LCD_TXOUT0- UMA_LCD_TXOUT0- 10
150_0603_5% 100K_0402_5% W=60mils LCD_TXOUT1+ 0_0402_5% 2 GM@ 1 R633
17 LCD_TXOUT1+ UMA_LCD_TXOUT1+ 10
LCD_TXOUT1- 0_0402_5% 2 GM@ 1 R635
17 LCD_TXOUT1- UMA_LCD_TXOUT1- 10
6 2
2
D 2 D
C853 LCD_TXOUT2+ 0_0402_5% 2 GM@ 1 R637
17 LCD_TXOUT2+ UMA_LCD_TXOUT2+ 10
0.1U_0402_16V7K LCD_TXOUT2- 0_0402_5% 2 GM@ 1 R639
17 LCD_TXOUT2- UMA_LCD_TXOUT2- 10
3
S
Q17A Inrush current = 0A
2N7002DW-T/R7_SOT363-6 1 G
Q18 LCD_TXCLK+ 0_0402_5%
2 1 2 2 17 LCD_TXCLK+ 2 GM@ 1 R641 UMA_LCD_TXCLK+ 10
R623 47K_0402_5% 2 AO3413_SOT23 LCD_TXCLK- 0_0402_5% 2 GM@ 1 R643
17 LCD_TXCLK- UMA_LCD_TXCLK- 10
3
D
1
C671 +LCD_VDD
0.01U_0402_25V7K W=60mils LCD_TZOUT0+ 0_0402_5% 2 GM@ 1 R645
1 17 LCD_TZOUT0+ UMA_LCD_TZOUT0+ 10
UMA_ENVDD 1 2 ENVDD 5 LCD_TZOUT0- 0_0402_5% 2 GM@ 1 R647
10 UMA_ENVDD 17 LCD_TZOUT0- UMA_LCD_TZOUT0- 10
R624 GM@ 0_0402_5% Q17B
VGA_ENVDD 1 2 2N7002DW-T/R7_SOT363-6 1 1 LCD_TZOUT1+ 0_0402_5% 2 GM@ 1 R649
17 VGA_ENVDD 17 LCD_TZOUT1+ UMA_LCD_TZOUT1+ 10
4
1
R625 PM@ 0_0402_5% LCD_TZOUT1- 0_0402_5% 2 GM@ 1 R651
17 LCD_TZOUT1- UMA_LCD_TZOUT1- 10
C672 C673
R626 4.7U_0805_10V4Z 0.1U_0402_16V4Z LCD_TZOUT2+ 0_0402_5% 2 GM@ 1 R653
17 LCD_TZOUT2+ UMA_LCD_TZOUT2+ 10
100K_0402_5% @ 2 2 LCD_TZOUT2- 0_0402_5% 2 GM@ 1 R655
17 LCD_TZOUT2- UMA_LCD_TZOUT2- 10
2
LCD_TZCLK+ 0_0402_5% 2 GM@ 1 R657
17 LCD_TZCLK+ UMA_LCD_TZCLK+ 10
LCD_TZCLK- 0_0402_5% 2 GM@ 1 R659
17 LCD_TZCLK- UMA_LCD_TZCLK- 10
2 2 2
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 18 of 45
5 4 3 2 1
A B C D E
1
D55 D56 D57 D58 +CRT_VCC_R +CRT_VCC
2 F3 30mil
1 1 2
3 RB491D_SOT23-3 1.1A_6V_MINISMDC110F-2 1
+3VS If=1A
DAN217_SC59 DAN217_SC59 DAN217_SC59 C679
3
@ @ @ @ 0.1U_0402_16V4Z
2
JCRT
L18 6
CRT_R CRT_R_L 6
10 UMA_CRT_R 1 2 1 2 11 11
1 R664 GM@ 0_0402_5% NBQ100505T-800Y_0402 CRT_R_L 1 1
1
17 VGA_CRT_R 1 2 7 7
R665 PM@ 0_0402_5% L19 CRT_DDC_DAT 12
CRT_G CRT_G_L CRT_G_L 12
10 UMA_CRT_G 1 2 1 2 2 2
R666 GM@ 0_0402_5% NBQ100505T-800Y_0402 8
HSYNC 8
17 VGA_CRT_G 1 2 13 13
R667 PM@ 0_0402_5% L20 CRT_B_L 3
CRT_B CRT_B_L 3
10 UMA_CRT_B 1 2 1 2 +CRT_VCC 9 9
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
R668 GM@ 0_0402_5% NBQ100505T-800Y_0402 VSYNC 14 16
14 G
17 VGA_CRT_B 1 2 4 4 G 17
150_0402_1%
150_0402_1%
150_0402_1%
R669 PM@ 0_0402_5% 1 1 1 1 1 1 10 10
1
CRT_DDC_CLK 15
R670 R671 R672 C680 C681 C682 C683 C684 C685 15
5 5
2 2 2 2 2 2 ALLTO_C10532-11505-L_15P-T
@
2
+CRT_VCC +3VS
1 2 2 1
C686 0.1U_0402_16V4Z R673 10K_0402_5%
5
1
1
R685 R674 +CRT_VCC
P
OE#
1 2 CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC 0_0402_5% 0_0402_5%
10 UMA_CRT_HSYNC A Y
R675 GM@ 0_0402_5% L21 10_0402_5%
G
U38
2
1 2 SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC 1 2 VSYNC
17 VGA_CRT_HSYNC
3
2 R676 PM@ 0_0402_5% L22 10_0402_5% R677 R678 2
10P_0402_50V8J
10P_0402_50V8J
4.7K_0402_5% 4.7K_0402_5%
2
+CRT_VCC Q19A
1 1
1
C687 C688 10 UMA_CRT_DATA 1 2 CRT_DATA 1 6 CRT_DDC_DAT
5
1
@ @ R679 GM@ 0_0402_5%
5
2 2 Q19B 2N7002DW-T/R7_SOT363-6
17 VGA_CRT_DATA 1 2
P
OE#
1 2 CRT_VSYNC 2 4 R680 PM@ 0_0402_5%
10 UMA_CRT_VSYNC A Y
R681 GM@ 0_0402_5% 10 UMA_CRT_CLK 1 2 CRT_CLK 4 3 CRT_DDC_CLK
U39 G R682 GM@ 0_0402_5% 1 1
1 2 SN74AHCT1G125GW_SOT353-5 17 VGA_CRT_CLK 1 2 1 1 2N7002DW-T/R7_SOT363-6
17 VGA_CRT_VSYNC
3
3 3
4 4
+3VS OE 2 R144 1
10K_0402_5% 2 HDMI@ 1 +3VS
IHDMI@ RV67 0_0402_5%
+3VS
1 1 1 1 1 1 1 1
C242 C243 C244 C245 C246 C247 C248 C249 U7
IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
2 2 2 2 2 2 2 2 +3VS OE
OE* 25 VGA_HDMI_CLK 17
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R141
G
20K_0402_5% 2
IHDMI@ VCC3V HDMI_SCLK
11 VCC3V SCL_SINK 28 1 3
2
15 Q48
2
PCIE_GTX_C_MRX_HDMI_P3 VCC3V Q47 BSH111_SOT23-3
G
21 VCC3V SDA_SINK 29
D 26 BSH111_SOT23-3 HDMI@ D
VCC3V
1
33 HDMI_SDATA HDMI@ 1 3 VGA_HDMI_DATA 17
R145 VCC3V
40 VCC3V HPD_SINK 30
PMEG2010AEH_SOD123 H@ F2 H@ 7.5K_0402_1% HDMI_HPD_R
S
46 VCC3V
+5VS 2 1 2 1 +HDMI_5V_OUT IHDMI@ 32 R147 2 1 4.7K_0402_5% +3VS
D53 1.1A_6V_MINISMDC110F-2 DDC_EN IHDMI@
1
2
C250
H@ +3VS R148 1 2 @ 0_0402_5% 3 34 R149 2 1 0_0402_5% @
0.1U_0402_16V4Z R150 FUNCTION1 FUNCTION3
1 2 @ 0_0402_5% 4 FUCNTION2 FUNCTION4 35 R151 2 1 0_0402_5% @ +3VS
2 R152 1 IHDMI@ 2 0_0402_5% R153 1 2 0_0402_5% IHDMI@
R154 1 IHDMI@ 2 0_0402_5% R155 1 2 0_0402_5% IHDMI@
2 R156 1 6
4.12K_0402_1% IHDMI@ ANALOG1(REXT)
10 PCIE_GTX_C_MRX_HDMI_P3 7 HPD_SOURCE
2
36 H@ R572 C659
GND
1
37 0.1U_0402_16V4Z U37 100K_0402_5% H@
GND 1 H@
4 3 43
OE#
4 3 GND HDMI_HPD_R 1
2 A Y 4
H@ OCE2012120YZF_0805 0.1U_0402_16V4Z
1
G
VGA_DVI_TXD1+ 1 2 R176 HDMI_R_D1+ STHDLS101TQTR QFN 48P HDMI SHIFTER_QFN48_7X7 74AHCT1G125GW_SOT353-5
@ 0_0402_5% IHDMI@ H@
3
VGA_DVI_TXD2- 1 2 R177 HDMI_R_D2-
@ 0_0402_5%
L12
1 1 2 2
B B
4 3
VGA_DVI_TXD2+
4
H@ OCE2012120YZF_0805
3
HDMI_R_CK+ 1 HDMI@ 2
HDMI Connector
1 2 R178 HDMI_R_D2+ R690 499_0402_1%
@ 0_0402_5% HDMI_R_CK- 1 HDMI@ 2 JHDMI
R691 499_0402_1% HDMI_HPD 19
CV164 1 HP_DET
17 VGA_HDMI_CLK- 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC- HDMI_R_D1- 1 HDMI@ 2 +HDMI_5V_OUT 18 +5V
CV165 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0- R692 499_0402_1% 17
17 VGA_HDMI_TX0- DDC/CEC_GND
CV166 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1- HDMI_R_D1+ 1 HDMI@ 2 HDMI_SDATA 16
17 VGA_HDMI_TX1- SDA
CV167 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2- R693 499_0402_1% HDMI_SCLK 15
17 VGA_HDMI_TX2- SCL +HDMI_5V_OUT
HDMI_R_D0- 1 HDMI@ 2 14
CV168 1 Reserved
17 VGA_HDMI_CLK+ 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC+ R694 499_0402_1% 13 CEC
CV169 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0+ HDMI_R_D0+ 1 HDMI@ 2 HDMI_R_CK- 12 20 HDMI_SCLK 1 R262 2
17 VGA_HDMI_TX0+ CK- GND
CV170 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1+ R695 499_0402_1% 11 21 H@ 2.2K_0402_5%
17 VGA_HDMI_TX1+ CK_shield GND
CV171 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2+ HDMI_R_D2+ 1 HDMI@ 2 HDMI_R_CK+ 10 22
17 VGA_HDMI_TX2+ CK+ GND
R696 499_0402_1% HDMI_R_D0- 9 23 HDMI_SDATA 1 R290 2
HDMI_R_D2- 1 HDMI@ 2 D0- GND H@ 2.2K_0402_5%
8 D0_shield
R697 499_0402_1% HDMI_R_D0+ 7 D0+
1
D HDMI_R_D1- 6 D1-
+5VS 2 Q20 5
G 2N7002_SOT23-3 HDMI_R_D1+ D1_shield
4 D1+
S HDMI@ HDMI_R_D2- 3
3
D2-
1 @ 2 2 D2_shield
R698 100K_0402_5% HDMI_R_D2+ 1 D2+
@ TYCO_1939864-1_19P
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 20 of 45
5 4 3 2 1
5 4 3 2 1
PCI_CBE#[0..3] PCI_CBE#[0..3] 31
+3VS
31 PCI_AD[0..31]
U9B
PCI_AD0 D11 F1 PCI_REQ#0
PCI_AD1 AD0 REQ0# RP15
C8 AD1 GNT0# G4 PCI_GNT#0 23
PCI_AD2 PCI_REQ#1 PCI_REQ#0
PCI_AD3
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7
PCI_REQ#1 31
PCI_REQ#1
1
2
8
7
AD3 GNT1#/GPIO51 PCI_GNT#1 31
PCI_AD4 E9 F13 PCI_REQ#2 PCI_REQ#2 3 6
PCI_AD5 AD4 REQ2#/GPIO52 PCI_REQ#3
C9 AD5 GNT2#/GPIO53 F12 4 5
PCI_AD6 E10 E6 PCI_REQ#3
PCI_AD7 AD6 REQ3#/GPIO54 8.2K_0804_8P4R_5%
B7 AD7 GNT3#/GPIO55 F6 STRAP_A16 23
PCI_AD8 C7 RP16
PCI_AD9 AD8 PCI_IRDY#
D C5 AD9 C/BE0# D8 PCI_CBE#0 31 1 8 D
PCI_AD10 G11 B4 PCI_CBE#1 31 PCI_DEVSEL# 2 7
PCI_AD11 AD10 C/BE1# PCI_PERR#
F8 AD11 C/BE2# D6 PCI_CBE#2 31 3 6
PCI_AD12 F11 A5 PCI_CBE#3 31 PCI_PLOCK# 4 5
PCI_AD13 AD12 C/BE3#
E7 AD13
PCI_AD14 A3 D3 PCI_IRDY# PCI_IRDY# 31 8.2K_0804_8P4R_5%
PCI_AD15 AD14 IRDY# RP17
D2 AD15 PAR E3 PCI_PAR 31
PCI_AD16 F10 R1 PCI_SERR# 1 8
AD16 PCIRST# PCI_RST# 31
PCI_AD17 D5 C6 PCI_DEVSEL# PCI_DEVSEL# 31 PCI_STOP# 2 7
PCI_AD18 AD17 DEVSEL# PCI_PERR# PCI_TRDY#
D10 AD18 PERR# E4 3 6
PCI_AD19 B3 C2 PCI_PLOCK# PCI_FRAME# 4 5
PCI_AD20 AD19 PLOCK# PCI_SERR#
F7 AD20 SERR# J4
PCI_AD21 C3 A4 PCI_STOP# PCI_STOP# 31 8.2K_0804_8P4R_5%
PCI_AD22 AD21 STOP# PCI_TRDY#
F3 AD22 TRDY# F5 PCI_TRDY# 31
PCI_AD23 F4 D7 PCI_FRAME# PCI_FRAME# 31
PCI_AD24 AD23 FRAME#
C1 AD24
PCI_AD25 G7 C14
AD25 PLTRST# PLT_RST# 8,17,27,28,33,34 C257
PCI_AD26 H7 D4 CLK_PCI_ICH R179
AD26 PCICLK CLK_PCI_ICH 16
PCI_AD27 D1 R2 CLK_PCI_ICH 2 1 1 2
PCI_AD28 AD27 PME# @ 10_0402_5%
G5 AD28
PCI_AD29 H6 @ 10P_0402_50V8J
PCI_AD30 AD29
G1 AD30
PCI_AD31 H3 AD31
+3VS +3VS
RP18 RP19
1 8 PCI_PIRQA# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# PCI_PIRQE# 1 8
31 PCI_PIRQA# PIRQA# PIRQE#/GPIO2
2 7 PCI_PIRQB# PCI_PIRQB# E1 K6 PCI_PIRQF# PCI_PIRQF# 2 7
PCI_PIRQC# PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG# PCI_PIRQG#
3 6 J6 PIRQC# PIRQG#/GPIO4 F2 3 6
C 4 5 PCI_PIRQD# PCI_PIRQD# C4 G2 PCI_PIRQH# PCI_PIRQH# 4 5 C
PIRQD# PIRQH#/GPIO5
8.2K_0804_8P4R_5% ICH9-M ES_FCBGA676 8.2K_0804_8P4R_5%
ICH9R3@
U9D
27 PCIE_IRX_C_NEWTX_N1 N29 PERN1 DMI0RXN V27 DMI_MTX_IRX_N3 8
For Express 27 PCIE_IRX_C_NEWTX_P1
C258 2
N28 PERP1 DMI0RXP V26 DMI_MTX_IRX_P3 8
27 PCIE_ITX_C_NEWRX_N1 1 0.1U_0402_16V7K NEW@ PCIE_ITX_NEWRX_N1 P27 PETN1 DMI0TXN U29 DMI_ITX_MRX_N3 8
Card C259 2 1 0.1U_0402_16V7K NEW@ PCIE_ITX_NEWRX_P1 P26 U28
PCI - Express
28 PCIE_IRX_C_LANTX_N3 J29 PERN3 DMI2RXN AB27 DMI_MTX_IRX_N1 8
For LAN 28 PCIE_IRX_C_LANTX_P3
C262 2
J28 PERP3 DMI2RXP AB26 DMI_MTX_IRX_P1 8
28 PCIE_ITX_C_LANRX_N3 1 0.1U_0402_16V7K PCIE_ITX_LANRX_N3 K27 PETN3 DMI2TXN AA29 DMI_ITX_MRX_N1 8
28 PCIE_ITX_C_LANRX_P3 C263 2 1 0.1U_0402_16V7K PCIE_ITX_LANRX_P3 K26 AA28
PETP3 DMI2TXP DMI_ITX_MRX_P1 8
CH751H-40PT_SOD323-2
1 R133 2
Security Classification Compal Secret Data Compal Electronics, Inc.
0_0402_5% 2009/07/22 2012/07/22 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 21 of 45
5 4 3 2 1
5 4 3 2 1
D D
+RTCBATT C270
12P_0402_50V8J
1
2 1
10M_0402_5%
D10 32.768KHZ_12.5P_MC-306 X1
1
BAS40-04_SOT23-3 3 NC 4
OUT
R189
+RTCVCC
2 1
3
NC IN
+CHGRTC
1 C272 U9A
2
12P_0402_50V8J ICH_RTCX1 C23 K5
RTCX1 FWH0/LAD0 LPC_AD0 33,34
C271 2 1 ICH_RTCX2 C24 K4
RTCX2 FWH1/LAD1 LPC_AD1 33,34
0.1U_0402_16V4Z L6
2 FWH2/LAD2 LPC_AD2 33,34
ICH_RTCRST# A25 K2
RTCRST# FWH3/LAD3 LPC_AD3 33,34
ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST#
CMOS Setting, near DDR Door J1
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 33,34
RTC
LPC
+RTCVCC R190 1 2 ICH_RTCRST# 1 2 B22 J3
23 ICH_INTVRMEN INTVRMEN LDRQ0#
20K_0402_5% SHORT PADS A22 J1
23 LAN100_SLP LAN100_SLP LDRQ1#/GPIO23
C273 1 2 GATEA20 1 2 +3VS
1U_0402_6.3V6K E25 N7 GATEA20 R191 @ 10K_0402_5%
GLAN_CLK A20GATE GATEA20 33
AJ27 H_DPRSTP# 2 1 +1.05VS
A20M# H_A20M# 4
C13 R192 @ 56_0402_5%
LAN_RSTSYNC H_FERR#
ITPM Setting, near DDR Door J2 DPRSTP# AJ25 H_DPRSTP# 5,8,43 2
R193
1
56_0402_5%
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# 5
R194 1 2ICH_SRTCRST# 1 2 G13
20K_0402_5% SHORT PADS LAN_RXD1 FERR# R195 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5%H_FERR# H_FERR# 4
LAN / GLAN
C274 1 2
C 1U_0402_6.3V6K D13 AD22 C
LAN_TXD_0 CPUPWRGD H_PWRGOOD 5
D12 LAN_TXD_1
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# 4
R196 1 2 SM_INTRUDER# KB_RST# R197 2 @ 1 10K_0402_5% +3VS
1M_0402_5% B10 AE22
GPIO56 INIT# H_INIT# 4
AG25
CPU
INTR H_INTR 4
+1.5VS 1 R198 2 GLAN_COMP B28 GLAN_COMPI RCIN# L3 KB_RST#
KB_RST# 33 2 1 +1.05VS
29 AZ_BITCLK_HD R200 1 2 33_0402_5% 24.9_0402_1% B27 +1.05VS 1 2 R199
R202 1 GLAN_COMPO
26 AZ_BITCLK_MD 2 33_0402_5%MDC@ NMI AF23 H_NMI 4
R201 330_0402_5%
2
B
8 AZ_BITCLK_MCH R203 1 2 33_0402_5%IHDMI@ AZ_BITCLK AF6 AF24 56_0402_5% @
HDA_BIT_CLK SMI# H_SMI# 4
AZ_SYNC AH4 HDA_SYNC
C
AH27 H_THERMTRIP# 3 1 2SC2411K_SOT23
STPCLK# H_STPCLK# 4
29 AZ_SYNC_HD R205 1 2 33_0402_5% AZ_RST# AE7 Q10 @
R206 1 HDA_RST#
26 AZ_SYNC_MD 2 33_0402_5%MDC@ THRMTRIP# AG26 THRMTRIP_ICH# 1 2 H_THERMTRIP#
H_THERMTRIP# 4,8
8 AZ_SYNC_MCH R207 1 2 33_0402_5%IHDMI@ AZ_SYNC 29 AZ_SDIN0_HD AF4 R208 54.9_0402_1%
HDA_SDIN0 TP12
26 AZ_SDIN1_MD AG4 HDA_SDIN1 TP12 AG27 PAD T5
1
8 AZ_SDIN2_MCH AH3 HDA_SDIN2
R209 1 2 33_0402_5% AE5 D50
IHDA
29 AZ_RST_HD# HDA_SDIN3
26 AZ_RST_MD# R210 1 2 33_0402_5%MDC@ AH11 DAN202UT106_SC70-3
SATA4RXN SATA_IRX_C_DTX_N4 25
8 AZ_RST_MCH# R211 1 2 33_0402_5%IHDMI@ AZ_RST# AZ_SDOUT AG5 AJ11 @
23 AZ_SDOUT HDA_SDOUT SATA4RXP SATA_IRX_C_DTX_P4 25
SATA4TXN AG12 SATA_ITX_DRX_N4 25 SATA ODD
AG7 AF12 SATA_ITX_DRX_P4 25
3
R212 1 HDA_DOCK_EN#/GPIO33 SATA4TXP
29 AZ_SDOUT_HD 2 33_0402_5% AE8 HDA_DOCK_RST#/GPIO34
26 AZ_SDOUT_MD R213 1 2 33_0402_5%MDC@
8 AZ_SDOUT_MCH R214 1 2 33_0402_5%IHDMI@ AZ_SDOUT SATA_LED# AG8 ENTRIP1 38,40
35 SATA_LED# SATALED#
SATA5RXN AH9 SATA_IRX_C_DTX_N5 25
AJ16 SATA0RXN SATA5RXP AJ9 SATA_IRX_C_DTX_P5 25 eSATA
AH16 SATA0RXP SATA5TXN AE10 SATA_ITX_DRX_N5 25 ENTRIP2 38,40
AF17 SATA0TXN SATA5TXP AF10 SATA_ITX_DRX_P5 25
B B
AG17 SATA0TXP
+3VS 1 2 SATA_LED# AH18
SATA_CLKN CLK_PCIE_SATA# 16
SATA
R215 10K_0402_5% 25 SATA_IRX_C_DTX_N1 AH13 AJ18
SATA1RXN SATA_CLKP CLK_PCIE_SATA 16
25 SATA_IRX_C_DTX_P1 AJ13 SATA1RXP SATARBIAS# AJ7
1ST HDD AG14 AH7 SATARBIAS
25 SATA_ITX_DRX_N1 SATA1TXN SATARBIAS
25 SATA_ITX_DRX_P1 AF14 SATA1TXP
2
R216
10mils width
ICH9-M ES_FCBGA676 24.9_0402_1% less than
ICH9R3@
500mils
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 22 of 45
5 4 3 2 1
5 4 3 2 1
2
4.7K_0402_5% 2 1
R226 for EMI request
1 6 ICH_SMBDATA
14,15,16,27 PM_SMBDATA
CLK_14M_ICH 1 2 1 2
5
U9C R228 C276
Q4A ICH_SMBCLK @ 10_0402_5% @ 4.7P_0402_50V8C
G16 SMBCLK SATA0GP/GPIO21 AH23 SPK_SEL 29
2N7002DW-T/R7_SOT363-6 4 ICH_SMBCLK ICH_SMBDATA BIOS need to CLK_48M_ICH
14,15,16,27 PM_SMBCLK 3
LINKALERT#
A13 SMBDATA SMB SATA1GP/GPIO19 AF19 1
R229
2 1
C277
2
SATA
GPIO
E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21 BT_PWR# 26 set GPIO
D 2N7002DW-T/R7_SOT363-6 ME_EC_CLK1 C17 AD20 @ 10_0402_5% @ 4.7P_0402_50V8C D
Q4B SMLINK0 SATA5GP/GPIO37 BT_RST# 26
+3V_SB R230 1 2 10K_0402_5% LINKALERT# ME_EC_DATA1 B18
R232 10K_0402_5% ME_EC_CLK1 SMLINK1
1 2 CLK14 H1 CLK_14M_ICH CLK_14M_ICH 16
R233 10K_0402_5% ME_EC_DATA1 ICH_RI# AF3 CLK_48M_ICH
R234
1
1
2
2 10K_0402_5% ICH_RI#
F19 RI# clocks CLK48 CLK_48M_ICH 16
S4_STATE# 1 2 +3V_SB
R236 1 2 10K_0402_5% XDP_DBRESET# R4 P1 R235 @ 10K_0402_5%
XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK ICH_LOW_BAT#
4 XDP_DBRESET# G19 SYS_RESET# 2 1
+3V_SB R238 1 2 10K_0402_5% EC_LID_OUT# C16 R237 8.2K_0402_5%
SLP_S3# PM_SLP_S3# 33
8 PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# 33
+3VS R240 1 2 8.2K_0402_5% PM_CLKRUN# G17
SYS / GPIO
SLP_S5# PM_SLP_S5# 33
33 EC_LID_OUT# EC_LID_OUT# A17 2 R239 1 1 R275 2 +3V_SB
SMBALERT#/GPIO11 S4_STATE# 0_0402_5% @ 1K_0402_5%
S4_STATE#/GPIO26 C10
R242 1 2 1K_0402_5% SB_WAKE# A14 SB_RSMRST# 1 Q11 3
C
+3V_SB 16 H_STP_PCI# STP_PCI# EC_RSMRST# 33
E19 G20 ICH_PWROK 1 2
E
16 H_STP_CPU# STP_CPU# PWROK
+3VS R244 1 2 10K_0402_5% SERIRQ R241 MMBT3906_SOT23-3
R245 1 2 @ 8.2K_0402_5% EC_THERM# PM_CLKRUN# L4 M2 10K_0402_5%
B
31 PM_CLKRUN#
Power MGT
PM_DPRSLPVR 8,43
2
CLKRUN# DPRSLPVR/GPIO16
THRM# not 1 2 +3V_SB
+3VS R246 1 2 10K_0402_5% OCP# used, 8.2K to 27,33 SB_WAKE# SB_WAKE# E20 B13 ICH_LOW_BAT# R243
WAKE# BATLOW#
1
31,33,34 SERIRQ SERIRQ M5 4.7K_0402_5%
ICH_ACIN 10K PU to EC_THERM# SERIRQ D11B D11A
+3VS 1 2 33 EC_THERM# AJ23 THRM# PWRBTN# R3 PBTN_OUT# 33
R248 330K_0402_5% +3VS. BAV99DW-7_SOT363 BAV99DW-7_SOT363
1 2 VGATE D21 D20 1 2
33,35,37 ACIN 8,33,43 VGATE VRMPWRGD LAN_RST#
D12 CH751H-40PT_SOD323-2 R247 0_0402_5%
PAD TP11 A20 D22 SB_RSMRST#
T6
6
R250 1 8.2K_0402_5% EC_SMI# TP11 RSMRST#
2 2 1
+3V_SB
R251 1 2 10K_0402_5% EC_SCI#
4 OCP#
OCP#
ICH_ACIN
AG19 GPIO1 CK_PWRGD R5 CK_PWRGD 16
R249
2.2K_0402_5%
RSMRST# circuit
AH21 GPIO6
+3VS 1 R807 2 100K_0402_5% 2HDD_DET# AG21 GPIO7 CLPWROK R6 ICH_PWROK
ICH_PWROK 8,33
33 EC_SMI# EC_SMI# A21
C EC_SCI# GPIO8 +3VS C
33 EC_SCI# C12 GPIO12 SLP_M# B16
17,20 VGA_HDMI_HPD C21 GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 8
1
R253 1 2 8.2K_0402_5% BT_DET# K1 B19
GPIO
+3VS
Controller Link
2HDD_DET# GPIO18 CL_CLK1 R252
AF8 GPIO20
BT_DET# AJ22 F22 3.24K_0402_1%
26 BT_DET# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 8
+3V_SB R255 2 1 @ 10K_0402_5% GPIO57 A9 C19
R257 2 100K_0402_5% GPIO27 CL_DATA1
1 D19
2
GPIO28
16 CLKREQ_SATA# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25 +CL_VREF0_ICH
AE19 SLOAD/GPIO38 CL_VREF1 A19 Width:Spacing
1
+3VS 1 R809 2 100K_0402_5% CIR_EN# CIR_EN# AG22 12mil:12mil 2
SDATAOUT0/GPIO39 R254
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 8
AH24 D18 453_0402_1% C278
GPIO57 GPIO49 CL_RST1# 0.1U_0402_16V4Z
A8 GPIO57/CLGPIO5 1
A16
2
SB_SPKR MEM_LED/GPIO24 SUS_PWR_ACK 1
29 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18 2 +3V_SB
iTPM Physical Presence AJ24 C11 R256 10K_0402_5%
MISC
8 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_TP3 B21 C20
TP8 TP3 WOL_EN/GPIO9
Assert = iTPM Physical Presence Enable T7 PAD AH20 TP8
CLGPIO5 TP9 AJ20 SUS_PWR_ACK Mobile Platform used only
De-assert = iTPM disable T8 PAD
TP10 TP9
Mobil Platform T9 PAD AJ21 TP10
**Only used in iAMT w/ME Firmware
GPIO57 Desktop Platform used only ICH9-M ES_FCBGA676 GPIO10 Desktop Platform used only
ICH9R3@
B
ICH9M Strap Pin Internal TPM Strap(Internal pull-down) Internal VR Enable Strap B
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) Flash Descriptor Security Override Strap
+3VS 1 2 ICH_SPI_MOSI 21 SPI_MOSI Low= Disable
R258 @ 1K_0402_5% Low= Descriptor Security override
High= iTPM enable by MCH strap*
Low = Internal VR Disabled GPIO33 High= Default* (Internal pull-up)
ICH_INTVRMEN High = Internal VR Enabled(Default)
No Reboot Strap (Internal pull-up)
+RTCVCC 1 2 ICH_INTVRMEN 22
+3VS 1 2 SB_SPKR SB_SPKR Low= *Default R259 330K_0402_5%
R261 @ 1K_0402_5% 1 2 ICH8M LAN100 SLP Strap
High= "No Reboot" R260 @ 0_0402_5%
LAN100_SLP 22
DMI Termination Voltage
(Internal VR for VccLAN1.05 and VccCL1.05) GPIO49 Low= Desktop used
High= Mobile* (Internal pull-up)
Boot BIOS Strap (Internal pull-up) Low = Internal VR Disabled
ICH_LAN100_SLP High = Internal VR Enabled(Default)
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
1 2 PCI_GNT#0 21
R263 @ 1K_0402_5%
0 0 RESERVED
1
R265
2
@ 1K_0402_5%
SPI_CS#1 21 0 1 SPI
1 0 PCI XOR Chain Entrance Strap
1 1 LPC* (Default) ICH_TP3 HDA_SDOUT Description
(Internal pull-up) (Internal pull-down)
0 0 RSVD
A16 Swap Override Strap +3VS
R266 @ 1K_0402_5%
AZ_SDOUT 22 0 1 Enter XOR Chain
A 1 2 STRAP_A16 21 A
R267 @ 1K_0402_5% Low= A16 swap override Enable 1 0 Normal Operation (Default)
PCI_GNT#3 ICH_TP3
High= Default* (Internal pull-up) R268 @ 1K_0402_5% 1 1 Set PCIE port config bit 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 23 of 45
5 4 3 2 1
5 4 3 2 1
U9F
U9E
+RTCVCC A23 VCCRTC6uA at G3 state VCC1_05[01] A15 +1.05VS
1 1 1 VCC1_05[02] B15 1 1 AA26 VSS[001] VSS[107] H5
+ICH_V5REF A6 2mA C15 AA27 J23
C279 C280 C281 V5REF VCC1_05[03] C282 C283 VSS[002] VSS[108]
VCC1_05[04] D15 AA3 VSS[003] VSS[109] J26
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
2 2 2 +ICH_V5REF_SUS VCC1_05[05] 2 2 VSS[004] VSS[110]
AE1 V5REF_SUS 2mA VCC1_05[06] F15 AB1 VSS[005] VSS[111] AC22
VCC1_05[07] L11 AA23 VSS[006] VSS[112] K28
AA24 VCC1_5_B[01] 646mA 1634mA VCC1_05[08] L12 AB28 VSS[007] VSS[113] K29
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB29 VSS[008] VSS[114] L13
D13 AB24 L16 AB4 L15
CH751H-40PT_SOD323-2 VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AB5 VSS[010] VSS[116] L2
+3VS 2 1 AC24 VCC1_5_B[05] VCC1_05[12] L18 AC17 VSS[011] VSS[117] L26
PJ37 AC25 M11 +1.5VS_DMIPLL_ICH +1.5VS AC26 L27
+ICH_V5REF VCC1_5_B[06] VCC1_05[13] VSS[012] VSS[118]
2 2 1 1 +5VS 2 1 AD24 VCC1_5_B[07] VCC1_05[14] M18 AC27 VSS[013] VSS[119] L5
R269 1 0.01U_0402_16V7K L13 1
CORE
D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 AC3 VSS[014] VSS[120] L7 D
JUMP_43X39 @ 100_0402_5% AE25 P18 1 MBK1608121YZF_0603 AD1 M12
C284 VCC1_5_B[09] VCC1_05[16] VSS[015] VSS[121]
AE26 VCC1_5_B[10] VCC1_05[17] T11 AD10 VSS[016] VSS[122] M13
2N7002DW-T/R7_SOT363-6 1U_0402_6.3V4Z AE27 T18 C285 C286 AD12 M14
2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[017] VSS[123]
+5V_SB 1 6 +5VALW AE28 VCC1_5_B[12] VCC1_05[19] U11 AD13 VSS[018] VSS[124] M15
Q16A 2
AE29 VCC1_5_B[13] VCC1_05[20] U18 AD14 VSS[019] VSS[125] M16
33,36 SBPWR_EN# STAR@ F25 V11 AD17 M17
Q16B VCC1_5_B[14] VCC1_05[21] VSS[020] VSS[126]
G25 V12 AD18 M23
2
VCCA3GP
47K_0402_5% J25 V18 1 AD4 N12
VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
1 R594 2 STAR@ +5V_SB 2 1 +ICH_V5REF_SUS K24 VCC1_5_B[20] AD5 VSS[026] VSS[132] N13
330K_0402_5% R270 2 K25 C287 AD6 N14
@ 100_0402_5% VCC1_5_B[21] 4.7U_0805_10V4Z VSS[027] VSS[133]
L23 VCC1_5_B[22] AD7 VSS[028] VSS[134] N15
C289 2
1 2 L24 VCC1_5_B[23] 23mA VCCDMIPLL R29 AD9 VSS[029] VSS[135] N16
C851 STAR@ 1U_0402_6.3V4Z L25 AE12 N17
0.1U_0402_25V6 1 VCC1_5_B[24] VSS[030] VSS[136]
M24 VCC1_5_B[25] W23 AE13 N18
M25 VCC1_5_B[26] 48mA VCC_DMI[1]
VCC_DMI[2] Y23 +1.05VS AE14
VSS[031]
VSS[032]
VSS[137]
VSS[138] N26
N23 VCC1_5_B[27] AE16 VSS[033] VSS[139] N27
SBPWR_EN# 1 R597 2 +5VALW N24 AB23 AE17 P12
47K_0402_5% VCC1_5_B[28] V_CPU_IO[1] VSS[034] VSS[140]
N25 VCC1_5_B[29] 2mA V_CPU_IO[2] AC23 1 1 1 AE2 VSS[035] VSS[141] P13
STAR@ P24 AE20 P14
+1.5VS_PCIE_ICH VCC1_5_B[30] C290 C291 C292 VSS[036] VSS[142]
P25 VCC1_5_B[31] AG29 AE24 P15
R24 VCC1_5_B[32] 308mAVCC3_3[01]
VCC3_3[02] AJ6 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z AE3
VSS[037]
VSS[038]
VSS[143]
VSS[144] P16
+1.5VS L14 2 1 10U_0805_10V4Z 2.2U_0603_6.3V6K R25 AC10 AE4 P17
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[33] VCC3_3[07] VSS[039] VSS[145]
1 R26 VCC1_5_B[34] AE6 VSS[040] VSS[146] P2
1 1 1 R27 VCC1_5_B[35] VCC3_3[03] AD19 AE9 VSS[041] VSS[147] P23
VCCP_CORE
+ T24 AF20 +3VS AF13 P28
C293 C294 C295 C296 VCC1_5_B[36] VCC3_3[04] VSS[042] VSS[148]
T27 VCC1_5_B[37] VCC3_3[05] AG24 AF16 VSS[043] VSS[149] P29
220U_6.3V_M_R15 T28 AC20 close to AG29 close to AG24 AF18 P4
2 2 10U_0805_10V4Z
2 2 VCC1_5_B[38] VCC3_3[06] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[044] VSS[150]
T29 VCC1_5_B[39] AF22 VSS[045] VSS[151] P7
C
U24 VCC1_5_B[40] 1 1 1 1 1 1 1 AH26 VSS[046] VSS[152] R11 C
U25 B9 C297 AF26 R12
VCC1_5_B[41] VCC3_3[08] C298 C299 C300 C301 C302 C303 VSS[047] VSS[153]
V24 VCC1_5_B[42] VCC3_3[09] F9 AF27 VSS[048] VSS[154] R13
V25 G3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF5 R14
+1.5VS +1.5VS_SATAPLL_ICH VCC1_5_B[43] VCC3_3[10] 2 2 2 2 2 2 2 VSS[049] VSS[155]
U23 VCC1_5_B[44] VCC3_3[11] G6 AF7 VSS[050] VSS[156] R15
PCI
W24 VCC1_5_B[45] VCC3_3[12] J2 AF9 VSS[051] VSS[157] R16
L15 1 2 W25 J7 close to AD19 close to B9, G6, K7 close to AJ6 AG13 R17
MBK1608121YZF_0603 VCC1_5_B[46] VCC3_3[13] VSS[052] VSS[158]
1 1 K23 VCC1_5_B[47] VCC3_3[14] K7 AG16 VSS[053] VSS[159] R18
Y24 +ICH_HDA AG18 R28
C304 C305 VCC1_5_B[48] NIHDMI@ VSS[054] VSS[160]
Y25 VCC1_5_B[49] AG20 VSS[055] VSS[161] T12
10U_0805_10V4Z 1U_0402_6.3V4Z 11mA AJ4 R271 0_0603_5% +3VS AG23 T13
2 2 VCCHDA VSS[056] VSS[162]
1 +1.5VS AG3 VSS[057] VSS[163] T14
47mA 11mA AJ3 R272 0_0603_5% AG6 T15
VCCSUSHDA C306 IHDMI@ VSS[058] VSS[164]
AJ19 VCCSATAPLL AG9 VSS[059] VSS[165] T16
0.1U_0402_16V4Z AH12 T17
2 VSS[060] VSS[166]
1342mA VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T10 AH14 VSS[061] VSS[167] T23
+1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T11 AH17 VSS[062] VSS[168] B26
1 1 AD15 VCC1_5_A[02] AH19 VSS[063] VSS[169] U12
AD16 +ICH_SUSHDA AH2 U13
C307 C308 VCC1_5_A[03] NIHDMI@ VSS[064] VSS[170]
AE15 VCC1_5_A[04] VCCSUS1_5[1] AD8 AH22 VSS[065] VSS[171] U14
ARX
1U_0402_6.3V4Z 1U_0402_6.3V4Z AF15 R273 0_0603_5% +3V_SB AH25 U15
2 2 VCC1_5_A[05] VSS[066] VSS[172]
AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 +VCCSUS1_5_ICH_INT 1 +VCCSUS1_5_ICH_INT AH28 VSS[067] VSS[173] U16
close to AE15 close to AF11 AH15 1 R274 0_0603_5% AH5 U17
VCC1_5_A[07] C310 C309 IHDMI@ VSS[068] VSS[174]
AJ15 VCC1_5_A[08] 212mA AH8 VSS[069] VSS[175] AD23
A18 0.1U_0402_16V4Z AJ12 U26
VCCSUS3_3[01] 0.1U_0402_16V4Z 2 VSS[070] VSS[176]
AC11 VCC1_5_A[09]
VCCPSUS VCCSUS3_3[02] D16 AJ14 VSS[071] VSS[177] U27
2
Symbol S0 S3 S4/S5 AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ17 VSS[072] VSS[178] U3
AE11 VCC1_5_A[11] VCCSUS3_3[04] E22 AJ8 VSS[073] VSS[179] V1
AF11 VCC1_5_A[12] B11 VSS[074] VSS[180] V13
ATX
VCCLAN1_05 VCC_1_05 VCCLAN3_3 VCCLAN3_3 AG10 VCC1_5_A[13] B14 VSS[075] VSS[181] V15
AG11 VCC1_5_A[14] B17 VSS[076] VSS[182] V23
AH10 VCC1_5_A[15] B2 VSS[077] VSS[183] V28
VCCCL1_5 VCC_1_5_A VCCCL3_3 VCCCL3_3 close to AC9 AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3V_SB B20 VSS[078] VSS[184] V29
B B23 VSS[079] VSS[185] V4 B
+1.5VS AC9 VCC1_5_A[17] 1 1 1 B5 VSS[080] VSS[186] V5
VCCCL1_05 VCC_1_05 VCCCL3_3 VCCCL3_3 B8 VSS[081] VSS[187] W26
1 1 AC18 C311 C312 C313 C26 W27
C314 C315 VCC1_5_A[18] 0.022U_0402_16V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z VSS[082] VSS[188]
AC19 VCC1_5_A[19] C27 VSS[083] VSS[189] W3
2 2
VCCSUS1_5 VCC_1_5_A VCCSUS3_3 VCCSUS3_3 VCCSUS3_3[06] T1 close to T1 close to AF1 2 E11 VSS[084] VSS[190] Y1
0.1U_0402_16V4Z AC21 T2 E14 Y28
2 2 VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
VCCSUS3_3[08] T3 E18 VSS[086] VSS[192] Y29
VCCSUS1_05 VCC_1_05 VCCSUS3_3 VCCSUS3_3 0.1U_0402_16V4Z G10 T4 E2 Y4
VCC1_5_A[21] VCCSUS3_3[09] VSS[087] VSS[193]
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 E21 VSS[088] VSS[194] Y5
Internal voltage regulators power these wells inside the ICH9 VCCSUS3_3[11] T6 E24 VSS[089] VSS[195] AG28
close to AC14 AC12 U6 E5 AH6
VCCPUSB
and current for this rail is accounted for in the sourcing voltage VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]
AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 E8 VSS[091] VSS[197] AF2
rail current requirements. AC14 V6 F16 B25
VCC1_5_A[25] VCCSUS3_3[14] VSS[092] VSS[198]
close to AC7 close to AJ5 VCCSUS3_3[15] V7 F28 VSS[093]
+1.5VS AJ5 VCCUSBPLL 11mA VCCSUS3_3[16] W6 F29 VSS[094]
1 1 VCCSUS3_3[17] W7 G12 VSS[095]
USB CORE
1 +5VS
GND SATA_ITX_C_DRX_P4_ODD JODDB
A+ 2
3 SATA_ITX_C_DRX_N4_ODD 1
A- 1
GND 4 2 2
5 SATA_IRX_DTX_N4_ODD 3
B- SATA_IRX_DTX_P4_ODD 3
B+ 6 4 4
7 5 +USB_VCCA
JHDD GND 5
6 6
7 SATA_IRX_DTX_P4 W=60mils JUSBB
7 SATA_IRX_DTX_N4
GND 1 DP 8 8 8 1 1
2 SATA_ITX_C_DRX_P1 C713 1 2 0.01U_0402_25V7K 9 +5VS 9 2
A+ SATA_ITX_DRX_P1 22 +5V 9 2
3 SATA_ITX_C_DRX_N1 C715 1 2 0.01U_0402_25V7K 10 10 SATA_ITX_C_DRX_N4 3
A- SATA_ITX_DRX_N1 22 +5V 10 3
4 11 11 SATA_ITX_C_DRX_P4 4
GND SATA_IRX_DTX_N1 C717 1 MD 11 4
B- 5 2 0.01U_0402_25V7K SATA_IRX_C_DTX_N1 22 15 GND GND 12 12 12 5 5
6 SATA_IRX_DTX_P1 C719 1 2 0.01U_0402_25V7K 14 13 13 6
B+ SATA_IRX_C_DTX_P1 22 GND GND GND 6
GND 7 GND 14 21 USB20_N0 7 7
21 USB20_P0 8 8
SANTA_206401-1_RV E&T_6905-E12N-00R 9
@ @ 9
V33 8 +3VS 21 USB20_N1 10 10
V33 9 21 USB20_P1 11 11
V33 10 12 12
C 11 13 C
GND GND
GND 12 14 GND
GND 13
14 SATA_ITX_C_DRX_P4_ODD C733 1 2 16@ 0.01U_0402_25V7K E&T_6905-E12N-00R
V5 +5VS
15 SATA_ITX_C_DRX_N4_ODDC734 1 2 16@ 0.01U_0402_25V7K @
V5
V5 16
17 SATA_IRX_DTX_N4_ODD C735 1 2 16@ 0.01U_0402_25V7K
GND SATA_IRX_DTX_P4_ODD C736 1
Reserved 18 2 16@ 0.01U_0402_25V7K
GND 19
V12 20
24 21 SATA_IRX_DTX_P4 C732 1 2 17@ 0.01U_0402_25V7K
GND V12 SATA_IRX_C_DTX_P4 22
23 22 SATA_IRX_DTX_N4 C731 1 2 17@ 0.01U_0402_25V7K
GND V12 SATA_IRX_C_DTX_N4 22
SATA_ITX_C_DRX_N4 C730 1 2 17@ 0.01U_0402_25V7K
SATA_ITX_DRX_N4 22
SANTA_19A202-1_22P SATA_ITX_C_DRX_P4 C729 1 2 17@ 0.01U_0402_25V7K
SATA_ITX_DRX_P4 22
@
this is temp. footprint
eSATA/USB
+USB_VCCB +USB_VCCB USB20_P3 R130 1 2 0_0402_5% USB20_P3_R W=60mils +USB_VCCB
1.4A
1
IN OUT
33 USB_CHG_EN# 4 EN# FLG 5 USB_OC#3 21,33
USB20_P3_S_O C84 +
USB20_N3_S_O +3VALW G528_SO8 1 C749 C750
C743 2 2
2
1
USB20_N3_S 2 9 3
1D- S SLP_CHG# 21
USB20_P3 3 8 USB20_P3_R PJDLC05_SOT23-3 JESATA
21 USB20_P3 2D+ D+ USB
1 VBUS
USB20_N3 4 7 USB20_N3_R USB20_N3_R 2
21 USB20_N3 2D- D- D-
USB20_P3_R 3
U53 D+
5 GND OE# 6 4 GND
21 SLP_CHG_M3 1 1OE#
4 2OE# 5 GND
10 C739 1 2 0.01U_0402_25V7K SATA_ITX_C_DRX_P5 6
21 SLP_CHG_M4 3OE# 22 SATA_ITX_DRX_P5 A+ ESATA
13 TS3USB221RSER_QFN10_2x1P5~D C740 1 2 0.01U_0402_25V7K SATA_ITX_C_DRX_N5 7
4OE# 22 SATA_ITX_DRX_N5 A-
@ 8 12
USB20_P3_S USB20_P3_S_O S OE# function C742 1 0.01U_0402_25V7K SATA_IRX_DTX_N5 GND SHIELD
2 1A 1B 3 22 SATA_IRX_C_DTX_N5 2 9 B- SHIELD 13
USB20_N3_S 5 6 USB20_N3_S_O X H disconnect C744 1 2 0.01U_0402_25V7K SATA_IRX_DTX_P5 10 14
2A 2B L L D=1D 22 SATA_IRX_C_DTX_P5 B+ SHIELD
9 3A 3B 8 R114 1 2 100_0402_5% @ 11 GND SHIELD 15
12 11 H L D=2D
4A 4B FOX_3Q318111
A A
+USB_VCCB 14 7 @
VCC GND
2
SN74CBT3125PWRG4_TSSOP14
C354 @
0.1U_0402_16V4Z OE# function
@ 1 H A port= B port
L disconnect Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/22 Deciphered Date 2012/07/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 25 of 45
5 4 3 2 1
5 4 3 2 1
2
C753 C751 BT@
R718 0.1U_0402_16V7K 0.1U_0402_16V4Z 1 1 1 1
100K_0402_5% BT@
BT@ 1 C761 C762 C763 C764
Bluetooth Connector
3
S
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
1
G
JBT 2 MDC@ 2 MDC@ 2 MDC@ 2 MDC@
23 BT_PWR# 1
R719
2
47K_0402_5% 2
2 Inrush current = 0A
D 12 GND2 D
BT@ C847 D Q22 BT@ 11
1
0.01U_0402_25V7K AO3413_SOT23 GND1
BT@ JMDC 1 2 +3V_SB
1 R731 NIHDMI@ 0_0603_5%
+BT_VCC
10 1 2 +MDC 1 2 +VCCSUS1_5_ICH_INT
10 GND1 RES0 R733 IHDMI@ 0_0603_5%
21 USB20_P5 9 9 22 AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4
21 USB20_N5 8 8 5 GND2 3.3V 6 +3V_SB
27 WLAN_BT_CLK 7 7 22 AZ_SYNC_MD 7 IAC_SYNC GND3 8
23 BT_DET# 1 BT@ 2 6 AZ_SDIN1_MD_R 9 10
6 IAC_SDATA_IN GND4
23 BT_RST# 1 BT@ 2BT_RESET# R721 0_0402_5% 5 5 22 AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD 22
R722 0_0402_5% 4
27 WLAN_BT_DATA 4
2
3 3
1 2 2 R736
GND
GND
GND
GND
GND
GND
+3VS 2
R723 @ 1 10_0402_5%
4.7K_0402_5% 1 @
+BT_VCC
ACES_87213-1000G 2 1 AZ_SDIN1_MD_R ACES_88018-124G
22 AZ_SDIN1_MD
13
14
15
16
17
18
1
2
C754 (MAX=200mA)
1 @ R737 33_0402_5% MDC@ @ 1
0.1U_0402_16V4Z C768
@ C755 C756 BT@R724
BT@R724 Connector for MDC Rev1.5 10P_0402_50V8J
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5% @
BT@ 2 BT@ 2
1
For EMI request
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 26 of 45
5 4 3 2 1
+3V_WLAN Default
PCIe Mini Card-WLAN/WiMax PJ18
+3V_WLAN
2 2 1 1 +3VS
@ JUMP_43X79 0.1U_0402_16V4Z
1 1 1
+3V_WLAN PJ19
+1.5VS 2 1 CM17 CM18 CM19
2 1 +3V_SB
WLAN@ WLAN@ WLAN@
JWLAN @ JUMP_43X79 2 2 2
1 2 0.01U_0402_25V4Z 4.7U_0805_10V4Z
1 2
26 WLAN_BT_DATA 3 3 4 4
26 WLAN_BT_CLK 5 5 6 6
16 CLKREQ_WLAN# 7 7 8 8
9 9 10 10
11 12 +1.5VS
16 CLK_WLAN# 11 12
16 CLK_WLAN 13 13 14 14
15 16 0.1U_0402_16V4Z
15 16
17 17 18 18 1 1 1
19 19 20 20 XMIT_OFF# 33
21 22 PLT_RST# CM20 CM21 CM22
21 22 PLT_RST# 8,17,21,28,33,34
23 24 WLAN@ WLAN@ WLAN@
21 PCIE_IRX_C_WLANTX_N4 23 24 2 2 2
21 PCIE_IRX_C_WLANTX_P4 25 25 26 26
27 28 0.01U_0402_25V4Z 4.7U_0805_10V4Z
27 28
29 29 30 30 PM_SMBCLK 14,15,16,23
21 PCIE_ITX_C_WLANRX_N4 31 31 32 32 PM_SMBDATA 14,15,16,23
21 PCIE_ITX_C_WLANRX_P4 33 33 34 34
35 35 36 36 USB20_N7 21
WLAN/ WiFi 37 37 38 38 USB20_P7 21 WiMax
+3V_WLAN 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
R110 1 2 0_0402_5% E51_TXD_R 49 50
33 E51_TXD 49 50
R106 1 2 0_0402_5% E51_RXD_R 51 52
33 E51_RXD 51 52
53 GND1 GND2 54
Debug card using
2
R959 FOX_AS0B226-S40N-7F
100K_0402_5% @
1
RN4 1 23 29
10K_0402_5% CN7 CP_USB# GND GND
9 CPUSB# Thermal_Pad 21 21 PCIE_ITX_C_NEWRX_N1 24 PETn0 GND 30
1
@ 0.1U_0402_16V4Z 21 PCIE_ITX_C_NEWRX_P1 25
RN5 @ RCLKEN PETp0
18 RCLKEN 26 GND
5
10K_0402_5% UN2 2
2
@ CLKREQ# 2 G577NSR91U_TQFN20_4x4 27
G Vcc
Y GND
1 A SANTA_132862-2_26P
1
D NC7SZ32P5X_NL_SC70-5 @
3
+LAN_VDD12
Close to Pin10,13,30,36,45
2 2 2 2 2
CL15 CL2 CL3 CL4 CL5
1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1
Place Close to Chip UL2
ISOLATEB 28
RL5 ISOLATEB
VDDTX 19 +EVDD12 1 2
1K_0402_1% LAN_X1 41 30 +LAN_VDD12
LAN_X2 CKXTAL1 DVDD12 CL6 CL7
42 CKXTAL2 DVDD12 36 Close to Pin19
13
2
RTL8103EL-GR_LQFP48_7X7
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 28 of 45
A B C D E
5 4 3 2 1
+3VS_DVDD RA1
Codec 10U_0805_10V4Z 30mil 2 1
1 1 0_0603_5%
+3VS
Audio regulator +5VS
CA1 CA2
1
+AVDD RA2
2 2 PJ33
40mil 0_0603_5%
1
RA3 0.1U_0402_16V4Z 0.1U_0402_16V4Z NIHDMI@ JUMP_43X39
2 1 10U_0805_10V4Z +1.5VS_DVDIO @
+VDDA
2
+1.5VS
2
0_0603_5% LA1
CA3
1
CA4
1
CA5
1
CA6
1 1
CA57 10U_0805_10V4Z 20mil1 2 +VDDA
2
FBMA-L11-160808-800LMT_0603 +5VALW
1 1 1
IHDMI@ 4.75V
2 2 2 2 2 CA7 CA8 CA56
D D
10U_0805_10V4Z 0.1U_0402_16V4Z 100P_0402_50V8J 100P_0402_50V8J 2 UA1
For EMI request 2 2 2 CA9 2
0.1U_0402_16V4Z For EMI request 1U_0402_6.3V4Z
25
38
1 VIN VOUT 5
9
UA2 @ CA10
1 1U_0402_6.3V4Z
2
AVDD1
AVDD2
DVDD_IO
DVDD
GND CA11 1 @
17,27,33,36,39,41 SUSP# 3 SHDN# BP 4 2 1
14 35 0.22U_0402_10V4Z
LINE2-L LOUT1_L AMP_SPK_L 30
For EMI request APL5151-475BC-TRL_SOT23-5 @
15 36 @
LINE2-R LOUT1_R AMP_SPK_R 30
1 2 MIC@
CA52 100P_0402_50V8J 16 39
30 MIC2_L MIC2_L LOUT2_L
Int. Mic 17 41
30 MIC2_R MIC2_R LOUT2_R
CA51 100P_0402_50V8J
1 2 23 LINE1_L SPDIFO1 48
MIC@
24 LINE1_R SPDIFO2 45
1 2
CA54 100P_0402_50V8J 21 33 1 RA5 2
30 MIC1_C_L MIC1_L HPOUT_L HP_L 30
63.4_0402_1%
Ext. Mic 22 32 1 RA6 2
30 MIC1_C_R MIC1_R HPOUT_R HP_R 30
CA53 100P_0402_50V8J 63.4_0402_1%
1 2
12 BEEP_IN MONO_OUT 37
1 2 MONO_IN
CA14 100P_0402_50V8J Beep sound
C 6 46 C
22 AZ_BITCLK_HD BITCLK DMIC_CLK1/2
5 44
22 AZ_SDOUT_HD SDATA_OUT DMIC_CLK3/4 EC Beep RA8
22 AZ_SDIN0_HD 2 1 AZ_SDIN0_HD_R 8 SDATA_IN LINE2_VREFO 20 33 EC_BEEP# 1 2
33_0402_5% RA7 +MIC1_VREFO
47K_0402_5%
11 18 +MIC2_VREFO
22 AZ_RST_HD# RESET# LINE1_VREFO CA46
10 28 10mil 1 2
22 AZ_SYNC_HD SYNC MIC1_VREFO
10mil CA45 MIC@ PCI Beep RA9
CA15
19 1U_0402_6.3V4Z 1 2 1 2 1 2 MONO_IN
MIC2_VREFO 23 SB_SPKR
23 SPK_SEL 2 GPIO0/DMIC_DATA1/2 47K_0402_5%
31 CA16 1 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z
CPVEE 2.2U_0603_6.3V6K
3 GPIO1/DMIC_DATA3/4
VREF 27 AC_VREF CA18 CA19 CA58 CardBUS Beep
100P_0402_50V8J
10U_0805_10V4Z
SENSE_A
0.1U_0402_16V4Z
13 SENSE A RA19
40 AC_JDREF 1 1 1 1 2
SENSE_B JDREF RA10 CA55 31 PCM_SPK#
34 SENSE B 47K_0402_5%
1
100P_0402_50V8J
CBN 30 1 2 1 1
20K_0402_1%
2 1 EAPD# 47 CA17 2.2U_0603_6.3V6K
30 MUTE# EAPD 2 2 2
RA4 0_0402_5% 29 RA11 CA20
CBP 10K_0402_5%
43 NC 0.1U_0402_16V4Z
IF test OK, link direct 2 2
2
4 DVSS AVSS1 26 For EMI request
CA34 @ 100P_0402_50V8J 7 42
AZ_BITCLK_HD DVSS AVSS2
1 2 2 1 For EMI request
RA31 @ 100_0402_5% CA47 1 2 0.1U_0603_50V7K
ALC272-GR_LQFP48_7X7
CA42 @ 100P_0402_50V8J need to re-link ALC272 CA48 1 2 0.1U_0603_50V7K
B
1 2 AZ_RST_HD# 2 1 +3VS
DGND AGND B
RA37 4.7K_0402_5% CA49 1 2 0.1U_0603_50V7K
@
For EMI request GPIO0-->SPK_SEL HIGH:HARMAN CA50 1 2 0.1U_0603_50V7K
LOW:NO-BRAND
RA12 1 2
0_0603_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 29 of 45
5 4 3 2 1
Ext. Mic
CH751H-40PT_SOD323-2
TPA6017 Medium Range Amplifier CA21
RA21 2 RA20
1K_0402_5% 4.7K_0402_5%
1 1
DA1
2 +MIC1_VREFO
4.7U_0805_10V4Z 2 1 2 1 MIC1_L
29 MIC1_C_L
+5VS 4.7U_0805_10V4Z 2 1 2 1 MIC1_R
29 MIC1_C_R
0.1U_0402_16V4Z 1K_0402_5%
CA22 RA22 2 RA23 1 1 2 +MIC1_VREFO
4.7K_0402_5% DA2
1 1 1 CH751H-40PT_SOD323-2
CA23
10U_0805_10V4Z
CA24 CA25 Int. Mic
2 2 2
2 MIC@ 1 +MIC2_VREFO
4.7K_0402_5% RA24
0.1U_0402_16V4Z 10 dB MIC@ RA25 MIC@
CA26 1K_0402_5% JMIC
1U_0402_6.3V4Z 2 1 2 1 INT_MIC 1 MIC@ 2INT_MIC_R 1 3
+5VS 29 MIC2_L 1 NC1
1 2 RA38 0_0402_5% 2 4
2 NC2
1
1U_0402_6.3V4Z CA27
16
15
29 MIC2_R 2 1 2 1
6
UA3 RA28 RA27 1K_0402_5% 220P_0402_50V7K reserve for test ACES_85204-0200N
100K_0402_5% 100K_0402_5% CA28 RA26 MIC@ @
Rin =70Kohm close to JLVDS
VDD
PVDD1
PVDD2
MIC@
3
@ MIC@
2
7 2 DA3 @
CA29 0.033U_0402_25V7K RIN+ GAIN0 PSOT24C_SOT23
3
1
GAIN1
1
29 AMP_SPK_R LINE_C_OUTR 17
CA30 0.033U_0402_25V7K RIN- SPKR+ RA30 RA29
ROUT+ 18
100K_0402_5% 100K_0402_5%
@
14 SPKR- Speaker Connector
2
ROUT-
9 LIN+
CA31 0.033U_0402_25V7K DA4 PJDLC05_SOT23-3
4 SPKL+ 2
LOUT+
1
29 AMP_SPK_L LINE_C_OUTL 5 3
CA32 0.033U_0402_25V7K LIN- SPKL- JSPK
LOUT- 8 GAIN0 GAIN1 Av(db)Rin(ohm)
SPKL+ LA3 1 2 FBMA-L11-160808-800LMT_0603 SPK_L1 1
SPKL- LA4 1 FBMA-L11-160808-800LMT_0603 SPK_L2 1
0 0 6 90K 2 2 2
setting 68Hz SPKR+ LA5 1 2 FBMA-L11-160808-800LMT_0603 SPK_R1 3
SPKR- LA6 1 FBMA-L11-160808-800LMT_0603 SPK_R2 3
0 1 10 70K 2 4 4
F=1/2ʌRC --> -3db NC 12 Keep 10 mil width
1 0 15.6 45K DA5 PJDLC05_SOT23-3 C860 C861 C862 C863 ACES_85204-0400N
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
680P_0402_50V7K
C=0.033U,R=70K,F=68Hz 10 AMP_BYPASS 3 1 1 1 1 @
BYPASS
29 MUTE# 19 SHUTDOWN 1 1 21.6 25K 1
2 2
@ @ @ @
2 2 2 2
GND5
GND1
GND2
GND3
GND4
CA33
0.47U_0603_10V7K For EMI request
1
TPA6017A2_TSSOP20
21
20
13
11
1
29 NBA_PLUG 4
LA7 1 2 HP_R_L 3
29 HP_R
KC FBM-L11-160808-121LMT 0603 6
LA8 1 2 HP_L_L 2
29 HP_L
KC FBM-L11-160808-121LMT 0603 1
1 FOX_JA6333L-B3T0-7F
+3VS 3 CA43 @
2
RA32 DA6 @
100K_0402_5% PJDLC05_SOT23-3
1
CA35 0.1U_0402_16V4Z
RA33 RA34 +3VS 1 2 For EMI request
2
5
1
2
CA36
Ext.MIC/LINE IN JACK
P
NC
2 1 2 2 4 0.1U_0402_16V4Z JEXMIC
A RA35 10K_0402_5% A Y 2
5
G
74LVC1G14GW_SOT353-5 UA5
1 UA4 1 14 4
29 MIC_SENSE
3
7 08 CA39
CA37 CA38 GND Q2# FOX_JA6333L-B3T0-7F
SW_XRE094_3P 0.01U_0402_16V7K 0.01U_0402_16V7K 74LCX74MTC_TSSOP14 3 1 CA44 1 1 @
4
2 2 2 0.1U_0402_16V4Z
1
2 @ CA40 CA41
120P_0402_50V8K @
0.1U_0402_16V4Z DA7 @ 2 @ 2 2
ENCODER_DIR 33
PJDLC05_SOT23-3
ENCODER_PULSE 33
120P_0402_50V8K
For EMI request
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 30 of 45
A B C D
21 PCI_AD[0..31] PCI_AD[0..31]
+5VS
1 1 0.1U_0402_16V4Z
IDSEL SELECT POWER-ON-STRAPPING CB1 CB2
1 (SEE NOTE & TABLE FOR OPTIONS) PCM@ PCM@ 1
2 2 1 1
10U_0805_10V4Z 0.1U_0402_16V4Z +3VS CB3 CB4
+3VS PCM@ PCM@
1 1 1 1 4.7U_0805_10V4Z
CB5 CB6 CB7 CB8 2 2
PCM@ PCM@ PCM@ PCM@
1
+S1_VCC
2 2 2 2 RB16 RB17 40mil UB2 4.7U_0805_10V4Z
33K_0402_5% 33K_0402_5% 5 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z UB1 @ PCM@ VCC/VPP +3.3V
6 VCC/VPP +3.3V 2
VCC5# 7 3
PCMCIA Socket
2
VCC5# VCC3# VCC5# +5V
64 CORE_VCC VCC5#/VCCD0#/SDATA 124 8 VCC3# GND 4
77 125 VCC3#
CORE_VCC VCC3#/VCCD1#/SCLK OZ2210GN-B1_SO8
97 CORE_VCC VPP_PGM/VPPD0/SLATCH 123
10U_0805_10V4Z 0.1U_0402_16V4Z 115 PCM@
CORE_VCC
1
+3VS PVT JPCM
1 1 1 1 103 S1_D10 RB22 1
CB9 CB10 CB13 PCI_VCC D10/CAD31 S1_D9 33K_0402_5% GND
PCM@ PCM@ PCM@
20 PCI_VCC D9/CAD30 102
S1_D1 PCM@
SA000026P10 (S IC OZ2210GN-B1 SO 8P) S1_D3
35 GND
33 PCI_VCC D1/CAD29 101 2 DATA3
100 S1_D8 VCC5# VPP_PGM IDSEL SELECT S1_CD1# 36
2
2 2 2 PCI_AD31 D8/CAD28 S1_D0 S1_D4 CD1#
4 AD31 D0/CAD27 99 3 DATA4
PCI_AD30 5 110 S1_A0 (124) (123) S1_D11 37
0.1U_0402_16V4Z PCI_AD29 AD30 A0/CAD26 S1_A1 S1_D5 DATA11
6 AD29 A1/CAD25 109 4 DATA5
PCI_AD28 7 108 S1_A2 S1_D12 38
PCI_AD27 AD28 A2/CAD24 S1_A3 S1_D6 DATA12
8 AD27 A3/CAD23 106 5 DATA6
PCI_AD26 9 105 S1_A4 VCC5# VPP_PGM IDSEL SELECT S1_D13 39
PCI_AD25 AD26 A4/CAD22 S1_A5 S1_D7 DATA13
10 AD25 A5/CAD21 104 (124) (125) 6 DATA7
PCI_AD24 13 118 S1_A6 S1_D14 40
PCI_AD23 AD24 A6/CAD20 S1_A25 S1_CE1# DATA14
2 14 AD23 A25/CAD19 95 7 CE1#
2
1
CB14
10P_0402_50V8J
@ Security Classification Compal Secret Data Compal Electronics, Inc.
2
Issued Date 2009/07/22 Deciphered Date 2012/07/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 31 of 45
A B C D
5 4 3 2 1
+3VS_CR
+3VALW 1 2
RC4 0_0603_5% @ 1
CC1
0.1U_0402_16V4Z
confirm that whether can be removed 3IN1@
D 2 RC7 0_0402_5% 3IN1@ D
2 1
UC2
+3VS_CR
CC4 0.1U_0402_16V4Z 1 AV_PLL
2 1 3 NC
2
3IN1@ 7
RC8 NC
+VCC_3IN1 9 CARD_3V3
100K_0402_5% 11
3IN1@ D3V3
+3VS_CR 33 D3V3 VREG 10
22 1
1
MS_D4 CC7
NC 30
RC10 0_0402_5% 1 +3VS_CR 8 1U_0402_6.3V4Z
RST# RST#_R CC5 RST#_R 3V3_IN 3IN1@
2 1 44 RST#
3IN1@ 1U_0402_6.3V4Z MODE SEL 2
45 MODE_SEL
1 3IN1@ XTLO 47 43
CC8 2 XTLI XTLO XD_CLE_SP19
48 XTLI XD_CE#_SP18 42
1U_0402_6.3V4Z 41
3IN1@ XD_ALE_SP17 SD_DATA2
21 USB20_N10 4 DM SD_DAT2/XD_RE#_SP16 40
2 SD_DATA3
21 USB20_P10 5 DP SD_DAT3/XD_WE#_SP15 39
CR_LED# 14 38
GPIO0 XD_RDY_SP14 RC11 1 3IN1@ 2 22_0402_5% SDCLK
SD_DAT4/XD_WP#/MS_D7_SP13 37
SD_DAT5/XD_D0/MS_D6_SP12 35
34 SD_MS_CLK RC12 1 3IN1@ 2 22_0402_5% MSCLK
+3VS SD_CLK/XD_D1/MS_CLK_SP11 MS_DATA3_SD_DATA6
SD_DAT6/XD_D7/MS_D3_SP10 31
MODE SEL 29 MSCD#
C MS_INS#_SP9 MS_DATA2_SD_DATA7 C
SD_DAT7/XD_D2/MS_D2_SP8 28
1
27 SD_MS_DATA0
RC13 SD_DAT0/XD_D6/MS_D0_SP7 MS_DATA1
SD_DAT1/XD_D3/MS_D1_SP6 26
120_0402_5% 25 MSBS
XD_D5_SP5
1
1 3IN1@ 23 SD_DATA1
CC13 RC16 XD_D4/SD_DAT1_SP4 SDCD#
21
22
3IN1@ EEDI
2 13 XTAL_CTR
RREF XTAL_CTR
24
1
MS_D5
12 DGND
32 15
CR_LED#
6
DGND EEDO
EECS 16
17
3 in 1 Card Reader
AGND EESK SDCMD
46 AGND SD_CMD 36
2
2
RTS5159-GR_LQFP48_7X7 3IN1@
RC14 RC15
6.19K_0402_1% 0_0402_5% confirm all pin define with connector spec.
3IN1@ 3IN1@
1
JREAD
SDWP# 1
SD_DATA1 SD-WP
2 SD-DAT1
SD_MS_DATA0 3 SD-DAT0
4 SD-GND
5 MS-GND
B MSBS B
6 MS-BS
SDCLK 7
MS_DATA1 SD-CLK
8 MS-DAT1
SD_MS_DATA0 9 MS-DAT0
+VCC_3IN1 10 SD-VCC
MS_DATA2_SD_DATA7
48Mhz 1 1
11
12
MS-DAT2
CC10 CC11 MSCD# SD-GND
13 MS-INS
1U_0402_6.3V4Z 0.1U_0402_16V4Z MS_DATA3_SD_DATA6 14
XTLI 3IN1@ 3IN1@ SDCMD MS-DAT3
16 CLK_48M_CR 1 2 15 SD-CMD
RC19 0_0402_5% 2 2 MSCLK 16 MS-SCLK
3IN1@ 17 MS-VCC
SD_DATA3 18 SD-DAT3
+3VS_CR 1 2 XTAL_CTR 19 MS-GND
RC20 0_0402_5% SD_DATA2 20 22
SDCD# SD-DAT2 GND1
3IN1@ R C USB AUTO DE-LINK MS FORMATTER Description 21 SD-CD GND2 23
TAITW_R009-125-LR_RV
0 NC YES Recommended @
MSCLK 1 2
YC1
12MHZ_16P_6X12000012 10K 180P LED ON @ RC17 @ CC14
@
2
A 10_0402_5% 10P_0402_50V8J A
XTLO 10K 680P YES SDCLK 1 2
CC12 6P_0402_50V8D
@ @ RC18 @ CC15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 32 of 45
5 4 3 2 1
5 4 3 2 1
+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 C771 1 1 2 2 C769
C770 1 2
C772 C773 C774 C775
1000P_0402_50V7K1000P_0402_50V7K 0.1U_0402_16V4Z
2 2 2 2 1 1
111
125
0.1U_0402_16V4Z 0.1U_0402_16V4Z
22
33
96
67
9
for EMI request U43
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
CLK_PCI_EC
1
D D
R738 1 21
22 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 18
@ 10_0402_5% 2 23
22 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# 29
23,31,34 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26
22,34 LPC_FRAME# 4 27 ACOFF 39
2
LFRAME# ACOFF/FANPWM2/GPIO13
1 22,34 LPC_AD3 5 LAD3
22,34 LPC_AD2 7 LAD2 PWM Output
C778 8 63 BATT_TEMPA
22,34 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA 38
@ 22P_0402_50V8J BATT_TEMPA
2 22,34 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 1
C776
2
100P_0402_50V8J
ADP_I/AD2/GPIO3A 65 ADP_I 39
CLK_PCI_EC 12 AD Input 66 ACIN_D 1 2
16 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 39
13 75 C779 100P_0402_50V8J
8,17,21,27,28,34 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
ECRST# 37 76
+3VL R739 ECRST# SELIO2#/AD5/GPIO43
23 EC_SCI# 20 SCI#/GPIO0E
47K_0402_5% 38
35 WL_BT_LED# CLKRUN#/GPIO1D
2 1 ECRST# 68
DAC_BRIG/DA0/GPIO3C DAC_BRIG 18
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 4
2 1 DA Output IREF/DA2/GPIO3E 71 IREF 39
C780 0.1U_0402_16V4Z KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 39
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI3/GPIO33 PSCLK1/GPIO4A USB_CHG_EN# 25
KSI4 59 84 +5VS
+3VL KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 25
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C ENCODER_DIR 30
KSI6 61 PS2 Interface 86 TP_CLK 1 2
KSI6/GPIO36 PSDAT2/GPIO4D ENCODER_PULSE 30
1 2 KSO1 KSI7 62 87 TP_CLK 4.7K_0402_5% R740
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 26
R595 47K_0402_5% KSO0 39 88 TP_DATA TP_DATA 1 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 26
1 2 KSO2 KSO1 40 4.7K_0402_5% R741
R596 47K_0402_5% KSO2 KSO1/GPIO21
41 KSO2/GPIO22
C KSO3 42 97 VGATE +3VALW C
KSO3/GPIO23 SDICS#/GPXOA00 VGATE 8,23,43
to avoid EC entry ENE test mode KSO4 43 98
KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# 36
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 SBPWR_EN# 24,36
LID_SW#
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 34 2 1
KSO7 46 SPI Device Interface 47K_0402_5% R766
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119
KSI[0..7] KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 34
KSO10 49 120
26 KSI[0..7] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 34
KSO11 50 SPI Flash ROM 126
KSO[0..17] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 34
KSO12 51 128
26 KSO[0..17] KSO12/GPIO2C SPICS# SPI_CS# 34
KSO13 52
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
RP23 KSO15 54 73
KSO16 KSO15/GPIO2F CIR_RX/GPIO40
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
+3VL 1 8 EC_SMB_CK1 KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 39
2 7 EC_SMB_DA1 90
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# 35 +3VALW
+3VS 3 6 EC_SMB_CK2 91
CAPS_LED#/GPIO53 CAPS_LED# 26
4 5 EC_SMB_DA2 EC_SMB_CK1 77 GPIO 92
38 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# 35
EC_SMB_DA1 78 93 1 2
38 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# 35
2.2K_8P4R_5% EC_SMB_CK2 79 SM Bus 95 100K_0402_5% R742
4,17 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 27,42
EC_SMB_DA2 80 121 D64
4,17 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 43
127 ACIN_D ACIN_D 2 1
AC_IN/GPIO59 ACIN 23,35,37
+3VL 2 1 CEC_INT#
R751 100K_0402_5% CH751H-40PT_SOD323-2
23 PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# 23
SLP_S5# 14 101
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 23
23 EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON 35
CEC_INT# 16 103
+3VALW LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI#
17 104 PM_PWROK
B SUSP#/GPIO0B ICH_PWROK/GPXO06 PM_PWROK B
C781 18 GPO 105
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 18
1 2 8 MCH_TSATN_EC# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 XMIT_OFF# 27 1 2 UMA_ENBKL 10
0.1U_0402_16V4Z PM_SLP_S4#_R 25 107 R745GM@ 0_0402_5%
EC_THERM#/GPIO11 GPXO10
5
@ 28 108 ENBKL 1 2
4 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 VGA_ENBKL 17
2 29 R746PM@ 0_0402_5%
P
23 PM_SLP_S5# B FANFB2/GPIO15
4 SLP_S5# 30 1 2
Y 27 E51_TXD EC_TX/GPIO16
1 31 110 R747 100K_0402_5%
23 PM_SLP_S4# A 27 E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1
G
32 112 ENBKL
26,35 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2
NC7SZ08P5X_NL_SC70-5 U44 34 114
35 PWR_SUSP_LED# USB_OC#3 21,25
3
@ PWR_LED#/GPIO19 GPXID3
26 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# 23
116 ICH_PWROK 1 2
GPXID5 SUSP# 17,27,29,36,39,41
maybe can remove 117 R231 10K_0402_5%
GPXID6 PBTN_OUT# 23
118 USB_OC#0_R PM_PWROK 1 2
CRY1 GPXID7 R264 10K_0402_5%
122 XCLK1
CRY2 123 124 +EC_V18R +3VS
PM_SLP_S5# SLP_S5# XCLK0 V18R
1 2
AGND
R748 0_0402_5% 1 2
GND
GND
GND
GND
GND
5
PM_SLP_S4# 1 2 PM_SLP_S4#_R 4.7U_0805_10V4Z
R750 0_0402_5% KB926QFD3_LQFP128_14X14 VGATE 2
P
11
24
35
94
113
69
R749 B
Y 4 ICH_PWROK 8,23
CRY1 1 2CRY2 PM_PWROK 1 A
G
@ 20M_0603_5% U5
3
NC7SZ08P5X_NL_SC70-5
1 2 EC_SWI#
23,27 SB_WAKE#
R753@ 0_0402_5% 1 1 1 2
1 2 C784 C785 R752@ 0_0402_5%
A LAN_WAKE# 28 A
1
R754 0_0402_5%
15P_0402_50V8J
15P_0402_50V8J
R756@ 0_0402_5% 2 2
1 2 USB_OC#0 21,25
R757 0_0402_5%
NC
NC
The circuit is reserve for new design for pre-MP Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/22 Deciphered Date 2012/07/22 Title
2
SCHEMATIC MB A4982
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
32.768KHZ_12.5P_1TJS125BJ4A421P AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 33 of 45
5 4 3 2 1
Lid SW LPC Debug Port
SPI Flash (16Mb*1) Please place the PAD under DDR DIMM.
+3VALW It's for 16" using
U48 16@
APX9132ATI-TRL_SOT23-3 H1
+3VS
+3VL 2 3
GND
VDD VOUT LID_SW# 33
6 5
1 20mils 1 1
1
C786 U46 1 2 7 4
23,31,33 SERIRQ PLT_RST# 8,17,21,27,28,33
8 4 C822 C823 R761 0_0402_5%
0.1U_0402_16V4Z VCC VSS 0.1U_0402_16V4Z 10P_0402_50V8J
2 2 16@ 16@ 2
3 W 22,33 LPC_AD3 8 3 LPC_AD2 22,33
7 HOLD
22,33 LPC_AD1 9 2 LPC_AD0 22,33
33 SPI_CS# 1 S
33 SPI_CLK 6 C
+3VALW It's for 17" using 22,33 LPC_FRAME# 10 1 CLK_PCI_DDR 16
5 2 U50 17@
33 EC_SO_SPI_SI D Q EC_SI_SPI_SO 33
2
APX9132ATI-TRL_SOT23-3
SST25LF080A_SO8-200mil @ DEBUG_PAD R764
2 3 LID_SW# 22_0402_5%
GND
VDD VOUT
1
1 1 2
1
SPI_CLK 2 R953 1 1 2
33_0402_5% C852 33P_0402_50V8J C836 C838 C820
0.1U_0402_16V4Z 10P_0402_50V8J 22P_0402_50V8J
reserve for EMI, close to U46 2 17@ 17@ 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 34 of 45
5 4 3 2 1
+3VL
NB_PM_R1
PCB NB_PM_R3
2
CANTIGA PM
R765 PCB ZKU LA-4982P REV1 CANTIGA PM PMR1@
D PMR3@ D
100K_0402_5%
SW5 PJP1 U3 U3
1
1 3 ON/OFFBTN#
ON/OFFBTN# 26,33 51_ON# 37
TOP side DC-IN
2 4 1 NB_GL40_R3 NB_GL40_R1
C646 16
6
@ SMT1-05-A_4P 0.1U_0402_16V4Z
6
5
2
U3 U9
1
BTM side 2 4 For EMI request R767
@ SMT1-05-A_4P
10K_0402_5% DC-IN
NB_GM45_R1 SB_R1
6
5
17
1
PJP1
debug phase using KTWAA45@ CANTIGA GM45 ICH9-M ES
GM45R1@ ICH9R1@
Screw Hole
C H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 C
ACIN 23,33,37
Vf=2.0V(typ),2.4V(max)
DC-IN LED If=30mA(max) POWER/SUSPEND LED
2
H_3P0N H_3P0N H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
1
D67 Q30A @ @ @ @ @ @ @ @ @ @
+3VALW 1 2 2 1 6 1
R768 120_0402_5%
HT-110UYG-CT_YEL/GRN 2N7002DW-T/R7_SOT363-6 H21 H22 H23 H24 H26 H27 H28 H29 H40
another at page36 D68
1
@ @ @ @ @ @ @ @ @
BATT CHARGE/FULL LED +3VALW 1
R770
2
120_0402_5%
1
1
+3VALW 1 2 1 @ @
R773 120_0402_5%
3 BATT_FULL_LED# 33
H32 H33 H34 H35
CPU
HT-210UD/UYG_AMB/GRN
H_3P7 H_3P7 H_3P7 H_3P7
1
@ @ @ @
B WL&BT LED D74
B
1
@ @
H_3P7 H_3P7
1
@ @
@ @ @ @
A
HDD LED A
1
+3VS 2 R779 1 6 1
10K_0402_5%
5
Q31A
D76 2N7002DW-T/R7_SOT363-6
1 2 2 1 3 4
+3VS
R780 120_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
HT-110UYG-CT_YEL/GRN Q31B 2N7002DW-T/R7_SOT363-6 2009/07/22 2012/07/22 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 35 of 45
5 4 3 2 1
A B C D E
470_0805_5%
470_0805_5%
8 1 8 1 Q34 C828 C829
D S D S
470_0805_5%
7 D S 2 7 D S 2 8 D S 1
2
2 2 R781 2 2 R782
6 D S 3 6 D S 3 7 D S 2
2 2 R783
1 5 D G 4 5 D G 4 6 D S 3 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 5 4
SI4800BDY_SO8 D G
1 R784 2 +VSB SI4800BDY_SO8 1 R785 2 +VSB 1U_0402_6.3V4Z
3 1
3 1
0.022U_0402_25V7K
0.01U_0402_25V7K
47K_0402_5% 47K_0402_5% SI4856ADY_SO8 1 R786
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1 1 1 1 2 +VSB
3 1
1
6
C831 220K_0402_5%
4.7U_0805_10V4Z
1 FDS6676AS 1
6
0.1U_0402_25V6
C830 R787 Q35A C832 C833 R788 Q36A
C835
330K_0402_5% Q35B 200K_0402_5% Q36B C834 R789 Q37A
2 2 SUSP 2 2 @ SUSP 5 820K_0402_5% Q37B
2 5 2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 2 SUSP 5
2
2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2
2N7002DW-T/R7_SOT363-6
4
+3VALW TO +3V_LAN
+3VALW TO +3V_SB
+3VALW
+3VALW
+3VALW +3V_SB
2
Vgs=-4.5V,Id=3A,Rds<97mohm PJ36
R793 2 1
100K_0402_5% 2 1
2
STAR@ C839 Q41 Q44 @ JUMP_43X79
2
2 0.1U_0402_16V7K AO3413_SOT23 Vgs=10V,Id=6A,Rds=35mohm Inrush current = 0A 2
1
D
S
STAR@ STAR@ PJ35 6
S
1 G
1U_0402_6.3V4Z
33 WOL_EN# 1 2 2 JUMP_43X79 1 5 4
R795 47K_0402_5% 2 @ C842 2 1 1
2
+3V_LAN
1
STAR@ C837 D 10U_0805_10V4Z 1 C843
1
G
1
STAR@ 2 STAR@ STAR@ STAR@ 470_0805_5%
Inrush current = 0A
3
1 SI3456BDV-T1-E3_TSOP6 2 2 STAR@
+VSB 2 1
6 1
1 1 R804 20K_0402_5%
1
STAR@ 1
C840 C841 1U_0402_6.3V4Z R805 C845 Q46A
4.7U_0805_10V4Z STAR@ Q46B 200K_0402_5% 0.1U_0402_25V6 STAR@
@ 2 2 SBPWR_EN# STAR@ STAR@ STAR@ SBPWR_EN#
5 2 SBPWR_EN# 24,33
2
2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
1
3 3
2
R801 R802 R796
470_0805_5% 470_0805_5% 100K_0402_5%
1
1
SUSP
42 SUSP
3
3
Q30B
2N7002DW-T/R7_SOT363-6 Q28B
1
D 2N7002DW-T/R7_SOT363-6
Q21 2 SUSP 5 SUSP 5 another at page35
17,27,29,33,39,41 SUSP#
2N7002_SOT23-3 G another at page35
2
S
3
4
R799
10K_0402_5%
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 36 of 45
A B C D E
A B C D
VS
VIN PR1
PL1 VIN 1M_0402_1%
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2
1
1
PJP1 N1 PR3
1 10A_125V_451010MRL PR2 5.6K_0402_5% PR4
+ 84.5K_0402_1% 10K_0402_1%
1
1 1
2 1 2 ACIN 23,33,35
2
+ PC1 PC2 PC3 PC4 PR5
8
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 22K_0402_1% PU1A
2
-
1 2 3
P
+ PACIN
- 4 O 1 PACIN 39
2 -
G
@ SINGA_2DW-0005-B03
1
PR6 LM393DG_SO8
4
PC5 20K_0402_1% PC6 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%
2
2
2
2 1 RTCVREF
PR8
VIN 10K_0402_1%
3.3V Vin Detector
2
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976
1
BATT+ 2 1
1
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
N1 TP0610K-T1-E3_SOT23-3
PR11
2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS 1 2 2
PR12
1
1K_1206_5%
1
1
PC8 PD4
PR13 PC7 0.1U_0603_25V7K 2 1 N3 1 2
100K_0402_1% 0.22U_1206_25V7K VIN B+
2
2
RLS4148_LL34-2 PR14
2
1K_1206_5%
35 51_ON# 1 2
PR15 1 2
22K_0402_1%
RTC Battery PR16
1K_1206_5%
1
RTCVREF
1
PR19 PR20
PR17
200_0603_5%
- PBJ1 + VL
100K_0402_1%
1 2
2.2M_0402_5%
2 1
PR18
499K_0402_1%
PR21 PR22 PU2 G920AT24U_SOT89-3 2 1 +RTCBATT
3.3V +RTCBATT
2
560_0603_5% 560_0603_5%
2
1 2 1 2 3 2 N2
+CHGRTC OUT IN PD5
8
@ MAXEL_ML1220T10 RB715F_SOT323-3 PU1B
1
GND
2 5
P
40 EN0 +
PC9 PC10 1 7
10U_0805_10V4Z 1 O
39 ACON 3 6 2 1 RTCVREF
2
1
G
1U_0805_25V4Z
SP093MX0000
1
LM393DG_SO8 PR23 PR24 PC11
1
10K_0402_1% 499K_0402_1% 1000P_0402_50V7K
1
PR26
2
PC12 @ PR25
@PR25 191K_0402_1%
2
3 3
1000P_0402_50V7K 66.5K_0402_1%
2
1
PJ3
2
PJ1 PJ2 PC13
+3VALWP 2 1 +3VALW +1.5VP 2 1 +1.5V VL 2 1 +5VL 1000P_0402_50V7K
2
2 1 2 1 2 1
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39
(5A,200mils ,Via NO.= 10) PJ4 (100mA,40mils ,Via NO.= 2) PR27
1
D 47K_0402_1%
2 2 1 1
OCP(min)=7.7A PQ2
2 2 1 PACIN
@ JUMP_43X118 SSM3K7002FU_SC70-3
G
(11A,440mils ,Via NO.= 22) S
3
PJ5 OCP(min)=12.97A PJ7
1
+5VALWP 2 2 1 1 +5VALW
+3VLP 2 2 1 1 +3VL
@ JUMP_43X118
(5A,200mils ,Via NO.= 10) PJ6 @ JUMP_43X39
2 2 1 1 (100mA,40mils ,Via NO.= 2) 2 +5VALWP
OCP(min)=7.9A
@ JUMP_43X118
PQ3
PJ9 PJ11 Precharge detector DTC115EUA_SC70-3
PJ8
3
+1.8VP +1.8V
2 1
+1.05VSP 2 2 1 1 +1.05VS 2 2 1 1 15.97V/14.84V FOR
+VSBP 2 1 +VSB
@ JUMP_43X39
@ JUMP_43X118 @ JUMP_43X79 ADAPTOR
(10A,400mils ,Via NO.=20)
PJ12
(120mA,40mils ,Via NO.= 1) OCP(min)=12.16A +1.8VSP 2 1 +1.8VS
2 1
@ JUMP_43X79
4
(2A,100mils ,Via NO.=6) 4
PJ10
+0.75VSP 2 2 1 1 +0.75VS OCP(min)=2.55A
@ JUMP_43X79
(2A,80mils ,Via NO.= 4)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/22 Deciphered Date 2012/07/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 37 of 45
A B C D
A B C D
100K_0402_1%_TSM0B104F4251RZ
PJP2 15A_65V_451015MRL SMB3025500YA_2P
1 BATT_S1 1 2 1 2
1 BATT+
2 2
2
3 BATT_P3 1 2 1 2
3 +3VLP
4 BATT_P4 PR28 PR29 PR30
4
1
BATT_P5 1K_0402_1% 47K_0402_1% 47K_0402_1% D
5 5
PH1
10 6 EC_SMDA PC14 PC15 PC16 2 PQ4
GND 6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K 0.1U_0603_25V7K PR32 G SSM3K7002FU_SC70-3
11 7
1
GND 7 47K_0402_1%
12 8 S
3
GND 8
1
13 9 1 2
2
GND 9 PR31 PR33
8
@ SUYIN_200045MR009G171ZR 1K_0402_1% 12.4K_0402_1% PU3A
1 2 3
P
+
1 2 1
2
O
2
G
PR34 PR35 PD6
For 17" 100_0402_1% 100_0402_1% LM393DG_SO8 RLS4148_LL34-2
4
0.22U_0805_16V7K
PJP3
1
1 BATT_S1
1
1
D
15.8K_0402_1%
2 2
1
PC17
3 BATT_P3 PR36 2 PQ5
3
1000P_0402_50V7K
PR37
4 BATT_P4 6.49K_0402_1% G SSM3K7002FU_SC70-3
4 BATT_P5
5 2 1 +3VLP 2 1 VL S
3
5
1
10 6 EC_SMDA
GND 6
PC18
11 7 EC_SMCA PR38
2
GND 7 100K_0402_1%
12 8
2
GND 8
1
13 GND 9 9
1
PR39
2
@ SUYIN_200045MR009G171ZR 1K_0402_1% 2
PR40
100K_0402_1%
2
2
BATT_TEMPA 33
EC_SMB_DA1 33
EC_SMB_CK1 33
PH2 near main Battery CONN :
BAT. thermal protection at 90 degree C
Recovery at 53 degree C
VL VL
PQ6
2
TP0610K-T1-E3_SOT23-3
1
PR41
PH2 47K_0402_1%
B+ 3 1 +VSBP PR42
100K_0402_1%_TSM0B104F4251RZ 47K_0402_1%
1
3 3
100K_0402_1%
@ 0.22U_1206_25V7K
@ 0.1U_0603_25V7K
1 2
2
1
1
PR43
PC19
PC20
PR44
8
13.7K_0402_1% PU3B
1 2 5
P
2
+
7 2 1
2
TM_REF1 O
6 -
G
VL PR45 PD7
1
22K_0402_1% LM393DG_SO8 RLS4148_LL34-2
4
1 2 PC21 PR46
2
0.22U_0805_16V7K 16.9K_0402_1%
2
PR47
2
100K_0402_1%
PR48
1
0_0402_5% D
1 2 2 PQ7
40 POK
G SSM3K7002FU_SC70-3
@ .1U_0402_16V7K
S
3
1
PC22
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 38 of 45
A B C D
A B C D
B+
@PQ42
@ PQ42
PQ8
FDS4435BZ_SO8 P2
PQ9
FDS4435BZ_SO8 P3
PR49
0.02_2512_1%
B+ PL19
HCB4532KF-800T90_1812 CHG_B+
FDS4435BZ_SO8
1 S D 8
2 S D 7
VIN 8 D S 1 1 S D 8 1 4 2 1 3 S D 6
7 D S 2 2 S D 7 4 G D 5
6 3 3 6 2 3 CSIN
D S S D
5 D G 4 4 G D 5
PQ10
4.7U_1206_25V6K
4.7U_1206_25V6K
4.7U_1206_25V6K
CSIP FDS4435BZ_SO8
1
1 1
1 S D 8
1
PQ12 TP0610K-T1-E3_SOT23-3 2 S D 7
PC24
PC25
PC26
PQ11 PR50 PR167 10_0603_5% 3 S D 6
2
DTA144EUA_SC70-3 200K_0402_1% 3 1 1 2 DCIN 4 G D 5
2
PC23 P3
2
1
1
2 5600P_0402_25V7K PR51
1
PC27 PR54 PQ13 47K_0402_1%
1
PR53 0.1U_0603_25V7K 100K_0402_1% DTC115EUA_SC70-3 1 2
2
47K_0402_1% VIN
2
PR55 PD9
2
2
100K_0402_1% 2 FSTCHG PR52 PD8
1
2
1
1
2.2U_0603_6.3V6K
RB715F_SOT323-3 PR56
PC28
2 PR57 200K_0402_1%
3
1
1
PQ14 10K_0402_1% 1 2 VIN
DTC115EUA_SC70-3 2 1 PU5 PC30
33 FSTCHG 0.1U_0603_25V7K
2
1
100K_0402_1%
1 2 1 24 DCIN 2 1 PQ15 PD11
3
VDD DCIN
1
1
2 PQ16 DTC115EUA_SC70-3 2 1 2
PR58
G SSM3K7002FU_SC70-3 PC29
S PR59 .1U_0402_16V7K 2 23 1SS355_SOD323-2
3
1
6251_EN CSON D
3 EN CSON 22 1 2
1
@ PC32
@PC32 PC33 PC31 2 PACIN
5
6
7
8
680P_0402_50V7K 0.047U_0603_16V7K 0.1U_0603_25V7K G
CSON 1 2 4 21 1 2 CSOP S PQ17
3
CELLS CSOP PR61 PQ18 SSM3K7002FU_SC70-3
PC34 6800P_0402_25V7K 20_0603_5% AO4466_SO8
2 2
1 2 5 ICOMP CSIN 20 2 1
1
2
D PR62 4
2 PQ19 PC35 PR63 6.81K_0402_1% PC36 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2
1
VCOMP CSIP PL3 PR66
S
3
3
2
1
PR67 1 2 7 18 LX_CHG 2.2_0603_5% 1 2 CHG 1 4
ICM PHASE
@ 680P_0603_50V8J @ 4.7_1206_5%
22K_0402_5% @PC37
@ PC37 100P_0402_50V8J
5
6
7
8
PR152
PACIN 1 2 1 2 2 3
37 PACIN
AO4466_SO8
10U_1206_25V6M
10U_1206_25V6M
PC38 6251VREF 8 17 DH_CHG
PR68 .1U_0402_16V7K VREF UGATE PR69 PC39
37 ACON 33 ADP_I
154K_0402_1% 0_0603_5% 0.1U_0603_25V7K
1
PC40
PC41
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1
33 IREF CHLIM BOOT
1
1
PQ21 PR70 4
1
0.01U_0402_25V7K
2
PC130
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1
PQ20
2
1
1
PC42
3
2
1
100K_0402_1% PR72 11 14 DL_CHG
VADJ LGATE
2
20K_0402_1% PR73
2
4.7_0603_5%
2
12 13 PC43
3
1
GND PGND 4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
PR74
Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A 18.2K_0402_1%
1 2
Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A 33 CHGVADJ
1
31.6K_0402_1%
VIN
2
CP mode
1
Vaclim=0.736V(90W) PR70=53.6k PR49=0.015 PR216
309K_0402_1%
Vaclim=1.08V(75W) PR70=24.9k PR49=0.02
PR166
2
Vaclim=1.08V65W) PR70=75k PR49=0.02 10K_0402_1%
1 2 ADP_V 33
1
1
@PD14
@ PD14 PR217
GLZ4.3B_LL34-2 47K_0402_1% PC162
.1U_0402_16V7K
2
2
CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge Vcell CHGVADJ
IREF=0.254V~3.048V 4V 0V
VCHLIM need over 95mV 4.2V 1.882V
4
4.35V 3.2935V 4
CELL number 4 3 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/22 Deciphered Date 2012/07/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 39 of 45
A B C D
5 4 3 2 1
2VREF_51125
0.22U_0603_10V7K
D D
1
PC44
2
PR76 PR77
13K_0402_1% 30K_0402_1%
1 2 1 2
PR78 PR79
B++
20K_0402_1% 19.1K_0402_1%
B++
PL20 1 2 1 2
HCB4532KF-800T90_1812
B+ 2 1 +3VLP
ENTRIP2
ENTRIP1
2200P_0402_50V7K
PR80 PR81
10U_1206_25V6M
10U_1206_25V6M
150K_0402_1% 150K_0402_1%
1
2200P_0402_50V7K
PC45
1 2 1 2
1
PC46
PC48
PC47
4.7U_0805_10V6K
2
2
6
5
6
7
8
PC49
PU6
8
7
6
5
1
C C
ENTRIP2
VREF
ENTRIP1
VFB2
TONSEL
VFB1
25 PQ23
PQ22 P PAD AO4466_SO8
2
AO4466_SO8
7 VO2 VO1 24 POK 38 4
4
8 23 PC51
PR82 VREG3 PGOOD PR83 .1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
3
2
1
0_0603_5% VBST2 VBST1 0_0603_5%
1
2
3
8
7
6
5
5
6
7
8
1
@ 680P_0603_50V8J @ 4.7_1206_5%
@ 680P_0603_50V8J @ 4.7_1206_5%
LG_3V LG_5V
Ipeak=5A 12 DRVL2 DRVL1 19
PR84
PR85
SKIPSEL
PQ24 PQ25
Imax=3.5A
VREG5
220U_6.3V_M
220U_6.3V_M
VCLK
1 AO4712_SO8 AO4712_SO8
GND
37 EN0 1
EN0
VIN
F=305KHz
2
2
+ +
PC52
PC53
4 4
PR86 TPS51125RGER_QFN24_4X4
Total Capacitor 220u,
13
14
15
16
17
18
1
1
499K_0402_1%
2 2
ESR 15mohm
PC54
PC55
B+ 1 2
1U_0402_6.3V6K
2
1
2
3
3
2
1
2
1
100K_0402_5%
1
PR87
PC131
1 2 VL
PC56
4.7U_0805_10V6K
2 PR88
B @ 0_0402_5% B
2
ENTRIP1 22,38 ENTRIP2 22,38 Ipeak=5A
B++
Imax=3.5A
0.1U_0603_25V7K
F=245KHz
2
PC57
Total Capacitor 220u,
1
D D
2VREF_51125
PQ26 2 2 PQ27 ESR 15mohm
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3
VL 2 1
PR89
100K_0402_1%
1
VS 1 2 2 PQ28
G SSM3K7002FU_SC70-3
49.9K_0402_1%
@ 0.01U_0402_16V7K
PR90 S
3
1
100K_0402_1%
1
PR91
PC58
A A
2
2
PL21
HCB4532KF-800T90_1812
1.05V_B+ 2 1 B+
4.7U_1206_25V6K
4.7U_1206_25V6K
1
1
1 1
PC59
PC60
5
6
7
8
PQ29
2
AO4466_SO8
PR92
255K_0402_1% 4
1 2
PR93 PR94
0_0402_5% 2.2_0603_1%
1 2 BST_1.05V1 2
17,27,29,33,36,39 SUSP#
3
2
1
1
PL6
15
14
PC62
1
@PC61
@PC61 PU7 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K BST_1.05V-1 1 2 1 2
EN_PSV
TP
VBST
+1.05VSP
4.7_1206_5%
2 13 DH_1.05V 0.1U_0603_25V7K
TON DRVH
1
Ipeak=10A
PR95
PR96 3 12 LX_1.05V
VOUT LL
5
6
7
8
220U_6.3V_M
100_0603_1%
1 2 4 11 1 2 +5VALW
1 Imax=7A
D
D
D
D
+5VALW V5FILT TRIP
PC63
PR97 +
F=315KHz
2
5 10 14.7K_0402_1% PQ30
VFB V5DRV FDS6670AS_NL_SO8
Total Capacitor 1430u,
1
2
680P_0603_50V8J
6 9 DL_1.05V 4 G
PGOOD DRVL
PGND
ESR 2.5mohm
PC65
PC64
GND
4.7U_0603_6.3V6K @ PC66
@PC66
2
1
S
S
S
47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC67
3
2
1
2 4.7U_0805_10V6K 2
2
PR98
8.25K_0402_1%
1 2
1
PR99
20.5K_0402_1%
2
PL22
HCB4532KF-800T90_1812
1.8V_B+ 2 1 B+
4.7U_1206_25V6K
4.7U_1206_25V6K
1
1
PC68
PC69
For Discrete
5
6
7
8
2
PQ31
AO4466_SO8
PR100
255K_0402_1% 4
3 1 2 3
PR101 PR102
220K_0402_5% 2.2_0603_1%
1 2 BST_1.8V 1 2
17,27,29,33,36,39 SUSP#
3
2
1
1
PL7
15
14
PC71
1
TP
VBST
+1.8VSP
2
4.7_1206_5%
2 13 DH_1.8V 0.1U_0603_25V7K
TON DRVH
1
Ipeak=2A
220U_6.3V_M
PR103
PR104 3 12 LX_1.8V 1
VOUT LL
5
6
7
8
100_0603_1%
Imax=1.4A
PC72
1 2 4 11 1 2 +5VALW PQ32 +
+5VALW V5FILT TRIP PR105 AO4712_SO8
F=315KHz
2
5 10 3K_0402_1%
VFB V5DRV 2
Total Capacitor 220u,
1
680P_0603_50V8J
6 9 DL_1.8V 4
PGOOD DRVL
PGND
ESR 15mohm
PC74
PC73
GND
4.7U_0603_6.3V6K @PC75
@ PC75
2
2
1
47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC76
7
3
2
1
4.7U_0805_10V6K
2
PR106
28.7K_0402_1%
1 2
1
4
PR107 4
20.5K_0402_1%
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 41 of 45
A B C D
5 4 3 2 1
PL23
D
HCB4532KF-800T90_1812 D
1.5V_B+ 2 1 B+
4.7U_1206_25V6K
4.7U_1206_25V6K
1
1
PC77
PC78
TPCA8030-H_SOP-ADV8-5
5
2
PQ33
PR108
255K_0402_1% 4
1 2
PR109 PR110
0_0402_5% 2.2_0603_1%
1 2 BST_1.5V 1 2
27,33 SYSON
3
2
1
1
PL8
15
14
PC80
1
@PC79
@PC79 PU9 1.0UH_PCMC104T-1R0MN_20A_20%
.1U_0402_16V7K BST_1.5V-1 1 2 1 2
EN_PSV
TP
VBST
+1.5VP
2
4.7_1206_5%
2 13 DH_1.5V 0.1U_0603_25V7K
TON DRVH
1
TPCA8028-H_SOP-ADVANCE8-5
Ipeak=11A
PR113
PR111 3 12 LX_1.5V
VOUT LL
220U_6.3V_M
100_0603_1%
1 2 4 11 1 2 +5VALW
1 Imax=7.7A
+5VALW V5FILT TRIP
PC81
PR112 +
F=315KHz
2
5 10 3.9K_0402_1%
C VFB V5DRV C
PQ34
Total Capacitor 940u,
1
1
2
680P_0603_50V8J
6 9 DL_1.5V 4
PGOOD DRVL
PGND
ESR 4.286mohm
PC83
PC82
GND
4.7U_0603_6.3V6K PC84
2
2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC85
7
3
2
1
4.7U_0805_10V6K
2
PR114
20.5K_0402_1%
1 2
1
PR115
20.5K_0402_1% PR257
100K_0402_5%
2
1 2 +3VALW
+1.5V
1 2
8 DDR3_SM_PWROK
1
@PC132
@ PC132 .1U_0402_16V7K +5VALW
@PJ34
@ PJ34
1
JUMP_43X79
For UMA
2
+1.5V
2
1
1
B @PC198
@ PC198 @ PC199
@PC199 B
@PJ17
@ PJ17 1U_0603_6.3V6M 4.7U_0805_6.3V6K
1
JUMP_43X79
2
2
6
PU10 @PU16
@ PU16
2
1 6 5
VCNTL
VIN VCNTL +3VALW VIN
7 POK
2 GND NC 5 VOUT 4 +1.8VP
1
1U_0603_6.3V6M
PC86 @PR254
@ PR254
1
1
PC87
22U_0805_6.3V6M
0.01U_0402_25V7K
4.7U_0805_6.3V6K 3 7 3
VREF NC VOUT
1
PR116 0_0402_5% @ PR255
@PR255
2
PC200
PC201
1K_0402_1% 4 8 1 2 8 2 3K_0402_1%
VOUT NC 27,33 SYSON EN FB
GND
2
9 9
2
2
TP TP
1
@ @
APL5331KAC-TRL_SO8 @ PC202
@PC202 APL5915KAI-TRL_SO8
2.4K_0402_1%
0.01U_0402_25V7K
2
1
PR256
PR117 +0.75VSP
1
0_0402_5% D PR118
10U_0805_6.3V6M
1 2 2 1K_0402_1%
36 SUSP
1
G @
2
2
1
PC90
S PC88
3
@ PC89
@PC89 PQ35 .1U_0402_16V7K
2
.1U_0402_16V7K SSM3K7002FU_SC70-3
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 42 of 45
5 4 3 2 1
5 4 3 2 1
+5VS
2
6
6
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
PR119
+CPU_B+ PL9
33
VR_ON
1_0603_5%
HCB4532KF-800T90_1812
1 2 B+
330P_0402_50V7K
330P_0402_50V7K
10U_1206_25V6M
10U_1206_25V6M
D 1 1 D
220U_25V_M
220U_25V_M
3300P_0402_50V7K
680P_0603_50V8J
1
1
PC126
PC127
PC93
PC94
PC98
PC99
+ +
0.022U_0402_16V7K
PR120 0_0402_5%
1
PC92
PC96
@ PC97
2.2U_0603_6.3V6K
8,23 PM_DPRSLPVR 1 2 PC95
PC91
0.01U_0402_25V7K
2
PR121 0_0402_5% 2 2
2
PR129
PR123
PR124
PR125
PR126
PR130
PR131
PR128
5,8,22 H_DPRSTP# 1 2
5
PR122 0_0402_5%
CLK_ENABLE# 1 2
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PQ36
PR127 0_0402_5% TPCA8023-H_SO8
+3VS 1 2 4
+3VS
1U_0603_6.3V6M
PL10
2
1
2
PC100
1.91K_0402_1%
2.2_0603_1% 0.22U_0603_10V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%
PR140 PC101
3
2
1
1
1 2 1 2 1 4 +CPU_CORE
2
2
PR132
4.7_1206_5%
TPCA8028-H_SOP-ADVANCE8-5
BOOT_CPU1
@ PR134
PR133
48
47
46
45
44
43
42
41
40
39
38
37
2 3
1
499_0402_1% PU11
10K_0402_1%
3.65K_0805_1%
PR141
3V3
CLK_EN#
DPRSTP#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
2
@ PQ38
PR135
PR136
PQ37 1_0402_5%
1
TPCA8028-H_SOP-ADVANCE8-5
1 2
1 36 4 4
2
8,23,33 VGATE PGOOD BOOT1
@ PC102
680P_0603_50V8J
PR137 @ 0_0603_5%
2
5 H_PSI# 2 35 UGATE_CPU1 1 2
PR138 4.99K_0402_1% PSI# UGATE1
2
PC125 .1U_0402_16V7K PMON 1 2 3 34 PHASE_CPU1 VSUM 1 2
3
2
1
3
2
1
PMON PHASE1
2 1 VCC_PRM
1 2 4 33 ISEN1 PC103
PR139 147K_0402_1% RBIAS PGND1 0.22U_0603_10V7K
C VR_TT# LGATE_CPU1 C
5 VR_TT# LGATE1 32 +CPU_B+
330P_0402_50V7K
330P_0402_50V7K
10U_1206_25V6M
10U_1206_25V6M
@PR142
@ PR142 4.22K_0402_1% PH3
1
1 2 1 2 6 NTC PVCC 31
1
TPCA8023-H_SO8
PC128
PC129
PC104
PC106
@ 100K_0603_1%_TH11-4H104FT 7 ISL6266AHRZ-T_QFN48_7X7 30 LGATE_CPU2
2
SOFT LGATE2
1 2
2
PQ39
@PC105
@ PC105 0.015U_0402_16V7K 8 29
0.022U_0603_25V7K PC107 OCSET PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2 PL11
PR143 13K_0402_1% 10 27 UGATE_CPU2 0.36UH_PCMC104T-R36MN1R17_30A_20%
COMP UGATE2
1 2
3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2
4.7_1206_5%
1 2 PR144
1
1000P_0402_50V7K PC109 12 25 2.2_0603_1% PC108 2 3
FB2 NC
@ PR146
PR145 8.25K_0402_1% 0.22U_0603_10V7K
TPCA8028-H_SOP-ADVANCE8-5
DROOP
1 2 TP 49
VDIFF
ISEN2
ISEN1
VSUM
VSEN
GND
VDD
RTN
DFB
1
VIN
@ PQ41
3.65K_0805_1%
PQ40
VO
1 2
1 2
1
10K_0402_1%
PR147
TPCA8028-H_SOP-ADVANCE8-5
1
PR148
680P_0603_50V8J
PC110 1000P_0402_50V7K 4 4
13
14
15
16
17
18
19
20
21
22
23
24
@ PC111
PR149
ISEN1 1_0402_5%
2
PR151 97.6K_0402_1% PC112 270P_0402_50V7K
2
1
1 2 2 1 ISEN2
3
2
1
3
2
1
2
1 2 +5VS PR154 @ 0_0603_5%
PR153 PR150 1_0603_5% VSUM 1 2
1
1 2 1K_0402_5% PC113
1U_0402_6.3V6K
2
PC114 100P_0402_50V8J 1 2
2
PR156
B PR155 100_0402_1% PC116 2200P_0402_50V7K 10_0603_5% PC115 B
1 2 1 2 1 2 +CPU_B+ 0.22U_0603_10V7K
VCC_PRM
1
1 2 PC117 ISEN2
0.1U_0603_25V7K
PR157 1K_0402_1%
2
PC118 330P_0603_50V8
6 VCCSENSE 1 2 1 2
VSUM
1
PR158 0_0402_5%
1
2.61K_0402_1%
PC119 PC120
PR160
PR159 20_0402_5% 1 2
6 VSSSENSE PR161 0_0402_5%
2
1
11K_0402_1%
PC121 180P_0402_50V8J
PR163
PR162 1 2
2
20_0402_5% 1 2 1 2 PH4
10KB_0603_5%_ERTJ1VR103J
2
VCC_PRM 1 2
PC124 0.22U_0402_6.3V6K
PC123 2 1 2 1
0.22U_0603_10V7K
A A
PREMP P41-1.05VSP/1.8VP Change PR96 422 ohm to 100 ohm Avoid 2nd source RT8209B can not power on(2009/07/27)
Change PC64 1U to 4.7U
PREMP P42-1.5VP/0.75VSP Change PR111 422 ohm to 100 ohm Avoid 2nd source RT8209B can not power on(2009/07/27)
Change PC82 1U to 4.7U
PREMP P42-1.5VP/0.75VSP Change PR112 14.7k to 3.9k Set 1.5V OCP to 13.25A(2009/07/27)
PREMP P40-3VALWP/5VALWP Change PC52, PC53 SF22001M200 to SF000001H00 SF22001M200 is forbids to use (2009/08/04)
PREMP P41-1.05VSP/1.8VP Change PC63, PC72 SF22001M200 to SF000001H00 SF22001M200 is forbids to use (2009/08/04)
PREMP P42-1.5VP/0.75VSP Change PC81 SF22001M200 to SF000001H00 SF22001M200 is forbids to use (2009/08/04)
MP P42-1.5VP/0.75VP Change High,Low side Mosfet and Choke. (2009/06/18)
Add bead on B+ node
MP P38-BATTERY CONN / Change PR33 13.7k to 12.4k Change resistor for OTP (2009/09/01)
OTP Change PR37 15.4k to 15.8k
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401791 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 30, 2009 Sheet 44 of 45
5 4 3 2 1
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A4982
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401791
Date: Wednesday, December 30, 2009 Sheet 45 of 45
5 4 3 2 1
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