ISSN 2321 3361 © 2020 IJESC

Research Article Volume 10 Issue No.3

Design and Analysis of 16X16 Multiplier using Kogge Stone Adder

and Approximate 15-4 Compressor
R. Agnes Lilly1, V. Abinaya2
B.E Student1, 2
Department of Electronics and Instrumentation Engineering
St. Joseph’s College of Engineering, Semmancheri, Chennai, India

Abstract:
The major role of electronics device is to provide compact area with high speed performance. The most complex module in digital
building blocks system is multiplier. So, Multiplier is chosen and approximate computing is applied on it so that it can be used in
electronic applications like multimedia etc. A design approach of 16-bit Wallace Tree approximate multiplier with 15-4
compressor is considered to provide more reliability. The 16x16 Wallace tree multiplier is synthesized and simulated using Xilinx
ISE 14.7 software. Multiplier involves generation of partial products and addition of partial products which takes longer time for
computation. Using compression technique in Wallace tree approach, the number of partial products are reduced before addition
is performed. This paper focuses on Design and Analysis of 16x16 Multiplier to optimize parameters like Area and Delay.
Optimization is done using 15-4 approximate compressor. Here, we modify the design by replacing the 4-bit Parallel Adder by
4-bit Kogge Stone Adder in approximate 15-4 compressor and also compare the performance of both the designs of the 16x16
Multiplier. Thus, the better optimization of area and delay is identified.

Keywords: Area, Compressor, Delay, Kogge Stone Adder, Multiplier, Parallel Adder, Wallace tree.

I. INTRODUCTION Add the multiplicand into an accumulator, if the LSB of

Multiplier is ’1’. Shift the Multiplicand one bit to the left and
Two major concerns in optimization have been delay and area Multiplier one bit to the right. Stop when all the bits of the
in VLSI circuit design. Multiplier circuit is chosen to achieve Multiplier are zero.
reduction in the area and delay of circuits. Multipliers involve
generation and addition of partial products. Owing to large Where,Y=Yn-1Yn-
2………………...Y2Y1Y0(Multiplicand).X=Xn-1Xn-
number of partial products, the computation time has become
high. In order to reduce the computation time, Wallace Tree 2………………………….X2X1X0 (Multiplier)
Approach was developed. Accurate compressors have been
used in Wallace tree Approach to reduce the number of partial
products. Though accurate compressors give error-free results
area and delay does not reach the best level of optimization.
To achieve better level of optimization, approximate
compressors came into existence. These compressors generate
approximate results and also they reduce the area and delay.
This idea can be utilized in error tolerant applications. In
Image Processing, the size can be reduced by using
multipliers. Kogge Stone Adder is incorporated in the existing
design and implanted in the compressor for improved speed
and for better optimization. This is carried out in simulation
with the help of Xilinx software. So, the main objectives are to
achieve better optimization in area and delay of the multiplier
circuit, to design the 16X16 multiplier using Wallace tree Figure.1. nXn Multiplication Process
Approach and approximate compressor, to obtain the outputs
of the design using simulation, to analyze the performance of XY multiplied terms are the intermediate partial products. P
existing design and proposed design. terms are the final output of the multiplication which is
nothing but the addition of partial products. The number of
II. MULTIPLIER rows of partial products are n and the number of bits in the
result would be 2n where n is the number of bits in the
Multipliers have an important role in various applications. multiplier and multiplicand.
With many advancements in technology, many researchers
have been tried for creating new designs for multiplier with the III. COMPRESSORS
best features like high speed, low power consumption, layout
regularity, less area or even combination of any of these Number of partial products to be added in the Multiplier is the
features in a multiplier to make the best design which paves main parameter that strongly proves it’s performance. So, the
way for compact VLSI implementation. The most common performance of a multiplier can be improved by reducing the
multiplication algorithm used is “add and shift” algorithm. number of partial products which can be done using

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compressors. Compressors are a critical component in a
Multiplier since it can add several partial products at once to
reduce logic depth of the generated partial product. In 3-2
compressor, it compresses the 3 bits of the input into 2bits
which is what taking place in Full adder circuit. In 4-2
compressor, it uses both the full adder as well as the half adder
circuits. Therefore, compressors can also be said that it
constitutes full adder circuit or half adder circuit or a
combination of both. With this idea many compressors were
developed that is big compressors can be constructed using
small compressors. There is a major division in compressors
such as accurate compressors and approximate compressors.
Accurate compressors give accurate results whereas
Approximate compressors give approximate results with
which better optimization of parameters is done which cannot
be done in accurate compressors. Here, 15-4 approximate
compressor is used.
IV. WALLACE TREE APPROACH
It multiplies two integers in a digital circuit where hardware is
efficiently implemented. It was invented by the Australian
Computer Scientist Chris Wallace in 1964. Compression
technique is used in the Wallace Tree so that the number of
partial products can be reduced before addition is performed.
They partition the partial products into columns and in each
columns, they group up the bits and compress them.
V. LITERATURE SURVEY
Microprocessors and Digital Signal Processors (DSP) are
playing a significant role to handle the complexity of digital
signal. In 2008, Dr. Liu researched that 95% of the processors
in the market are based on digital signal [1]. K . K . P a r t h I a
dds that digital signal processors take care of convolution,
correlation and filtering of digital signal [2]. Multipliers,
shifters and adders are mainly used to accomplish these tasks.
Among the three modules, multiplier is the most complex one.
The fact that multipliers take more time and consume higher
power than other two modules is mentioned in the year 2013
by Y.Kim, Y.Zhang, P.Li [3].
Multipliers have three phases - generation of partial products,
reduction of partial products and final stage addition.
Reduction of partial products take much time and power in the
multiplier. Many techniques were proposed to reduce the
critical path in the multiplier. Among them, the use of
compressors in partial product reduction stage is the most
popular one. Compressors are basic circuits which are made of
full adders or half adders to count the number of “ones” in the
input. Several compressors are required in the partial product
reduction stage [4]-[5].
Recently developed method is to design the Approximate
15-4 compressor by using approximate 5-3 compressor. This
is implemented in 16X16 multiplier Approximate 5-3
compressors are used in 4 different ways in 15-4 compressor.
Simulation results are compared with the accurate 15-4
compressor [6]-[7].
Various compressors such as 3-2, 4-2, 5-2 and 5-3 were
proposed by researchers in the last 20 years. The 3-2, 4-2 and
5-2 compressors are the basic components in many
applications, in particular partial product summation in
multipliers. In 2007, Novel architectures and designs of high
speed, low power 3- 2, 4-2 and 5-2 compressors capable of
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operating at ultra-low voltages are presented. The architecture
lays emphasis on the use of multiplexers in arithmetic circuits
that result in high speed and efficient design [8]. In 2008,
Compressor was designed which uses bit sliced adder
architecture to exploit the parallelism in the computation of
sum of 15 input bits by 5 full adders. This compressor is
centered around the design of a novel 5-3 compressor. Here,
the compressor makes use of minimum hardware resources
and is tested using 14 transistor and 10 transistor adder designs
[9].
In 2009, 16X16 bit multiplier was developed using high speed
compressor. It reduces the number of adders by introducing
special kind of adders that are capable of adding 5 or 6 or 7
bits per decade [10].
In 2010, a new design concept that engaged accuracy as a
design parameter in multipliers was proposed. By introducing
accuracy as a design parameter, the bottleneck of conventional
digital IC design techniques can be breakthrough to improve
on the performances of power consumption and speed [11]. In
2011, novel architecture of multiplier with error tunable
characteristics was designed. It highlighted a fact that power
savings can be done in a multiplier based on designs [12]. A
novel approximate multiplier with low power consumption
and a shorter critical path than traditional multipliers was
designed [13].
In 2012, Wallace Tree Carry Save Adder structures were used
to sum the partial products in reduced time. Speed of the
Wallace tree multiplier was improved by using compressor
technique [14]. Approximate computing has gained significant
attention due to the popularity of multimedia applications. A
novel inaccurate 4-2 counter that can effectively reduce the
partial product stages of the Wallace Multiplier was designed
in 2013 [15]. An improved version of tree based multiplier
architecture called Wallace tree multiplier was developed. It
used Carry Save Addition Algorithm to reduce the latency
[16]. In 2014, Multipliers based on Wallace reduction
provided an area efficient strategy [ 17]. A new power and
area efficient Approximate Wallace Tree Multiplier for error
tolerant applications was presented. It used bit width aware
approximate multiplication algorithm for optimal design of the
multiplier [18]. To give fruitful results for unsigned integers,
to reduce delay and to enhance speed Wallace tree multiplier is
used [19].
In 2015, a design approach was developed for compressor
based approximate multipliers. It also highlighted a fact that it
is attractive for error resilient applications and for arithmetic
applications [20]. Analysis of approximate compressors for
Multiplication was done. It proposed a fact that inexact
computing is an attractive paradigm for digital processing at
nanometric scales and also for computer arithmetic designs.
This analysis dealt with two new approximate 4-2 compressors
for utilization in a multiplier [21]. Approximate Multiplier was
designed where both the approximation and truncation were
considered. In this it proposed three compressors with an
accuracy constraint for the partial product reduction [ 22]. By
comparing the hardware complexity of designs, critical path
delay, and error rate and power consumption for the three
designs of approximate compressors, study of approximate
compressors for multiplication using FPGA is done [23].
VI. EXISTING SYSTEM
In this, multiplier used 15-4 approximate compressor which
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constitutes 4-bit parallel adder for adding the partial products.
It uses 5 full adders to get 15 inputs to it. Every Full adder
gives 2 inputs. Here two approximate 5-3 compressors are
used where one compressor gets all the sums of the full adders
and the other one takes all the carries generated by the full
adders. Since each compressor gives 3 outputs, a null bit is
added to it for 4-bit parallel addition using 4- bit parallel
adder. Following figure will show all of its contents and how
they are constructed together.
Figure.2. 15-4 Approximate Compressor using 4-bit
Parallel Adder
Figure.3. Design of 5-3 approximate compressor
Here, output 2 is approximated and following are the output
equations of this figure 3.
Figure.4. Output Equations of the approximate 5-3
compressor
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VII. PROPOSED SYSTEM
In this multiplier, almost same design is used but with the
small alteration. In the existing system, each adder used in the
4-bit parallel adder gets carry input only when previous adder
finishes it’s operation and it causes delay. So, instead of 4-bit
parallel adder 4-bit Kogge Stone Adder is used. Therefore, it
involves 16X16 Multiplier where Wallace Tree approach is
used in which various compressors are used. Highest form of
compressor used is approximate 15-4 compressor in which 4-
bit Kogge Stone Adder is used for final stage addition.
Figure.5. 16x16 Multiplier using Wallace tree approach
Figure.6. 15-4 Approximate Compressor using 4-bit Kogge
Stone Adder
4-bit Kogge Stone Adder is a parallel prefix adder which is a
form of carry look ahead adder. Using 3 stages of operation it
computes the carry. Equations used in each stages is given
below. At pre-processing stage, P=Ai XOR Bi, G=Ai AND Bi
At prefix stage, P=Pi AND Piprev,
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G=(Pi AND Giprev) OR Gi
At final computation, Gi=Ci ,Si=Pi XOR Ci-1

Figure.9. Interior View of the RTL Schematic

Figure.7. Working of Kogge Stone Adder

It gets the inputs and produces generate and propagate signals.

Then, it takes up two pairs of generate and propagate signals
and continues the computation and finally it founds the carry
using which it results the sum output. This process takes place
by using the different equations at three different stages.

VIII. RESULTS AND COMPARISON

Using Xilinx ISE 14.7, simulation output is obtained. RTL

Figure.10. Simulation Output Waveform
schematic and the simulation output (if inputs are same) are
same for both the existing and the proposed. RTL Schematic
But the Device Utilization Summary (Area) and Delay
may look the same from outside for both the systems but on
Analysis (Delay) differ in both the systems.
the inside, it is actually different since alteration in the circuit
is done. The circuits used can be clearly seen when it is
zoomed in.

Figure.11. Device Utilization Summary of Existing System

In the Device Utilization Summary, Area in terms of LUTs.

(Look up Table). Following figure gives the details about
delay involved in the existing system circuit.

Figure.8. RTL Schematic Figure.12. Delay Analysis of Existing System

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 IX. CONCLUSION

The approximate 16x16bit Wallace tree multiplierusing15- 4

Figure.13. Device Utilization Summary of Proposed System
compressor architecture has been designed and synthesized
using on Spartan 6 XC3S100E board and simulated in Xilinx
ISE 14.7. The performance of proposed Multiplier with Kogge
Stone Adder is compared with the same architecture of
multiplier using parallel adder. It can be inferred that 16x16
multiplier architecture using 15-4 compressor with Kogge
Stone Adder is faster compared to multiplier with parallel
adder. In future the performance of the proposed multiplier can
be improved and applied in applications like video and image
processing.

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Figure.14. Delay Analysis of Proposed System
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