COMP-261 Computer Organization and

Assembly Language

Lecture
Instruction Set Architecture (ISA
Dr Hashim Al

Fall - 2021

Department of IT and Computer Scienc

Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology

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Introduction
Software
• Computing Platform
• Hardware — To execute program
Application
• Gates: NOR, NAND

• Digital Circuit: Combinational, Sequential

OS
• CPLDs, ASICs, FPGAs
Compiler Firmware
• Programmable Processor: Registers, ALU, Control Unit

• Memory: ROM, RAM

ISA
• I/O peripherals

• Software — Program to run

CPU I/O
• How can we execute program on our own design processor?

• Higher Level Languages

Memory
• Assembly Language

Digital Circuits
• Low Level Languages [Machine Level]

Gates & Transistors

• What is a good ISA?
Hardware
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Introduction
Software
• What is a good ISA?

• A functional contract
Application
OS
• All ISAs similar in high-level ways

Compiler Firmware
• But many design choices in details

• Two philosophies: CISC/RISC

ISA

CPU I/O
• Good ISA…

Memory
• Enable high performance

Digital Circuits
• Compatibility is a powerful force
Gates & Transistors
• Tricks: binary translation, ISAs Hardware
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What Constitutes ISA?
• Main Features: Operations:
• How many?

• Which ones? Operands:

• Set of basic/primitive operations
• How many?

• Location

• Storage structure — Registers/Memory

• Types

• How to specify?

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• How addressees are speci ed
Instruction Format:
• Size

• How many formats?

• How instructions are encoded

• We will look at some of the decisions facing an instruction set

architect, and

• How those decisions were made in the design of the MIPS

instruction set.

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The Big Picture
• Assembly Language

• Interface the architecture presents to user,

compile, and operating system

• “Low-Level” instructions that use the

datapath and memory to perform basic types
of operations

• Arithmetic: ADD, SUB, MUL, DIV etc.

• Logical: AND, OR, SHIFT etc.

• Data Transfer: LOAD, STORE

• (Un)conditional Branch: Jump, branch on

condition

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Software Layers

• High-level languages such

as C, C++, FORTRAN, JAVA
are translated into assembly
code by a compiler.

• Assembly language
translated to machine
language by assembler.

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Basic ISA Classes
• Memory to Memory Machines
• Can access memory directly in instructions: e.g., Mem[0] = Mem[1] + 1

• But we need storage for temporaries

• Memory is slow (hard to optimize code)

• Memory is big (need lots of address bits in code —> large code)

• Architectural Registers
• registers can hold temporary variables

• registers are (unbelievably) faster than memory

• memory tra c is reduced, so program is sped up 


(since registers are faster than memory)

• code density improves —> smaller code 


(since register named with fewer bits than memory location)

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Basic ISA Classes (cont’d)
• Accumulator (1 register):

• General Purpose Register File

(Load/Store):
load R1, B
add R1, C
store A, R1

Basic ISA Classes (cont’d)

• General Purpose Register File
(Register-Memory): load R1, B
load R2, C
add R1, R1, R2
store A, R1

• Stack (not a register le but an operand stack)

• Comparison:
• Bytes per instruction? Number of Instructions? Cycles per instruction?
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Comparing Number of Instructions
• Code sequence for C = A + B for four classes of instruction sets:

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General Purpose Register Machines Dominate
• Literally all machines use general purpose registers

• Advantages of registers

• registers are faster than memory

• memory tra c is reduced, so program is speedup 


(since registers are unbelievably faster than memory)

• registers can hold variables

• registers are easier for a compiler to use:
(A*B) - (C*D) - (E*F) —> can do multiples in any order vs. Stack

• Code density improves

(since register named with fewer bits than memory location)

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Example: MIPS Assembly Language Notation
• Generic

• Addition

• Subtraction

• f=(g+h)-(i+j)

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Instruction Set De nition (Programming Model)
Objects = architected entities
Operations = instruction types

= machine state
• Data operation
• Registers • Arithmetic (add, multiply, subtract,
• General purpose
divide, etc.)

• Special purpose (e.g. program • Logical (and, or, xor, not etc.)

counter, condition code, stack • Data transfer

pointer)
• Move (register —> register)

• Memory locations
• Load (memory —> register)

• Linear address space: 0, 1, 2, …, • Store (register —> memory)

2n-1

• Instruction sequencing
• Branch (conditional, e.g. less than,
greater than, equal)

• Jump (unconditional)
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Registers and Memory (MIPS)
• 32 registers provided
• R0 .. R31

• You’ll sometimes see $ instead of R

(R6 and $6 both denote register 6)

• Some special-use registers

• Register R0 is hard-wired to zero

• Register R29 is the stack pointer

• Register R31 is used for procedure return address

• Arithmetic instructions operands must be registers

• This is a load/store machine! Must load all data to registers before using it.

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Memory Organization
• Viewed as a large, single-dimension array, with an address.

• A memory address is an index into the array

• "Byte addressing" means that the index points to a byte of memory.

• Bytes are nice, but most data items use larger "words"

• For MIPS, a word is 32 bits or 4 bytes.

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Memory Organization
• Bytes are nice, but most data items use larger “words"

• For MIPS, a word is 32 bits or 4 bytes.

• 32-bit computer
• 232 bytes with byte addresses from 0 to 232-1

• 230 words with byte addresses 0, 4, 8, ... 232-4

• Words are aligned

• Big Endian: address of MSB = word address —> xx00

• Little Endian: address of LSB = word address —> xx00

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Execution Model
Instruction Set Architecture

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Programmable Machine
• Computing Machine
• Input — Code + Data

• Output — Desired Output

• Sequential Execution Model

• Program is a sequence of instructions

• Instructions are atomic and executed sequentially

• Stored Program Concept

• Program and data both are stored in memory

• Instructions are fetched from memory for

execution
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Instruction Execution Model
• The computer is just nite state machine

• Registers (few of them, but fast)

• Memory (lots of memory, but slower)

• Program counter (next instruction to execute)

• A computer executes instructions

• Fetches next instruction from memory

• Decodes it ( gure out what it does)

• Reads its inputs (registers & memory)

• Executes it (adds, multiply, etc.)

• Write its outputs (registers & memory)

• Next instruction (adjust the program counter)

• Program is just “data in memory”

• Makes computers programmable (“universal”)
Instruction —> Insn
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The Sequential Model
ISA — Tasks to do
Get instruction from memory

Instruction Format/Decoding
Operand Fetch — Addressing Modes
Operation Codes and Data Types
Addressing Modes
Instruction Sequencing

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 Executing an Assembly Instruction
• Program Counter holds the
instruction address

• Sequencer (FSM) fetches

instruction from memory and puts it
into the Instruction Register

• Control logic decodes the

instruction and tells the register le,
alu and other registers what to do

• If an ALU operation (e.g. add) data

ows from register le, through ALU
and back to register le

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fl
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Register File Program Execution
Register File Memory
4 bytes wide
R0 0 Program Counter
R1 0x00000000 0x00 add R4, R0, R0
R2
R3 00000006 Instruction Register 0x04 sub R1, R3, R4
R4 00000004 0 add R4, R0, R0 0x08
……
R30
R31

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Register File Program Execution
Register File Memory
4 bytes wide
R0 0 Program Counter
R1 00000006 0x00 add R4, R0, R0
0x00000004
R2
R3 00000006 Instruction Register 0x04 sub R1, R3, R4
R4 00000000 sub R1, R3, R4 0x08
……
R30
R31

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Register File Program Execution
Register File Memory
4 bytes wide
R8 Program Counter
R9 0x00 add R8, R17, R18
R16 ???
R17 0x00000002 Instruction Register 0x04 add R9, R19, R20
R18 0x00000003 0x08 sub R16, R8, R9
R19 0x00000001
R20 0x00000004 Example:
… f=(g+h)-(i+j)
R16 == f
R17 == g
R18 == h
R19 == i
R20 == j
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Accessing Data from Memory
• ALU generated address

• Address goes to Memory

Address Register

• When memory is accessed,

results are returned to Memory
Data Register

• Notice that data and instruction

addresses can be the same -
both just address memory

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 Memory Operations - Load
Register File Memory
4 bytes wide
R0 Program Counter
R1 0x00000004
0x00000000 0x00 addi R5, R0, 0x14
R2
R3 Instruction Register 0x04 lw R6, 0 (R5)
R4 lw R6,
addi 0(R5)
R5, R0, 0x14 0x08
R5 0x00000014
R6 0x12345678 ➡Loading data from Memory
0x0C
… R6 <— mem[0x14]
Assume &A = 0x14
0x10
• addi: adds 16-bit constant to source register
➡Address can be computed by adding an 0x14 0x12345678
o set to register

LW R6, 0(R5)
R6 <— mem[R5+0]
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Memory Operations - Store
Register File Memory
4 bytes wide
R0 Program Counter
R1 0x00000008 0x00 addi R5, R0, 0x18
R2
R3 Instruction Register 0x04 addi R6, R0, 200
R4 sw R6, 0 (R5) 0x08 sw R6, 0 (R5)
R5 0x00000018
R6 0x000000C8 ➡Storing data to memory works 0x0C
… essentially the same way

A = 200; assume &A = 0x18 0x10

mem[0x18] <— 200
0x14 0x12345678
addi R5, R0, 0x18

addi R6, R0, 200

0x18 0x000000C8
sw R6, 0(R5)
200 = 0xC8
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 Instruction Format (Machine Language)
• add R8, R17, R18
• is stored in binary format as

00000010 00110010 01000000 00100000

• MIPS lays out instructions into “ elds”

Field Description
op Operation of the instruction
rs First register source operand
rt Second register source operand
rd Register destination operand Why are there 5
shamt Shift amount bits in the register
funct Function (select type pf operation) eld??
• add = 3210

• sub = 3410
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 MIPS Instruction Formats
• More than more than one format for instructions, usually
• Di erent kinds of instructions need di erent kinds of elds, data

• Example: 3 MIPS instruction formats

Questions:
I-format: How big an immediate can you have?
(What is the maximum value?)
J-format: How far can you jump in instructions?
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 Constants
• Small constants are used quite frequently (50% of operands)
e.g., A = A + 5;
B = B + 1;
• Solutions? Why not....
C = C - 18;
• ...just put 'typical constants' in memory and load them.

• ...just create hard-wired registers (like $zero) for constants like one.

• MIPS Instructions: addi $29, $29, 4

slti $8, $18, 10 How do we get these
constants in a
andi $29, $29, 6 e cient way?
ori $29, $29, 5

• How do we make this work?

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Loading Immediate Values
• How do we put a constant (immediate) value into a register?
• Put the value 100 into register R6: R6 <— R0 + 100 = 0+100 = 100

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MIPS Machine Language

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Loading Immediate Values
• What’s the largest immediate value that can be loaded into a register?

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Control (Instruction Sequencing)
• MIPS unconditional branch instructions:

• j label
• Example:

Go here if
$4 != $s5

Go here
always
• OK, so with these--Can you build a simple for(...) {...} loop?

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Branch Instructions
• They exist because we need to change the program counter

• bne (branch not equal) compares regs and branches if regs “!=”

• j (jump) goto address, unconditional branch

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Branch Instructions
• Branch instructions are used to implement C-style loops

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Addresses in Branches and Jumps
• Instructions

• Formats

• But, the addresses in these elds are not 32 bits !

• How do we handle this?

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Addresses in Branches and Jumps
• Instructions

• Formats

• Could specify a register and add it to this 16bit address

• Use the PC + (16-bit relative word address to nd the address to jump to)

• Note: most branches are local (“principle of locality”)

• Jump instructions just use the high order bits of PC

• 32-bit jump address = 4 (most signi cant) bits of PC concatenated with 26-bit word address (or 28-
bit byte address)

• Address boundaries of 256 MB

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Branch Instructions
• Example

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Generic Examples of Instruction Format Widths

• Better for generating compact code

• Easier to use for generating assembly code

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Summary of Instruction Formats
• If code size is most important, use variable length instructions

• If performance is most important, use xed length instructions

• Recent embedded machines (ARM, MIPS) have an optional mode to

execute subset of 16-bit wide instructions (Thumb, MIPS16); per
procedure, decide which one of performance or density is more important

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Observation
• “Simple” computations, movements of data, etc., are not always “simple” in terms of a
single, obvious assembly instruction

• Often requires a sequence of even more primitive instructions

• One options is to try to “anticipate” every such computation, and try to provide an assembly
instruction for it

(Complex Instruction Set Computing = CISC)
• PRO: assembly programs are easier to write by hand

• CON: hardware gets really, really complicated by instructions used very rarely.

• Compilers might be harder to write

• Other option is to provide a small set of essential primitive instructions 


(Reduced Instruction Set Computing = RISC)
• CON: anything in a high level language turns into LOTS of instructions in assembly
language

• PRO: hardware and compiler become easier to design, cleaner, easier to optimise for
speed, performance

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Summary
• Architecture = what’s visible to the program about the machine
• Not everything in the deep implementation is “visible”

• Microarchitecture = what’s invisible in the deep implementation

A big piece of the ISA = assembly language structure

• Primitive instructions, execute sequentially, atomically

• Issues are formats, computations, addressing modes, etc.

• We do one example in some detail: MIPS

• A RISC machine, its virtue is that it is pretty simple

• Can pick up the assembly language without too much memorisation

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MIPS Instruction Set Architecture
(Review)

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MIPS — Key Points
• MIPS is a general-purpose register, load-store, xed-instruction-length
architecture.

• MIPS is optimised for fast pipelined performance, not for low instruction
count.

• Four principles of ISA

• Simplicity favours regularity

• Smaller is faster

• Good design demands compromise

• Make the common case fast

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MIPS Instruction Formats

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MIPS — Accessing the Operands

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MIPS Instruction Set

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MIPS — Instructions / Operations
• Arithmetic • Data movement
• ADD, SUB etc.
• Load, Store

• Logical • Procedure linkage

• AND, OR etc.

• Relational
• Less than etc.

• Branch/jump
• Conditional Branch

• Unconditional Jump

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MIPS ISA Features — Addressing
Purpose Addressing modes
• Operand sources
• Immediate

• Result destinations
• Register

• Jump targets • Base/index

• PC relative

• (pseudo) Direct

• Register indirect

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