COA

UNIT1
 Why COA?
• to know how system works internally
• knowledge is helpful in improving performance
• Performance-> The speed with which a computer
executes programs is affected by the design of its
instruction set, its hardware and its software,
including the operating system, and the
technology(VLSI)
---- improving technology
---- using parallelism( instruction level, multicore,
multiprocessors)
 COMPUTER ARCHITECTURE Vs
COMPUTER ORGANISATION
Computer Architecure

• The design, arrangement , construction or organization of the different

parts of a computer system is known as Computer Architecture. It is the
conceptual design and fundamental operational structure of a computer
system.
• Computer Architecture is to design a computer that maximizes
performance while keeping power consumption in check, costs low
relatively to an amount of expected performance and it is also reliable.
• There are many aspects to be considered like Set Design, Functional
Organization, Logic Design and Implementation are the first prior.
Computer Organization
----Computer organization refers to the operational units and their
interconnection that realize the architecture specification. Computer
organization deals with physical aspects of computer design, memory and
their types and microprocessors design.
Role of computer architect: to make design trade-offs across the h/w-s/w
interface to meet functional, performance and cost requirements.
 COMPUTER TYPES
• EMBEDDED SYSTEMS
• PERSONAL SYSTEMS
--DESKTOP, WORKSTATION(minicomputers),PDAs,
LAPTOPs, NOTEBOOK)
--also called microcomputers
• SERVERS AND ENTERPRISE(BUSINESS) SYSTEMS
-- also called mainframes
• SUPERCOMPUTERS
 Functional Units of Digital System
• 5 units- CU, ALU, I/P, O/P, MEMORY
 Memory Operations
• Both program instructions and data operands are stored in
the memory.
• During program running, they need to be moved b/w main
memory and processor
• two basic operations involving the memory are needed,
namely, Read and Write.
• The Read operation transfers a copy of the contents from a
specific memory location to the processor
RD signal carries value – MAR (a main memory address)
• The Write operation transfers an item of information from
the processor to a specific memory location, overwriting
the former contents of that location.
WR signal carries 2 values- MAR,MDR
 Basic Operational Concepts
primary function of a computer system is to
execute a program
 To perform the execution of an instruction by
processor.
After processing the data, store the results
----the result is either stored in the memory for
further reference, or it is sent to the outside
world through some output port.
Interconnection between Processor and Memory
(book)
The processor-memory interface
• If a word is to be read from the memory, the interface
sends the address of that word to the memory along
with a Read control signal.
( RD carries value in MAR)

• If a word is to be written into memory, the interface

transfers both the address and the word to the
memory along with a Write control signal
(WR carries values in MAR and MDR)
• Note: RD and WR are 2 basic memory operations
 Special function registers:-
PC,IR,MAR,MDR
• The Program counter (PC) monitors the execution of instructions.
---- Individual instructions are brought from the memory into the processor, which
executes the specified operations. Data to be used as instruction operands are also
stored in the memory
• The instruction register IR is used to hold the instruction that is currently being
executed.
----The contents of IR are available to the control unit, which generate the timing
signals that control, the various processing elements involved in executing the
instruction.
• general-purpose registers , often called processor registers. They serve a variety
of functions, including holding operands that have been loaded from the memory
for processing
• Example: The two registers MAR and MDR (part of general-purpose registers )are
used to handle the data transfer between the main memory and the processor.
------The MAR holds the address of the main memory to or from which data is to be
transferred.
----The MDR contains the data to be written into or read from the addressed word of
the main memory.
 Basic Operational steps
to perform a given task:-
• LOAD PROGRAM FROM SECONDARY MEMORY TO MAIN
MEMORY
----an appropriate program consisting of a list of instructions is stored in the
memory. It is often transferred there from secondary storage through the
input unit.

• TO BEGIN EXECUTION, SET PC TO FIRST INSTRUCION OF

THE PROGRAM.

• LOAD INDIVIDUAL INSTRUCTIONS FROM MAIN M. TO

REGISTERS ( AS PER PC)
----Individual instructions are brought from the memory into the processor,
which executes the specified operations.
----Instructions such as Load, Store, and Add perform data transfer and
arithmetic operations.
----When the addressed word (in this case, the first instruction of the program)
has been fetched from the memory it is loaded into register IR. At this
point, the instruction is ready to be interpreted and executed
• LOAD OPERANDS/DATA WHEN NEEDED ACCORDING TO
INSTRUCTION BEING EXECUTED
----Data to be used as instruction operands are also stored in the
memory
----If an operand that resides in the memory is required for an
instruction, it is fetched by sending its address to the memory and
initiating a Read operation.

• UPDATE OR INCREMENT PC TO CONTINUE EXECUTION

-----the contents of the PC are incremented so that the PC points to the
next instruction to be executed.
-----Thus, as soon as the execution of the current instruction is
completed, the processor is ready to fetch a new instruction
 Sequence of actions
(details later in INSTRUCTION CYCLE)
•(PC) (MAR)( the contents of PC transferred to
MAR)

•(MAR) (Address bus) Select a particular memory

location

•Issues RD control signals

•Reads instruction present in memory and loaded into

MDR

•Will be placed in IR (Contents transferred from MDR to

IR)
•Instruction present in IR will be decoded by
which processor understand what operation it has
to perform

•Increments the contents of PC by 1, so that it

points to the next instruction address

•If data required for operation is available in

register, it performs the operation

•If data is present in memory following sequence

is performed
•Address of the data MAR

•MAR Address bus select memory

location where is issued RD signal

•Reads data via data bus MDR

•From MDR data can be directly routed to ALU or it

can be placed in register and then operation can be
performed

•Results of the operation can be directed towards

output device, memory or register

•Normal execution preempted (interrupt)

HANDLING SPECIAL CONDITIONS (Interrupts)
• An interrupt is a request from I/O device for
service by processor
• Processor provides requested service by
executing interrupt service routine (ISR)
• Contents of PC, general registers, and some
control information are stored in memory .
• When ISR completed, processor restored, so
that interrupted program may continue
COMMUNICATION B/W CPU AND DEVICE
• The processor can service these devices in one of the two
ways.
• One way is to use the polling routine, and the other way is
to use an interrupt.
 Polling enables the processor software to check each of the
input and output devices frequently. During this check, the
processor tests to see if any devices need servicing or not.
 Interrupt method provides an external asynchronous input
that informs the processor that it should complete
whatever instruction that is currently being executed and
fetch a new routine that will service the requesting device.
 EXAMPLE
• A typical instruction to read contents from main memory into register.
I: Load R2, LOC

STEPS OF EXECUTION
1. the instruction is fetched from the memory into the processor.  I
2. Next, the operation to be performed is determined by the control unit. 
LOAD
3. The operand at LOC is then fetched from the memory into the processor. 
VALUE/DATA STORED AT LOC
4. Finally, the operand is stored in register R2.

• After completing the desired operations, the results are in processor registers.
They can be transferred to the memory using instructions such as
Store R4, LOC
--This instruction copies the operand in register R4 to memory location LOC. The
original contents of location LOC are overwritten, but those of R4 are
preserved.
NOTE: The data transfer b/w main memory and processor(registers) is done by
generating control signals– RD control signal, WR control signal by The
processor-memory interface
 BUS
• A bus is a common pathway through which
information flows from one computer
component to another.
• It is a group of wires or lines that serves as a
connecting path for several devices.
• When a word is transferred over a bus, all bits
are transferred in parallel ie 1 bit per line.
Functions of Buses in Computers
• 1. Data sharing - All types of buses found in a
computer transfer data between the computer
peripherals connected to it.
• 2. Addressing - A bus has address lines, which match
those of the processor. This allows data to be sent to or
from specific memory locations.
• 3. Power - A bus supplies power to various peripherals
connected to it.
• 4. Timing - The bus provides a system clock signal to
synchronize the peripherals attached to it with the rest
of the system.
The CPU and memory are normally connected
by three groups of connections, each called a
bus: data bus, address bus and control bus
•Address bus : unidirectional : group of wires which carries
address information bits form processor to peripherals
(16,20,24 or more parallel signal lines)
•23 = 8 i.e. 3 address line is required to select 8 location

•In general 2x = n where x number of address lines (address

bit) and n is number of location
•Databus: bidirectional : group of wires which carries data
information bit form processor to peripherals and vice –
versa
•Controlbus: bidirectional: group of wires which carries
control signals form processor to peripherals and vice –
versa
Synchronous and Asynchronous Buses
• In a synchronous bus, bus operations are
synchronized with reference to a clock signal.
The bus clock is generally derived from the
computer system clock.
• An asynchronous bus has no system clock.
Handshaking is done to properly conduct the
transmission of data between the sender and
the receiver.
 Different bus Structures

Single bus
• All units are connected to it.
• Only one transfer at a time
• Low cost
• Flexibility in attaching to different peripherals
Multiple buses
• More than one transfer at same time(concurrency)
• More cost, less time
• Eg: In two – bus structure : One bus can be used to fetch
instruction other can be used to fetch data, required for
execution.
MULTIPLE BUS STRUCTURE
Bus Terminologies
• Computers have two major types of buses:
1. System bus:- This is the bus that connects the CPU
to the main memory on the motherboard. The system
bus is also called the front-side bus, memory bus, local
bus, or host bus.
2. A number of I/O Buses, (I/O is an acronym for
input/output), connecting various peripheral devices to
the CPU. These devices connect to the system bus via a
‘bridge’ implemented in the processors' chipset. Other
names for the I/O bus include “expansion bus",
"external bus” or “host bus”.
•
 Buffer registers
Need?
Different components work at different speeds like,
processor and memory operate at electronic speeds
but externals devices are relatively slow.
BUFFER REGISTERS
• are used to hold information during transfer to smooth
out the timing differences
• prevent processor from being locked by a slow I/O
device
• allow processor to rapidly switch between devices
Eg: printing process- processor transfer all data to be
printed buffer, then printer continues printing from
buffer without intervention of bus and processor.
 Instructions
Instruction:
A computer must have instructions capable of performing four types of
operations:
• Data transfers between the memory and the processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers

Instruction sets are differentiated by the following:

• Number of bits per instruction.
• Stack-based or register-based.
• Number of explicit operands per instruction.
• Operand location.
• Types of operations.
• Type and size of operands.
In designing an instruction set, consideration is
given to:
• Instruction length. – Whether short, long, or
variable.
• Number of operands.
• Number of addressable registers.
• Memory organization. – Whether byte- or word
addressable.
• Addressing modes. – Choose any or all: direct,
indirect or indexed.
 INSTRUCTION FORMAT
• A instruction in computer comprises of groups called
fields. (every thing is in 0 and 1 )
• so each field has different significance on the basis of
which a CPU decide what so perform.
The most common fields are:
1) Operation field which specifies the operation to be
performed like addition.
2) Address field which contain the location of operand,
i.e., register or memory location.
3) Mode field which specifies how operand is to be
founded.
TYPES
 Basic instruction types
On the basis of no. of addresses needed to perform an operation.
1) Three address instructions–
Syntax: Operation destination , source 1, source 2

Add C, A ,B // C=A+B
// store result in C

• A, B-source operands
• C-destination operands
• Advantage: Single instruction can perform the complete operation
• Disadvantage : Instruction code will be too large to fit in one word location in memory

2) Two address instructions-

Syntax : Operation destination , source

To perform above operation (ADD A,B,C) using 2 address format, we need 2 instructions

• MOVE C, B // First move B value in C

• ADD C, A // C<- C+A , which is equivalent to C=A+B of 3 address format
// store result in C

 Disadvantage: Single instruction is not sufficient to perform the entire operation

3) One address instructions –
• Syntax- Operation source/destination
• In this type either a source or destination operand is mentioned
in the instruction
• Other operand is implied to be a processor register called
Accumulator
Add A
• Add contents of A to accumulator & store sum back to accumulator.
• Eg: ADD E (general)
• Load D; ACC [memlocation _D]
• ADD E; ACC (ACC) +(E)
• STORE F; memlocation_ F (ACC )

4) Zero address instructions

• Location of all operands are defined implicitly

• Instruction store operands in a structure called push down stack.

• A instruction is of various length depending upon the number of
addresses it contain.
• Generally CPU organization are of three types on the basis of
number of address fields:
 Single Accumulator organization (1 address instruction)
 General register organization (3,2 address instruction)
 Stack organization (0 address instruction)
• In first organization operation is done involving a special register
called accumulator.
• In second on multiple registers are used for the computation
purpose.
• In third organization the work on stack basis operation due to which
it does not contain any address field.
• It is not necessary that only a single organization is is applied a
blend of various organization is mostly what we see generally.
 notations
1) Register transfer notations(RTN)
• Possible locations that may be involved in data transfers are
memory locations, processor registers, or registers in the I/O
subsystem
• Predefined names for the processor registers may be R0 or R5.
• Registers in the I/O subsystem may be identified by names such as
DATAIN or OUTSTATUS
Example expression: R3<–[R1]+[R2]
• the operation that adds the contents of registers R2 and R3, and
places their sum into register R4
• contents of any location are denoted by placing square brackets
around its name
• Right hand side of RTN-denotes a value.
• Left hand side of RTN-name of a location.
2) Assembly language notations(ALN)
• RTN is easy to understand and but cannot be used to represent
machine instructions
• Mnemonics can be converted to machine language, which processor
understands using assembler

Load R2, LOC

// transfer content of LOC into R2
• Add R3, R2, R1
• Adding contents of R1, R2 & place sum in R3.

//read micro-operation and their corresponding mnemonics

EG: the operation Load may be written as LD,
while the operation Store, which transfers a word from a processor
register to the memory, may be written as STR or ST
 Basic Instruction Cycle
• Basic computer operation cycle
– Fetch the instruction from memory into a control
register (PC)
– Decode the instruction
– Locate the operands used by the instruction
– Fetch operands from memory (if necessary)
– Execute the operation in processor registers
– Store the results in the proper place
– Go back to step 1 to fetch the next instruction
 Instruction execution & sequencing
• The processor control circuits use information in PC to fetch &
execute instructions one at a time (generally in order of increasing
address).
• This is called straight line sequencing.

• Executing an instruction-2 phase procedures.

1st phase–“instruction fetch”-instruction is fetched from memory
location whose address is in PC.
This instruction is placed in instruction register in processor
2nd phase-“instruction execute”-instruction in IR is examined to
determine which operation to be performed. This involves a small
number of steps such as fetching operands from the memory or
from processor registers, performing an arithmetic or logic
operation, and storing the result in the destination location.
• At some point during this two-phase procedure, the contents of the
PC are advanced to point to the next instruction.
INSTRUCTION EXECUTION & STRIAGHT LINE
SEQUENCING
 UPDATING PC VALUE
• Generally 2 types of instructions are encountered during execution– normal or simple
instruction and branch instruction

Branch instructions/ Branching:-

 Branch instruction are those which changes the normal sequence of execution.
 This type of instruction loads a new address into the program counter, when branch (loop)
condition is satisfied.
 As a result, the processor fetches and executes the instruction at this new address, called the
branch target
 If the condition is not satisfied, the PC is incremented in the normal way, and the next
instruction in sequential address order is fetched and executed.
 Sequence can be changed either conditionally or unconditionally.
 Accordingly we have conditional branch instructions and unconditional branch instruction.
 Conditional branch instruction changes the sequence only when certain conditions are met.
 Unconditional branch instruction changes the sequence of execution irrespective of condition
of the results.
 Eg: Adding N nos. // read
Branching
Condition codes
• CONDITIONAL CODE FLAGS: The processor keeps track of
information about the results of various operations for use by
subsequent conditional branch instructions.
• These flags are grouped together in a special processor register
called “condition code register” or “status register”
• Individual condition code flags-1 or 0.
• 4 commonly used flags.
• 1) N (negative)-set to 1 if result is –ve or else 0.
• 2) Z (zero)-set to 1 if result is 0, or else 0 .
• 3) V (overflow)-set to 1if arithmetic overflow occurs or else 0.
overflow occurs when the result of an arithmetic operation is
outside the range of values that can be represented by the number
of bits available for the operands
• 4) C(carry)-set to 1 if carry out results from operation or else 0
 Memory Locations and Addresses
• The memory consists of many millions of storage cells, each of
which can store a bit of information having the value 0 or 1.
• Data is transferred to and from memory in groups of bits called
words. A word can be a group of 8 bits, 16 bits, 32 bits or 64 bits
(and growing).

• If the word is 8 bits, it is referred to as a byte. The term “byte” is so

common in computer science that sometimes a 16-bit word is
referred to as a 2-byte word, or a 32-bit word is referred to as a 4-
byte word.

• Modern computers have word lengths that typically range from 16

to 64 bits.
• Accessing the memory to store or retrieve a single item of
information, either a word or a byte, requires distinct
names for each location, called an address.
• If address size is k bit , it means-- the memory can have up
to 2^k addressable locations(0 to 2^k − 1). The 2^k
addresses constitute the address space of the computer.
• For example, a 24-bit address generates an address space
of 2^24 (16,777,216) locations.
Memory addresses are defined using unsigned
binary integers.
 Byte Addressability
• 3 basic information quantities: bit, byte, and
word.
• It is impractical to assign distinct addresses to
individual bit locations in the memory.
• The most practical assignment is to have
successive addresses refer to successive byte
locations in the memory.
• Thus for a byte addressable memory, if the word
length of the machine is 32 bits, successive words
are located at addresses 0, 4, 8,..., with each
word consisting of four bytes.
 Assigning byte addresses
2 ways:-
1. big-endian assignment
---used when lower byte addresses are used for the more significant
bytes (the leftmost bytes) of the word.
2. little-endian assignment
--- the lower byte addresses are used for the less significant bytes (the
rightmost bytes) of the word.
The words “more significant” and “less significant” are used in relation
to the weights (powers of 2) assigned to bits when the word
represents a number.
// more significant higher power of 2
• In addition to specifying the address ordering of bytes within a
word, it is also necessary to specify the labeling of bits within a byte
or a word.
• The same ordering is also used for labeling bits within a byte, that
is, b7, b6,..., b0, from left to right.
 Word Alignment
• In the case of a 32-bit word length, natural word boundaries occur
at addresses 0, 4, 8…
aligned addresses
• We say that the word locations have aligned addresses if they begin
at a byte address that is a multiple of the number of bytes in a
word.
• aligned addresses makes accessing of memory operands more
efficient. (details in ch8)
• Eg: , if the word length is 16 (2 bytes), aligned words begin at byte
addresses 0, 2, 4,...,
and for a word length of 64 (23 bytes), aligned words begin at byte
addresses 0, 8, 16,....

unaligned addresses:-words can begin at an arbitrary byte address

Accessing Numbers and Characters
• A number usually occupies one word, and can
be accessed in the memory by specifying its
word address.
• Similarly, individual characters can be
accessed by their byte address.
 addressing modes
• refer to the different ways in which the memory locations of
instruction operands can be specified
// note: In assembly language, a variable is represented by
allocating a register or a memory location to hold its value
Different modes are:
 1) Immediate Addressing
• Operand is given explicitly in the instruction
• Operand = Value
• e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
Eg: Add R4, R6, 200immediate
Or Add R4, R6, #200 (ie. R4=R6+200)
# indicate immediate
 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space
 Direct Addressing Diagram
Instruction
Opcode Address A
Memory

Operand
1) Absolute mode
the address of the memory location(Absolute mode) where
the operand is located.
eg: A declaration such as Integer NUM1, NUM2, SUM;
In HLL , it will cause the compiler to allocate a memory
location to each of the variable.
EA= Memory_LOC
Whenever they are referenced later in the program, the
compiler can generate assembly-language instructions that
use the Absolute mode to access these variables.
Load R2, NUM1
2) Register mode
• Operand is held in register named in address field
• EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
– Requires good assembly programming or compiler writing

• Used for Implementation of Variables

• an operand is accessed by specifying the name of the register
eg: The instruction Add R4, R2, R3 uses the Register mode for all three
operands
 INDIRECT ADDRESSING MODES
When address is not given directly

Indirect mode—The effective address of the operand is the

contents of a register that is specified in the instruction.
• EA = [A]
– Look in A, find address (A) and look there for operand
• e.g. ADD (A)
– Add contents of cell pointed to by contents of A to accumulator

---Used when program requires capability for modifying the

address of the memory operand during each pass through
the loop eg: for implementing pointers holding address
---A good way to provide this capability is to use a processor
register to hold the address of the operand.
---
 Indirect Addressing Diagram
Instruction
Opcode Address A
Memory

Pointer to operand

Operand
 1) Register Indirect Addressing
• C.f. indirect addressing
• EA = [R]
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing
Register Indirect Addressing Diagram
Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand

 Eg:

• To execute the Load instruction in the processor

uses the value B, which is in register R5, as the
effective address of the operand.
• register R5 serves as a pointer to load an
operand from the memory into register R2.
• Indirect addressing through a memory location
is also possible, but it is found only in CISC-style
processors.
 Eg: addition of n numbers in a list
• R4: act as pointer, or reference to calculate address of next
number (similar to ptr++)
• R2: tells no. of numbers left for addition
2) Index mode—The effective address of the operand is
generated by adding a constant value to the contents of a
register.
--useful in dealing with lists and arrays
--refer register used in this mode as the index register.
Eg: X(Ri)
X denotes a constant signed integer value contained in the
instruction
EA = X + [Ri]
When the instruction is translated into machine code, the
constant X is given as a part of the instruction and is
restricted to fewer bits than the word
Indexed Addressing Diagram
Instruction
Opcode Register R Constant Value
Memory

Registers

Pointer to Operand + Operand

• two ways of using the Index mode
Variations in index mode
• For example, a second register Rj may be used
to contain the offset X, in which case we can
write the Index mode as
(Ri,Rj)
• The effective address is the sum of the
contents of registers Ri and Rj
Note: basic Index mode X(Ri)
If X=0, This has the same effect as the Absolute
mode
 3) Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = X + (PC)
• i.e. get operand from X bytes away from
current location pointed to by PC
• c.f locality of reference & cache usage
 3) Additional Addressing Modes
5) Autoincrement mode— to calculate The effective address
of the next operand the contents of this register are
automatically incremented to point to the next operand in
memory.
Notation: (Ri)+
6) Autodecrement mode—The contents of a register specified
in the instruction are first automatically decremented and
are then used as the effective address of the operand.
−(Ri)
Eg: Move (SP), NEWITEM
to push a new item on the stack, we can use just one
instruction
Move −(SP), NEWITEM
7) Relative Mode: The effective address is determined by
the Index mode using the program counter in place of
the general-purpose register Ri.
---the Index mode by using general-purpose processor
registers.
---Some computers have a version of this mode in which
the program counter, PC, is used instead of a general-
purpose register.
----Then, X(PC) can be used to address a memory location
--The effective address is determined by the Index mode
using the program counter in place of the general-
purpose register Ri.
 Instruction Sets
A microprocessor is a processing unit on a single chip. It is an integrated
circuit which performs the core functions of a computer CPU.
Characterstics of a micro processor:
• Instruction Set –
Set of complete instructions that the microprocessor executes .
• Word Length –
The number of bits processed in a single instruction is called word length
or word size. Greater the word size, larger the processing power of the
CPU.
• System Clock Speed –
Clock speed determines how fast a single instruction can be executed in a
processor.
• Classification of Microprocessors:
Besides the classification based on the word length, the classification is
also based on the architecture i.e. Instruction Set of the microprocessor.
These are categorised into RISC and CISC.
• two fundamentally different approaches in
the design of instruction sets for modern
computers:

1) Reduced Instruction Set Computers (RISC).

2) Complex Instruction Set Architecture (CISC)
 Characteristics of RISC Vs CISC processors
No RISC
1 Simple instructions taking one
cycle
2 Instructions are executed by
hardwired control unit
3 Few instructions
4 Fixed format instructions
5 Few addressing mode, and most
instructions have register to
register addressing mode
6 Multiple register set
7 Highly pipelined
CISC
Complex instructions taking
multiple cycles
Instructions are executed by
microprogramed control unit
Many instructions
Variable format instructions
Many addressing modes
Single register set
Not pipelined or less pipelined