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Generation of PWM Schemes For Power Electronic Converters: Abstract - Advanced Digital Signal Processors (DSP) Have
Generation of PWM Schemes For Power Electronic Converters: Abstract - Advanced Digital Signal Processors (DSP) Have
Abstract-- Advanced Digital Signal Processors (DSP) have complex switching PWM for successful operation for open loop as
the capability to generate complex Pulse Width Modulation well as closed loop. Sin-triangle PWM and Space Vector PWM
(PWM) signals for power electronics converter applications. technique is widely used for controlling complex inverter
Floating point processors like DS-1104, FPGA Spartan 6 are topologies [10-11]. Again, for closed loop control to implement
popular because of their capability of solving complex complex algorithm like sliding mode control, adaptive hysteresis
mathematics and MATLAB integration feature. But owing to control, model predictive control, variable duty and constant
larger space and higher cost requirement these processors frequency operation is required where floating point DS-1104 or
can’t be used as embedded processor. In this article low cost Spartan 6 FPGA is used for easy prototype demonstration. DS-1104
floating point DSP processor TMS320F28379D is tested for is also having MATLAB integration feature thus creating digital
generating complex PWM signals. The result shows control very easy. But for practical implementation this solution
generation of PWM is easier and can be adopted for can’t be realized for embedded system design and prototype making
designing power electronics converters. with increased cost and size.
This paper discusses the use of low cost Delfino TMS320F28379D
Index Terms—Pulse Width Modulation (PWM), DSP, Duty Ratio
development board-a dual CPU floating point DSP processor [11],
(D).
for generating complex PWM signal commonly used in power
I. INTRODUCTION electronics converters.
Pulse Width Modulation (PWM) is a control technique used in II. GENERATION OF PWM SCHEMES
power electronics converter to regulate power supplied from power
source to load. Duty cycle is the output variable of PWM which In an embedded application [13], the target processor produces
carries information and encode the control function of converter [1- pulses from a Time Based Clock (TBCLK). The Time Based
2]. In many applications where constant energy is to be supplied to Clock can run at the CPU speed or a fraction of it. Pulses
load and output voltage is constant like switched mode power produced by the TBCLK are counted as they occur forming a
converter constant duty cycle fixed frequency PWM signal is staircase signal whose count value at any time is monitored by a
required for control. This PWM signal generation can be done in Time Based Counter (TBCTR). When the TBCTR reaches a
analog domain or in digital domain. In analog domain Op-Amp preset value named the Time Base Period (TBPRD), the counter
circuits are extensively used for generating PWM from carrier and resets itself to 0 and the staircase signal repeats. PWM signals are
modulating signals [2]. But due to component aging, temperature generated based when the TBCTR equals a Compare (CMP)
drift and new hardware design for slight variation is restricted the value as shown in Fig.1.
use of analog domain for generating PWM signals. Whereas in
digital control generating PWM signal is quite easy and writing
Up/Down Count Mode
DC converter fixed frequency fixed duty cycle PWM is mostly used ON Time OFF Time ON Time OFF Time
counter multiplied by each tick time period is total PWM time example in the Fig. 4 the triangle wave is compared with two
period. It is also called carrier time period. reference value i.e. 0.25 as lower and 0.75 as upper for a triangle
Similarly for up count and down count the PWM time period is, peak at 1. Thus two PWM signal is generated as the same time
(TBPRD+1)*TBCLK. period as triangle time period (f1, f2). After XOR operation of f1
The resolution, of a PWM generator is equal to the number of and f2 i.e. f = f1 ⊕ f 2 the output PWM signal is double than
Time Based n pulses present in the PWM period expressed as a
carrier triangle signal. Therefore, fsw=2ftriangle is possible. For this
number of bits. Resolution expressed as a number of bits:
TPWM example the duty ratio is 0.5. The same procedure can be
followed to generate dead time intelligently.
n=log 2TBCLK , Number of Time Base pulses per PWM period
TPWM
Reference Signal
is . For example, a 20 kHz PWM signal is to be
Triangle Signal
TBCLK
generated using an 80MHz CPU. The Time Based Clock
(TBCLK) is set to 1/80Mhz and the resolution is calculated as:
Tpwm/TBCLK=(1/20k)/(1/80M) and n=log2(4000) =11.96 =12 F(t)
bits.
The High Resolution Timer option, based on the availability on
hardware, decreases the TBCLK to a value of 150e-12 seconds.
This is particularly useful if your application requires a high
PWM frequency
(NOTE: 250 kHz and greater is considered to be a high PWM
frequency). 2TS
This concept is utilized to generate PWM for buck, boost or
synchronous buck, boost converter as shown in Fig. 2 and Fig. 3.
d(t)
Reference Signal
Sawtooth Signal
L
DIODE D1
F(t)
Vs
MOSFET C R
S1
TON Time(t)
TS
Fig. 4. Generating fixed duty (d) double switching frequency PWM signal
DIODE D1
form half carrier frequency.
L
d(t) C R
Vs The main interrupt loop coding in DSP for XOR time interrupt
MOSFET
TON Time(t) S1 operation is
TS
{
if
Fig. 2 Fixed Duty (d) PWM for Buck and Boost Converter.
((((int)(( _out_1 * 3.0517578125e-
005)<0.25))^((int)(((CGDOUBLE) _out_56 )>0.75))))
Reference Signal
Sawtooth Signal
L {GPBSET = 0x4L;}
F(t)
S2
Vs S1
C R Else
{GPBCLEAR = 0x4L;};
_delayOutBuf57 = t80;
_delayOutBuf2 = t25;
Dead
L if ( t12)
Time
S1
Vs S2
C R _sampBuf21 = t22;
d(t)
if ( t67)
_sampBuf76 = t77;
TON TS Time(t) End Of Sample Count = TIMER2TIM;
}
Fig. 3. PWM signal for synchronous buck and boost converter. Hardware dead time generation is not flexible but in DSP
software approach changing in programming can effectively
introduce dead time. Other complex algorithm for inverter control
Generally PWM time period is the same as the carrier time as discussed earlier can be easily done in TMS320F28379D
period. Thus generating high frequency PWM requires same high development board. EPWM channels can be effectively utilized
frequency as carrier. fsw=fcarrier. Sometime it is difficult in practical for high resolution PWM generation. Simple digital input/output
circuit to use high carrier frequency. It is possible to increase can be programmed for PWM with limited switching frequency
switching frequency without increasing carrier frequency. For typically 2-5 kHz in this board.
Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India
Modulating Sin for one Leg Carrier Wave Modulating Sin for other Leg
0.8
0.6
0.4
0.2
Switching Pulse for Top Switch of one Leg Switching Pulse for Top Switch of other Leg
0.8
0.6
0.4
0.2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
(a)
3rd Harmonics Injected Modulating Sin for One Leg Carrier Wave 3rd Harmonics Injected Modulating Sin for Other Leg
0.8
0.6
0.4
0.2
Switching Pulse for Top Switch of One Leg Switching Pulse for Top Switch of One Leg
0.8
0.6
0.4
0.2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time (s)
(b)
Sector
6
5
4
3
2
1
0
T0 Ti Ti1
8e-005
6e-005
4e-005
2e-005
0
Top Switch Pulse Phase A Top Switch Pulse Phase B Top Switch Pulse Phase C
1
0.8
0.6
0.4
0.2
0
0.025 0.03 0.035 0.04 0.045
Time (s)
(c)
Fig. 5. Inverter Switching Pulse Generation Scheme: (a) Sin-Triangle PWM (1KHz) Generation Scheme for Single phase inverter (b) Third harmonics
injected Sin-Triangle PWM (1KHz) for single phase inverter (c) Space vector PWM (10 KHz) for three phase inverter.
Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India
Plot Plot
1.2 1.2
1.1 1.1 Right click on the background
to pop back up a layer.
1.0 1.0
.9 .9
.8 .8
:out
.7 .7
.6 hase
.6
.5 .5
.4 .4
.3 .3
.2 .2
.1 .1
0 0
-.1 -.1
-.20 .0005 .001 .0015 .002 .0025 .003 .0035.004 .0045.005 .0055 .006 .0065.007 .0075.008 .0085 .009 .0095 .01 -.2
0 .0005.001 .0015.002 .0025 .003 .0035.004 .0045.005 .0055 .006 .0065.007 .0075.008 .0085 .009 .0095 .01
Time (sec) Time (sec)
Plot
1.2
1.1
1.0
.9
.8
.7
.6
.5
.4
.3
.2
.1
0
-.1
-.2
0 .001 .002 .003 .004 .005 .006 .007 .008 .009 .01 .011 .012 .013 .014 .015 .016 .017 .018 .019 .02
Time (sec)
Plot
1.2
1.1
1.0
.9
.8
.7
.6
.5
.4
.3
.2
.1
0
-.1
-.2
0 .001 .002 .003 .004 .005 .006 .007 .008 .009 .01 .011 .012 .013 .014 .015 .016 .017 .018 .019 .02
Time (sec)
(j) (k)
Fig. 6. (a) Fixed duty constant frequency PWM signal generation (simulated) (b) Fixed duty constant frequency PWM signal generation (practical) (c)
Triangular carrier frequency of 500 Hz (simulated) (d) Fixed duty 1Khz frequency PWM signal generation from half carrier frequency i.e. 500Hz. (e) Sin-
Triangle PWM generation (Simulated-M-0.8) (f) Sin-Triangle PWM of 1khz switching frequency (Practical-M-0.8)) (g) Space Vector PWM generation for
1kHz switching frequency (Simulated-M-0.8) (h) Space Vector PWM generation for 1kHz switching frequency (Practical-M-0.8). (i) Small increase in duty
ratio near zero crossing for space vector PWM (j) Duty ratio changes sinusoidally near zero crossing for Sin-Triangle PWM. (k) Sin-Triangle PWM of 1 kHz
switching frequency (practical-M-0.75).
Proceedings of the National Power Systems Conference (NPSC) - 2018, December 14-16, NIT Tiruchirappalli, India
REFERENCES
[1] Holmes, D. Grahame, and Thomas A. Lipo. Pulse width
modulation for power converters: principles and practice. Vol.
18. John Wiley & Sons, 2003.
[2] Holtz, Joachim. "Pulsewidth modulation for electronic power
conversion." Proceedings of the IEEE vol. 82, no.8, pp. 1194-
1214, 1994.
[3] K. Kim, Y. Jung and Y. Lim, "A New Hybrid Random PWM
Scheme," in IEEE Transactions on Power Electronics, vol. 24,
no. 1, pp. 192-200, Jan. 2009.