EEE109 (Matthews) Fall 2009

Midterm Exam Two Announcement

Exam Date: Monday, November 7, 2011.

The following topics have been listed as a study guide. It should not be assumed that all
topics to appear on the exam are explicitly described here. However, if you understand
each of these topics and the relevant background information, you should be ready for the
exam.

The exam will take place in the regularly scheduled room at the regular time. Students
are allowed one sheet of notes 8 12 × 11 inches, both sides, and handwritten.

Large-signal models for BJT and MOS devices – regions of operation

Two-Transistor Current Mirrors
• errors due to finite beta
• errors due to finite Early voltage (or nonzero lambda)
• output resistance and its implications for current mirrors
• output current equal to a multiple of the reference current
• output voltage range
• Role of current mirror in a differential amplifier
• Increasing output resistance with emitter (or source in MOS) degeneration
Differential Amplifiers, MOS and BJT – large signal behavior
• Bias conditions
• Input conditions to “steer” tail current all to one side
2VOV for MOS, about 4VT for BJT
Differential Amplifiers, MOS and BJT –small-signal behavior
• difference- and common-mode signals
• difference- and common-mode gain
• difference- and common-mode input resistances
• The half-circuit analysis technique
Input-referred offset voltage
• Apply the general principle
Find vOUT with vID = 0 , divide vOUT by the voltage gain
Find iOUT with vID = 0 , divide iOUT by the transconductance gain
• Offset mechanisms
∆Vth for MOSFET differential and transconductance amplifiers
∆RC for BJT differential amplifiers
∆I S for BJT transconductance amplifiers
Transconductance amplifiers
• voltage input, current output
• use of current mirrors