Question Paper Code : 12533

B.E. / B.TECH DEGREE EXAMINATION, APRIL / MAY 2018

Third Semester
Common to B.E.-Computer Science and Engineering
15CS303 – COMPUTER ORGANISATION AND ARCHITECTURE
(Regulations: Mepco – R2015)
ANSWER KEY

PART A

1. Purpose of MAR and MDR

MAR:
MAR are used to handle the data transfer between the main memory and the processor. The MAR holds the
address of the main memory to or from which data is to be transferred.
MDR:
MDR are used to handle the data transfer between the main memory and the processor. The MDR contains
the data to be written into or read from the addressed word of the main memory.

2. X=1010100 Y=1000011-Perform

a) X = 1010100

2's complement of Y = + 0111101

--------------
Sum = 10010001

Discard end carry

Answer: X - Y = 0010001

b) Y = 1000011

2's complement of X = + 0101100

---------------

Sum = 1101111

There is no end carry, Therefore the answer is Y-X = - (2's complement of 1101111) = -0010001

3. Register Transfer Sequence to read a word from memory

Move (R1), R2
The processor has to specify the address of the memory location where this information is stored and
request a Read operation. This applies whether the information to be fetched represents an instruction in a
program or an operand specified by an instruction.
4. Diff between hardwired and micro programmed control:

Hardwired:

It uses flags, decoder, logic  gates and other digital circuits.

Difficult to design, test and implement.
Faster mode of operation.

Micro programmed:

It uses sequence of micro-instruction

It generates a set of control signal on the basis of control line.
Easy to design, test and implement.

5. Pipeline speedup and efficiency

Speedup is a number that measures the relative performance of two systems processing the same problem.
The efficiency of n stages in a pipeline is defined as ratio of the actual speedup to the maximum speed.

6. Delayed Branching
Delayed branch allows one or more instructions following the branch to be executed in the
pipeline whether the branch is taken or not.

7. Number of bits used for address space=24

Number of words there in address space is 224 = 16x220 =16K words

8. Hit and miss rate

The fraction or percentage of accesses that result in a hit is called the hit rate. The fraction or percentage of
accesses that result in a miss is called the miss rate.

9. Isolated and memory mapped I/O

Isolated I/O uses separate memory space. Limited instructions can be used. Those are IN, OUT, INS,
OUTS. Uses complex internal logic. Memory mapped I/O: Memory mapped I/O uses memory from the
main memory. Memory mapped I/O devices are treated as memory locations on the memory map.

10. Synchronous and Asynchronous bus.

A synchronous bus transmits bits of data by using a shared clock signal to synchronize the timing of both
the sender and the receiver. That's why it's called “synchronous". An asynchronous bus, on the other
hand, does not require a common clock signal to be shared between sender and receiver in order to work.

PART B

11. a) i. carry save addition of summands:

Multiplication requires the addition of several summands. A technique called carry-save addition (CSA)
can be used to speed up the process. Instead of letting the carries ripple along the rows, they can be “saved”
and introduced into the next row, at the correct weighted positions.

Explanation: (2 marks)

This frees up an input to each of three full adders in the first row. These inputs can be used to introduce the
third summand bits m2q2, m1q2, and m0q2. Now, two inputs of each of three full adders in the second row
are fed by the sum and carry outputs from the first row. The third input is used to introduce the bits m2q3,
m1q3, and m0q3 of the fourth summand. The high-order bits m3q2 and m3q3 of the third and fourth
summands are introduced into the remaining free full-adder inputs at the left end in the second and third
 rows. The saved carry bits and the sum bits from the second row are now added in the third row, which is a
ripple-carry adder, to produce the final product bits.

Schematic representation of carry save addition (2 marks)

Problem (2 marks)

A) M=101011 Q=101101
ANS: 11110001111
B) M=110101 Q=100011
ANS: 11100110111

11. a.(ii) Instructions:

The physical and logical structure of computers is normally described in reference manuals
provided with the system. Such manuals explain the internal construction of the CPU, including the
processor registers available and their logical capabilities.
ADD R1, R2, R3 To denote the operation R1 ← R2 + R3. The number of address fields in the
instruction can be reduced from three to two if the destination register is the same as one of the source
registers. Thus the instruction ADD R1, R2 Would denote the operation R1 ← R1 + R2. Only register
addresses for R1 and R2 need be specified in this instruction.

THREE-ADDRESS INSTRUCTIONS Computers with three-address instruction formats can

use each address field to specify either a processor register or a memory operand. The program in assembly
language that evaluates X = (A + B) ∗ (C + D) is shown below, together with comments that explain the
register transfer operation of each instruction. ADD R1, A, B R1 ← M [A] + M [B] ADD R2, C, D R2 ←
M [C] + M [D] MUL X, R1, R2 M [X] ← R1 ∗ R2.

TWO-ADDRESS INSTRUCTIONS Two address instructions are the most common in

commercial computers. Here again each address field can specify either a processor register or a memory
word. The program to evaluate X = (A + B) ∗ (C + D) is as follows: MOV R1, A R1 ← M [A] ADD R1, B
R1 ← R1 + M [B] MOV R2, C R2 ← M [C]

ONE-ADDRESS INSTRUCTIONS One-address instructions use an implied accumulator (AC)

register for all data manipulation. For multiplication and division there is a need for a second register.
However, here we will neglect the second and assume that the AC contains the result of tall operations. The
program to evaluate X = (A + B) ∗ (C + D) is LOAD A AC ← M [A] ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC LOAD C AC ← M [C]

11.b.(i) A=110011
B=010101

Definition (2 marks)
A technique called bit-pair recoding of the multiplier results in using at most one summand for
each pair of bits in the multiplier. It is derived directly from the Booth algorithm.

Explanation (1 mark)

The pair (+1 −1) is equivalent to the pair (0 +1). That is, instead of adding −1 times the
multiplicand M at shift position i to +1 ×M at position i + 1, the same result is obtained by adding
+1 ×M at position i.
 Problem: (5 marks)

Bit pair recoding for the multiplier is:

Sign bit extension is:
So,
Implied 0 to right of LSB
So it becomes,

ANS: 10000101111

11 b. (ii) Addressing Modes.

The different ways for specifying the locations of instruction operands are known as addressing modes. (1
Mark)
Types (2 Marks)
Register mode
Absolute Mode
Indirect mode
Index mode
Auto decrement mode
Auto increment mode
Relative Mode

Explanation-5 marks
 Register Indirect: —The effective address of the operand is the contents of a register.
 Indirection and pointers:
Register, absolute, and immediate modes directly provide the operand or address.
Other modes provide information from which the effective address of operand is derived
For program that adds numbers in a list, use register as pointer to next number.
Load R2, (R5)

 Indexing:
Consider index mode in: Load R2, X(R5) Effective address is given by [R5] + X
assume operand address is 1020, 4 words (20 bytes) from start of array at 1000 Can put
start address in R5 and use X=20 Alternatively, put offset in R5 and use X=1000

 Auto increment mode: effective address given by register contents; after accessing
operand, register contents incremented to point to next Useful for adjusting pointers in
loop body:
Add SUM, (Ri)+
MoveByte (Rj)+, Rk

Increment by 4 for words, and by 1 for bytes

12.a) i. Sequence of actions needed to fetch and execute instructions: store R6, X (R8) ------4 marks

Stores the contents of register R6 into memory location X + [R8]. It can be implemented as
follows:
1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read registers R6 and R8.
3. Compute the effective address X + [R8].
4. Store the contents of register R6 into memory location X + [R8].
5. No action.

Load R5, X(R7)-----4 marks

Load the contents of memory location X+ (R7) into register R5. It can be implemented as follows:
1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read the contents of source register R7
3. Compute the effective address X + [R7].
4. No Action
5. Load the contents of memory location X+ (R7) into register R5

12. a) ii. Hardware components:

 ALU
 Datapath

ALU: Diagram with explanation: 2 marks

Data path: Diagram with explanation: 2 marks

12.b.(i)

PC_UPDATE:

12. b) ii. Approaches:

Hardwired Control Mechanism:

Generation of control signals depends on (2 marks)
Contents of the step counter
Contents of the instruction register
The result of a computation or a comparison operation
External input signals, such as interrupt requests
Diagram: 3 marks
Explanation: 3 marks
12. b) ii) R4=1000
R6=7500
R7=2500
Instruction is: SUBTRACT R6, R4, R7

Detailed explanation with diagram: 4 marks

Solution with explanation: 4 marks

RA= 1000
RB= 2500
RZ= 1500
RY= Since it is a subtraction instruction there is no need to access memory contents.
R6= 1500

13.a.) Hazard: Definition and types->2 marks

Operand Forwarding
Pipeline stalls due to data dependencies can be alleviated through the use of operand forwarding.

Operand Forwarding-------------------------------------------------6 Marks

Consider the pair of instructions discussed above, where the pipeline is stalled for three cycles to enable the
Subtract instruction to use the new value in register R2. The desired value is actually available at the end of
cycle 3, when the ALU completes the operation for the Add instruction. This value is loaded into register
which is a part of interstage buffer B3.

Rather than stall the Subtract instruction, the hardware can forward the value from register RZ to where it
is needed in cycle 4, which is the ALU input. The arrow shows that the ALU result from cycle 3 is used as
an input to the ALU in cycle 4. Modification needed in the datapath of to make this forwarding possible.
A new multiplexer, MuxA, is inserted before input In A of the ALU, and the existing multiplexer MuxB is
expanded with another input. The multiplexers select either a value read from the register file in the normal
manner, or the value available in register RZ.

Forwarding can also be extended to a result in register RY. This would handle a data dependency such as
the one involving register R2 in the following sequence of instructions:
Add R2, R3, #100
Or R4, R5, R6
Subtract R9, R2, #30
When the Subtract instruction is in the Compute stage of the pipeline, the Or instruction is in the Memory
stage (where no operation is performed), and the Add instruction is in the Write stage. The new value of
register R2 generated by the Add instruction is now in register RY. Forwarding this value from register RY
to ALU input InA makes it possible

When the Subtract instruction is in the Compute stage of the pipeline, the Or instruction is in the
Memory stage (where no operation is performed), and the Add instruction is in the Write stage.
The new value of register R2 generated by the Add instruction is now in register RY. Forwarding
this value from register RY to ALU input InA makes it possible
13.b Pipelining in CISC:

For pipelining in CISC processors, complications arise due to instructions that are variable in size,
have multiple memory operands and complex addressing modes, and use condition codes.
Instructions that occupy more than one word may take several cycles to fetch. Furthermore,
variability in instruction size and format complicates both decoding and operand access, as well as
management of the dispatch queue in a superscalar processor.

The availability of more complex addressing modes such as Autoincrement or Autodecrement

introduces side effects when executing instructions. Aside effect occurs when a location other than
that of the destination operand is also affected.

Examples: ----- 2 marks

Instruction Move R5, (R8)+ has a side effect. Not only is the destination register R5 affected, but
source register R8 is also affected by the autoincrement operation.

.Compare R7, R8 Branch>0 TARGET the result of the Compare instruction affects the condition
code flags as a side effect. The Branch instruction, in turn, implicitly depends on this side effect.

Move (R2), (R3)

Move (R4), R5

The first Move instruction requires two operand accesses to the memory, while the second Move
instruction requires only one. Executing these instructions in a pipeline requires additional
hardware to stall the second Move instruction so that the first Move instruction can complete its
two operand accesses to the memory.

Pipelining in Cold Fire Processors---- 3 marks

Pipelining in Intel Processors-----------3 marksAdd R3, R2, R1

14.a) i.DMA Controllers

Definition-(2 marks)
A special control unit is provided to manage the transfer, without continuous intervention by the processor.
This approach is called direct memory access, or DMA.
Typical registers in DMA controllers with explanation: (3 marks)

Use of DMA controllers in computer system –with explanation (3 marks)

 14.a.(ii) The cache is divided into 4 sets. Therefore, 4 bits are needed to identify the set number. Main
memory consists of 16384 blocks. The tag length is bits. Each block contains 256 words. Therefore, bits
are needed to specify the word.
Figure with explanation of direct and associative mapping: 5 marks

Total words in main memory=

To address

Main memory address=

TAG =

SET=

WORD =

14.b) i. Virtual memory:

Definition: --------------------------2 marks

If a program does not completely fit into the main memory, the parts of it not currently being executed are
stored on a secondary storage device, typically a magnetic disk. As these parts are needed for execution,
they must first be brought into the main memory, possibly replacing other parts that are already in the
memory. These actions are performed automatically by the operating system, using a scheme known as
virtual memory.

Virtual memory organization: ------------------2 marks

Virtual Memory Management Technique: --------------2 marks

Virtual memory organization along with Address translation -2 marks

14.b) ii. DRAM Chip:

Explanation: 3 marks
Static RAMs are fast, but their cells require several transistors. Less expensive and higher density
RAMs can be implemented with simpler cells. But, these simpler cells do not retain their state for
a long period, unless they are accessed frequently for Read or Write operations. Memories that use
such cells are called dynamic RAMs (DRAMs).

Information is stored in a dynamic memory cell in the form of a charge on a capacitor, but this
charge can be maintained for only tens of milliseconds. Since the cell is required to store
information for a much longer time, its contents must be periodically refreshed by restoring the
capacitor charge to its full value. This occurs when the contents of the cell are read or when new
information is written into it.

To store information in this cell, transistor T is turned on and an appropriate voltage is applied to
the bit line. This causes a known amount of charge to be stored in the capacitor. After the
transistor is turned off, the charge remains stored in the capacitor, but not for long. The capacitor
begins to discharge.

This is because the transistor continues to conduct a tiny amount of current, measured in
picoamperes, after it is turned off. Hence, the information stored in the cell can be retrieved
correctly only if it is read before the charge in the capacitor drops below some threshold value.

Single transistor dynamic cell: 2 marks

Internal organization: 3 marks

 15.a) A) HDMI:

Short for High Definition Multimedia Interface, HDMI is a connector and cable capable of

transmitting high-quality and high-bandwidth streams of audio and video between devices. The HDMI
technology is used with devices such as an HDTV, Projector, DVD player. The picture to the right is an
example of an HDMI cable.

The HDMI ports are found either on the video card or motherboard on the back of the computer. It
is important to note that not all computers and video cards have HDMI connects, and your computer may
only have a Display Port, DVI, or VGA connector. In the picture to the right is an example of some of these
connectors with an example of the HDMI connector.

B) PCI

Features: 2 marks

The PCI (Peripheral Component Interconnect) bus was developed as a low-cost, Processor-
independent bus. The peripheral components interconnect (PCI) bus is designed for multiprocessor
systems and high-performance peripherals, including audio and video systems and network adapters. It
is housed on the motherboard of a computer and used to connect I/O interfaces for a wide variety of
devices.

Working of PCI bus with diagram: 6 marks

Device Configuration:

PCI incorporates in each I/O device interface a small configuration ROM memory that stores information
about that device. The PCI initialization software reads these ROMs and determines whether the device is a
printer, a keyboard, an Ethernet interface, or a disk controller.

15.b) i) Interrupts:

Definition: 2 marks

The program enters a wait loop in which it repeatedly tests the device status. During this period, the
processor is not performing any useful computation. There are many situations where other tasks can be
performed while waiting for an I/O device to become ready. To allow this to happen, we can arrange for the
 I/O device to alert the processor when it becomes ready. It can do so by sending a hardware signal called an
interrupt request to the processor. Since the processor is no longer required to continuously poll the status
of I/O devices, it can use the waiting period to perform other useful tasks. Indeed, by using interrupts, such
waiting periods can ideally be eliminated.

Example with explanation: 2 marks

Enabling and Disabling Interrupts: with definition: 2 marks

Scenario: 2 marks

1. The device raises an interrupt request.

2. The processor interrupts the program currently being executed and saves the contents of the PC and PS
registers.
3. Interrupts are disabled by clearing the IE bit in the PS to 0.
4. The action requested by the interrupt is performed by the interrupt-service routine, during which time the
device is informed that its request has been recognized, and in response, it deactivates the interrupt-request
signal.

15.b.(ii) Programmed control IO:

Definition: 2 marks

A simple way of implementing this task is to write a program that performs all functions needed to realize
the desired action. This method is known as program-controlled I/O.

Connection for Keyboard, processor and display: with explanation (3 marks)

Registers in keyboard and display interfaces: with explanation: (3 marks)