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IOP PUBLISHING NANOTECHNOLOGY
Nanotechnology 22 (2011) 245303 (3pp) doi:10.1088/0957-4484/22/24/245303

Intrinsic top-down unmanufacturability

M J Kelly
Centre for Advanced Photonics and Electronics, Department of Engineering,
University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 0FA, UK

Received 8 February 2011, in final form 15 March 2011

Published 20 April 2011
Online at stacks.iop.org/Nano/22/245303

Abstract
Although small structures can be fabricated by deposition, lithography and etching, in some
cases their intrinsic variability precludes their use as elements in useful arrays. Manufacture is a
proper subset of fabrication. We show that structures with 3 nm design rules can be fabricated
but not manufactured in a top-down approach—they do not have the reproducibility to give a
satisfactory yield to a pre-ordained specification. It is also shown that the transition from
manufacturability to intrinsic unmanufacturability takes place at nearer 7 nm design rules.

Nanoscience continues to provide new insights and phenomena
based on the analysis of specific material properties
of nanoscale artefacts made by conventional fabrication
techniques as used in microelectronics. Many papers are
reported in the literature [1] on aspects of nano-electronics and
nano-optoelectronics giving details and results of experiments
that are performed in the hope of contributing to a post-silicon
CMOS era for computation and communication. This hope is
predicated on a subsequent triumph of technology that renders
what are one-off results initially into something that can be
achieved by a fabrication process which is capable of being
used in manufacture. Hundreds of papers are explicit and
thousands are implicit about wishing for future breakthroughs
to achieve low-cost, high-volume manufacturability [2]. Such
manufacturability implies that repeated fabrication of artefacts
is possible to produce electronic, optical, magnetic or other
properties with a high and highly reproducible yield within
a tight tolerance of a pre-specified performance. If this (top-
down) manufacturing process is to be based on the most
modern forms of deposition (including epitaxy), e-beam or
ultra-deep UV lithography and precision etching, the mainstay
of microelectronics and optoelectronics fabrication, then there
are strict limits described below for which one-off fabrication
is possible, but manufacture is not. Bottom up self-assembly
of molecular units is not considered here, although there is
a vanishing probability of generating a wide-area defect-free
(especially line-defect-free) arrays.
First we show that, even if an array of 3 nm diameter
vertical pillars on a 6 nm pitch can be fabricated, it
cannot be manufactured [3]. It is possible to define 3 nm
diameter openings in a resist material using electron-beam
lithography [4] and it is possible to fabricate features 5 nm
apart [5], both on a heroic rather than routine basis and not
yet together. The assertion is that the resulting array is not
able to be reproduced to give electronic or optical properties
that are within a narrow range of pre-specified values. The
proof comes in two stages, first considering (a) the intrinsic
variability of the cross section of the pillars and then (b) the
implications of this variability on the optical and electronic
properties. (a) There are two ways of making these pillars:
using a metal particle catalyst to grow the pillars or infilling
lithographically defined holes in a resist layer. The bottom
layer of the metal catalyst particle will ideally have N ∼ 80
atoms in its cross section, and will have variability in area
√
of at least N ∼ 9, because of the statistical variability
of small numbers of independent atoms in the last layer as
prepared. This variability is transferred to the area of each of
the growing pillars, giving them σarea = 12%. Similarly, the
top layer of the holes in the resist will also have a minimum
statistical spread of 12% in area as well, whether used to grow
the quantum pillar or the catalytic metal dot. This variation
will come from the statistics of small numbers when trying to
remove independent atoms from the top layer. (b) Whatever
the height of the pillar, the quantum confinement energy for
electrons has a contribution that is inversely proportional to
the cross-section area, and so the confinement energy will
have a standard deviation of at least 12%. Such a variation
means 25 meV in 200 meV for typical confinement energies
in III–V semiconductors, which is unacceptably broad for any
optical applications [6]. Any electronic transport between
nanopillars, if the intervening regions are filled in with a
quantum barrier material (e.g. AlAs surrounding GaAs pillars),
will be well into the disordered regime (i.e. no superlattice
subbands which are typically 20meV wide at this scale), and
so of little use [6]. In addition the variability of surface
state properties from one feature to another is an additional
complication. Finally, we note that quantum dots at 3 nm
diameter will have an even greater variability than the pillars

0957-4484/11/245303+03$33.00 1 © 2011 IOP Publishing Ltd Printed in the UK & the USA
Nanotechnology 22 (2011) 245303 M J Kelly

because of a lack of total control over the height of the pillars, (5) Many results in nanoscience can be shown to be
and so an extra variability from the quantum confinement intrinsically unmanufacturable in terms of ideas for
energy in the third dimension. In the case of quantum dots applications in electronic or optoelectronic components,
used as the catalyst for pillar growth, this simple analysis and so will remain as scientific curiosities.
accounts for the fact that the standard deviation by volume of (6) Arrays of quantum dots, single-electron tunnel junction
the quantum dots is not less than 15% once the feature size is transistors, split-gate transistors, carbon nanotubes, etc,
5 nm or less in any data acquired over the last 20 years. can always be used for their aggregate or averaged
Even if an alternative fabrication technique, other than properties, but not as elements in any form of pixellated
those described above, could result in a perfect 6 nm pitch array [11].
array of 3 nm quantum dots (such as some as yet unknown (7) Any precision optical metamaterials that rely on feature
method for perfectly crystallizing a perfect and single layer accuracy and precision at less than ∼5 nm will also be
of 2 functionalized quantum dot structures made in the gas unmanufacturable: the main structural features in these
phase and then subject to a strict mass selection), one would metamaterials are at about 150 nm, so this means that
not be able to integrate the elements of the array for the accuracy to 2–3% cannot be achieved [12].
purposes of addressing or reading out. Any such wires for (8) None of these findings preclude the use of such small
contacting and passing current on the 3 nm scale would be structures as one-offs subject to individual biasing.
subject to the same variability and consequent low yield as the
(9) The comments above have focused on electronic and
quantum pillars above. The transport would be well into the
optical properties, but they can be broadened to cover the
disordered regime and tunnelling of electrons between adjacent
variability of electromechanical properties, or indeed any
wires would be uncontrolled, resulting in uncontrolled and
other properties that might be used in sensing applications.
uncontrollable parasitic interference.
Given that 3 nm design rule arrays are intrinsically (10) Pace Feynman [13] and his 1959 lecture that initiated
unmanufacturable using a top-down process, what are the nanotechnology as we know it today, there is plenty of
wider implications of this result? room at the bottom for fabrication, but rather less for
manufacture!
(1) Current manufacture achieves 6σ yield, i.e. the pre-
specified range performance must encompass the ±3σ In summary, a 6 nm array of 3 nm diameter features is
range of the properties of the produced artefacts. At 3 nm intrinsically unmanufacturable using the most modern tools of
design rules we struggle to achieve even 2σ yield. microelectronic fabrication, because of the intolerable level of
(2) In practice there are many experimental examples that feature-to-feature fluctuations and the inability to address or
show intrinsic variability above the level imposed by the read out from individual sites on the array.
statistics of small numbers. It is important to note that,
in scaling for silicon CMOS technology, the limits are at a
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