5 4 3 2 1

D
X-S32K148EVBQ144/Q176 D
C U S T O M E R E V B

Table of Contents Revisions

01 TITLE AND NOTES Rev Description Designer Date Approved
02 POWER SUPPLY / LIN / CAN X4 Schematic J.Sanchez TBD
03 S32K148 MCU A Prototype
04 VOLTAGE TRANSLATORS AX1 First Release
05 OPEN SDA
06 ETHERNET
07 FLASH MEM
C 08 SAI AUDIO C

09 I/Os HEADERS
10 TOUCH
11 USER I/Os C A U T I O N :
This schematic is provided for reference
purposes only. As such, NXP does not make any 3 Different test points
warranty, implied or otherwise, as to the used in design:
suitability of circuit design or component
selection (type or value) used in these TPVx - Through Hole Pad
small
schematics for hardware design using the NXP
S32K family of Microprocessors. Customers using TPHx - Through Hile Pad
any part of these schematics as a basis for Large (for standard 0.1"
header). Also used on IO
hardware design, do so at their own risk and Matrix (IOMx)
Freescale does not assume any liability for such
a hardware design. TPX - Surface Mount Wire
Loop

B Notes: B

- All components and board processes are to be ROHS compliant

- All connectors and headers are denoted Jx/Px and are 2.54mm pitch unless otherwise stated
- All jumpers are denoted Jx. Jumpers are 2mm pitch
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always
posn 1-2.
2 Pin jumpers generally have the "source" on pin 1.
- All switches are denoted SWx
- All test points (SMT wire loop style) are denoted TPx
- Test point Vias (just through hole pads) are denoted TPVx

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
Signals (ports) have not been routed via busses as this makes it harder to determine
This document contains information proprietary to NXP and shall not be used for engineering design,
where each signal goes. procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
User notes are given throughtout the schematics. ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Specific PCB LAYOUT notes are detailed in ITALICS Jesus Sanchez
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez TITLE
Approved: Size Document Number Rev
Juan Romero B SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 1 of 11

5 4 3 2 1
 5 4 3 2 1

3.3V Switching Regulator

Input Voltage 5V, Output 3.3V at 1600mA
P5V0_V1SBC PVEXT_SBC

TP16 Battery supply

L2 330 OHM
input for SMPS R526 R527 TPAD23
1 2 DNP 0 R92 R97 1.69K
0603 0603 1.0K
R106 0603 0 1%
TP41 Buck/boost J18 VBAT P5V0 R93 1% DNP
D TP8 TP7 TS5 TP9 SMPS output HS-CAN/dual LIN HDR TH 1X3 TS2 TPAD8 TPAD15 U1 D
D4
J9 VBAT VSUP voltage system basis chip 1 D500
1 VBAT A C 2 A C 1 3
1

1
3 3 VIN FB TPAD20 L3 TPAD505 TP26 TPAD35TS7 P3V3_SW
2 C12 C13 C14 C21 C22 TP38 TP39 TP47 TP40 PMEG6045ETP 4.7uH
PMEG3050EP

VCAN_SBC
0.1uF + C11 0.1uF 0.1uF + C16 0.1uF 0.1uF R215 R216 C70 C71 L8 22uH 4 2 1 2 R633 0603 0
C63 4700 PF C69 4700 PF

1
SD OUT

GND1
GND2
GND3
GND4
CON PWR 3 47uF 47uF 0 0 22uF 22uF 1 2
SH1
SH2

Low Low R189 0603 0603 + C8 C501

C65 DNP C67 DNP

C
ESR ESR
C10 0 DNP 47uF 0.1UF C24
0.1uF 0603 JP1 AP1509-SG-13 D5 22uF C26 C30

5
6
7
8
DNP PMEG6045ETP 10V 0.1UF 0.1UF
P5V0_V1SBC P5V0_V2SBC

A
P5V0_V1SBC

1
C526 C528

29
26

38

43

20

47
U9

1
Bbootstrap capacitor R140 R132 0.1uF 10UF
R531 10.0K 10.0K Layout note: follow IC datasheet recommandations for

NC_29
BAT
BATV2
BATHS1

BATSMPS

VCAN

VSMPS
10.0K
PCB layout and thermal dissipation
C64 C62 TP37 TP34 TP24
4700 PF DNP 42
BOOTH1 44
41 L1 46
40 CAPA L2 48
CAPB BOOTH2
TPAD7 TS10 TP5
R163 1.0K 28 P5V0_V1SBC PVEXT_SBC
BATSENSE 6 TPAD39 TS11

1
C43 SBC_EN 5 V1 3 R204 0402 0
0.01UF EN V2 2

1
VEXT 27
PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX_LSR177 0402 0 7 ADCCAP TPAD30 TPAD29
PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN_LS R154 0402 0 8 SDI
PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX_LS R150 0402 0 9 SDO C29 C45 C47 C31 C54 C57 C60 VDD_MCU_PERH TP505 TP500 P5V0_V1SBC PVEXT_SBC
TX / RX PTA26/FTM5_CH1/LPSPI1_PCS0_LS R149 0402 0 10 SCK 11 R139 0402 0 0.01UF 10UF 10UF 0.1uF 10UF 10UF 0.1uF VCCA_LS_SBC
SCSN INTN1 13 0402 PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25_LS pag[2] VCCA_LS_SBC
R124 0 R5500603 0 R5170603 0
POKA-YOKE: Place both jumpers with INTN2 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26_LS pag[2]
R6320603 DNP
the same orientation and provide PTA3/LPUART0_TX_LS R128 0402 0 17 C521 C519 C522 C520 C515 C514 C513 C512
same airgap between their terminals PTA2/LPUART0_RX_LS TXDL1
in a square fashion. R129 0402 0 16 0.1uF 0.1uF 0.1uF 0.1uF R525 10.0K SBC_OE 0.1uF 0.1uF 0.1uF 0.1uF
RXDL1 24 SBC_LIN_OUT1 R542 0402 0 LIN1
LIN1 25 SBC_LIN_OUT2 R535 0402 0 LIN2 U504
PTA9/LPUART2_TX R130 0402 0 15 LIN2 TP14 TP10
PTA8/LPUART2_RX R131 0402 0 14 TXDL2 R543 0402 0 LIN1_OUT LIN1and LIN2 Bus 1 8
RXDL2 0402 LIN2_OUT LIN1_OUT pag[9] routed to I/O VCCA VCCB
R530 0 Connectors
LIN2_OUT pag[9] SBC_LIN1TX 0402 2 7 PTA3/LPUART0_TX_LS
pag[3,9] PTA3/LPUART0_TX R540 0
PTE5/CAN0_TX_LS R126 0402 0 19 21 SBC_CANH R112 0402 0 CAN_H SBC_LIN1RX R536 0402 0 3 A1 B1 6 PTA2/LPUART0_RX_LS
PTE4/CAN0_RX_LS TXDC CANH SBC_CANL CAN_L pag[3,9] PTA2/LPUART0_RX A2 B2
R127 0402 0 18 22 R135 0402 0
RXDC CANL 4 5
R119 0402 0 CANH_OUT CAN Bus GND OE
C SBC_RESET 0402 12 39 SBC_LIMP 0402 CANL_OUT CANH_OUT pag[9] routed to I/O C
R532 0 R134 0
RSTN LIMP CANL_OUT pag[9] Connectors
TP30 TP28 NTSX2102GU8H

30 SBC_HVIO8 D7
P5V0_V2SBC J14 VSUP VSUP
SBC_HVIO1 37 NC_30 31 SBC_HVIO7 C A R262 U500
J15 pag[2] SBC_HVIO1 1.8K
1 2 SBC_HVIO8 R334 10K R203 0402 0 SBC_HVIO2 36 HVIO1 NC_31 32 SBC_HVIO6 TP12 TP15
3 4 SBC_HVIO7 SBC_HVIO3 35 HVIO2 NC_32 33 SBC_HVIO5 1 8
SBC_LIMP 5 6 SBC_HVIO6 SBC_HVIO4 34 HVIO3 NC_33 VCCA VCCB
SBC_EN SBC_HVIO5 HVIO4 PTA9/LPUART2_TX

GNDSMPS
7 8 SW6 SBC_LIN2TX R511 0402 0 2 7
SBC_HVIO1 SBC_HVIO4 pag[3,9] PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2 A1 B1 PTA8/LPUART2_RX
1 2 C116 SBC_LIN2RX R512 0402 0 3 6
SBC_HVIO2 SBC_HVIO3 pag[3,9] PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 A2 B2

GND1

GND2
3 4 1 2

EPAD
4700 PF HVIO1-8
3 4 4 5
Bidirectional
open-drain low-side
Test and reference points GND OE
driver with

23

45

49
integrated pull-up TBD NTSX2102GU8H
SBC Wake-Up change to UJA1132/HW/5V0 GND4 GND3 GND2 GND5 TP59 TP3 TP58 TP1 TP56 TP4
resistance
U502

1
TP504 TP13
1 8
VCCA VCCB
R519 0402 0 2 7 PTE5/CAN0_TX_LS
pag[3] PTE5/TCLK2/FTM2_CH3/CAN0_TX/FXIO_D7 A1 B1 PTE4/CAN0_RX_LS
TRACE R520 0402 0 3 6
pag[3] PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 A2 B2
4 5
GND OE
TX / RX
NTSX2102GU8H
POKA-YOKE: Place both jumpers with
the same orientation and provide
same airgap between their terminals
in a square fashion.

CAN /FD Interface Power LED Indicators

Master LIN1 Interface TP20 TP11 U506
VSUP
option TP45 - LIN 2.x compliant VBAT HDR 1X4 RA TP25 TP22
J12 HDR1X2 D8 PMEG3050EP - Compliant with SAE J2602 1 8
1 2 A C 2K R226 CAN_H 1 VCCA VCCB
- Downward compatible with LIN 1.3
2K R225 2 SBC_SPI_MOSI R554 0402 0 2 7 PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN_LS
- Integrated LIN slave termination pag[3,9] PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN A1 B1 PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX_LS
DNP R180 3 SBC_SPI_MISO R555 0402 0 3 6
pag[3,9] PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX A2 B2
R125 C25 C20 4
VBAT 60.4 100PF 100PF VSUP P5V0 4 5
TP29 GND OE
J11
SPLIT
B LIN1 1 J13 NTSX2102GU8H B
2 HDR 1X4 RA
3 LIN Bus 1 C15 R138 R13 R9 R12 U507
C58 4 4700 PF 60.4 ISO 11898-2:201x (upcoming merged ISO 1.8K 560 560 TP21 TP17
220PF 11898-2/5/6) compliant 1 Mbit/s high-speed 1 8
VCCA VCCB
CAN transceiver supporting CAN FD active
CAN_L SBC_SPI_CLK R563 0402 0 2 7 PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX_LS
communication up to 2 Mbit/s in the CAN pag[3,9] PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX

A
SBC_SPI_CS R564 0402 0 3 A1 B1 6 PTA26/FTM5_CH1/LPSPI1_PCS0_LS
FD data field pag[3,9] PTA26/FTM5_CH1/LPSPI1_PCS0 A2 B2
DS1 DS2 DS3
4 5
GND OE

ORANGE

ORANGE

ORANGE
NTSX2102GU8H

C
R4 0603 0
pag[2] SBC_HVIO1
DNP

R500
0 U501
0603 TP502 TP501
1 8
VCCA VCCB
R528 0402 0 2 7
pag[3,9] PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25 0402 3 A1 B1 6 PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25_LS pag[2]
Global Supply Jumpers and R534 0
pag[3,9] PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26 A2 B2 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26_LS pag[2]
Power Selection TPAD501 4
GND OE
5

3
P3V3_SW
Master LIN2 Interface R504 10.0K 1 Q500
VSUP MMBT3904TT1G NTSX2102GU8H
option TP54 - LIN 2.x compliant P3V3_SW VDD P5V0 P5V0_V1SBC P5V0 P5V_SDA_PSW R502 33K

2
J21 HDR1X2 D9 PMEG3050EP - Compliant with SAE J2602 J8 TPAD2 TS12 R153 R523
1 2 A C 2K R276 J7 TPAD502 TS15 1 U503
- Downward compatible with LIN 1.3 10K 10K
2K R279 1 2 TP503
- Integrated LIN slave termination
1

2 3 TPAD500 1 8
1

VCCA VCCB

3
3 VDD
VBAT HDR TH 1X3 R505 10.0K 1 Q501 R537 0402 0 2 7 SBC_RESET
TP51 pag[3,4,5,9] PTA5/TCLK1_2/RESET A1 B1
HDR TH 1X3 MMBT3904TT1G 3 6
R503 33K A2 B2

2
LIN2 1 J17 4 5
2 HDR 1X4 RA J19 GND OE
3 LIN Bus 2
C77 4 NTSX2102GU8H
220PF VDD TPAD12 TPAD32 VDD_MCU VDD_MCU_PERH
2
1

R59 0603 0 TS16 TPAD17

R60 0603 0
1

A A

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ____ IUO: X PUBI: ____

Designer: Drawing Title:
Jesus Sanchez
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez I/O HEADERS
Approved: Size Document Number Rev
Juan Romero D SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 2 of 11

5 4 3 2 1
 5 4 3 2 1

R302 0402 0
pag[10] TOUCH_ADC0_A
R304 0402 0
pag[10] TOUCH_ADC1_A

R274 0402 0
S32K148 Microcontroller pag[3] PTB6_XTAL
pag[3] PTB7_EXTAL
R76
R78
0402
0402
0
0
PTB6_XTAL

PTB7_EXTAL
pag[10] TOUCH_ADC0_B
pag[10] TOUCH_ADC1_B R275 0402 0
144pins LQFP R64
DNP
0402 0

Y1
U7A 1 2
TS4 TPAD44 VDD_MCU
R205
TOUCH 0402 0 PTA0 115 8MHZ
pag[9] PTA0/ACMP0_IN0/ADC0_SE0 PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0
R206
TOUCH 0402 0 PTA1 113 C4 C3
pag[9] PTA1/ACMP0_IN1/ADC0_SE1
XTAL

1
105 PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1 12PF 12PF

VC080505C150RP
pag[2,3,9] PTA2/LPUART0_RX PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT/FXIO_D4/LPUART0_RX/ADC1_SE0

1
D 104 D
pag[2,3,9] PTA3/LPUART0_TX PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1
JTAG 142 DNP
pag[3,5] PTA4/CMP0_OUT/JTAG_TMS/SWD_DIO PTA4/CMP0_OUT/EWM_OUT/JTAG_TMS/SWD_DIO
141 32 C502 C504 C44 C72 C73 C50 C23 C505 C516 C525 C524 C503 C518 C510 C9 D2
pag[2,3,4,5,9] PTA5/TCLK1_2/RESET PTA5/TCLK1/RESET VDD1
85 11 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 10uF 10uF 10UF
pag[3,9] PTA6/FTM0_FLT1 PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE2 VDD2
83 67 DNP DNP
pag[3,9] PTA7/FTM0_FLT2

2
SBC_LIN2RX 144 PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE3 VDD3 51
pag[2,3,9] PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1 VDD4
SBC_LIN2TX 143 91
pag[2,3,9] PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2 PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT0 VDD5
pag[3] PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO JTAG 136 124
SAI 135 PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO VDD6
pag[3,8,9] PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC L1
134 13 TS3 TPAD14
pag[3,8,9] PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLK VDDA
SAI 130 VDDA_MCU
pag[3,8,9] PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0 PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D0 VREFH_MCU 30 OHMFER_BEAD
SAI 127 14 R508 0402 0 R509 0603 0
pag[3,8,9] PTA14/FTM0_FLT0/FTM3_FLT1/SAI0_D3

1
R191 0402
TOUCH 0 PTA15 120 PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D3 VREFH
pag[9] PTA15/FTM1_CH2/ADC1_SE12

1
R193 0402 0 PTA16 119 PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE12 15 VDD_MCU_PERH
pag[9] PTA16/FTM1_CH3/ADC1_SE13
TOUCH
ENET QSPI 92 PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE13 VREFL R506 0402 0 DNP
S32K148 Debugg Connector
pag[3,4,9] PTA17/FTM0_CH6/ENET_RESET VREFH pag[9]
pag[3,4,9] PTA25/FTM5_CH0
10 PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT/FTM5_FLT0
PTA25/FTM5_CH0 VSS1
66 C7 C506 C6 C507 C508 C509 C5 C511 D1 20-pin Cortex Debug D ETM connector
SBC_SPI_CS 19 31 1000pF 0.1uF 1000pF 0.1uF 1000pF 0.1uF 10uF 10uF
pag[2,3,9] PTA26/FTM5_CH1/LPSPI1_PCS0 PTA26/FTM5_CH1/LPSPI1_PCS0/LPSPI0_PCS0 VSS2
pag[2,3,9] PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX
SBC_SPI_MISO 22 16 DNP

2
SBC_SPI_CLK 24 PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX/CAN0_TX VSS3 12 C551
pag[2,3,9] PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX R72 R90 R95 R107 R518
SBC_SPI_MOSI 26 PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX/CAN0_RX VSS4 50 0.1uF DNP
pag[2,3,9] PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN 10K 10K 10K 10K
27 PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN VSS5 90
pag[3,9] PTA30/FTM5_CH5 PTA30/FTM5_CH5/LPUART2_RX/LPSPI0_SOUT VSS6 J10
33 123
pag[3,9] PTA31/FTM5_CH6 PTA31/FTM5_CH6/LPSPI0_PCS1 VSS7 1 2 R507 0402 0 JTAG
PTA4/CMP0_OUT/JTAG_TMS/SWD_DIO pag[3,5]
3 4 R510 0402 0 JTAG
PTC4/FTM1_CH0/RTC_CLKOUT/JTAG_TCLK/SWD_CLK pag[3,5]
PS32K118UEX0MLQT 5 6 R515 0402 0 JTAG
PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO pag[3]
TPAD24 7 8 R516 0402 0 JTAG
PTC5/FTM2_CH0/RTC_CLKOUT/JTAG_TDI pag[3]
U7B 9 10 R110 0402 0
TPAD26 PTA5/TCLK1_2/RESET pag[2,3,4,5,9]
R113 0402 0 11 12 R114 0402 0 TRACE
PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT pag[3,9]
78 U7E R121 0402 0 13 14 R122 0402 0 TRACE
pag[3,9] PTB0/SBC_LPSPI0_PCS0 PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE14 PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 pag[3,9]
77 138 SAI 15 16 R136 0402 0 TRACE
pag[3,9] PTB1/LPSPI0_SOUT PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE15 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D2 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/SAI0_D2 pag[3,8,9] PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 pag[2,3]
pag[3,9] PTB2/LPSPI0_SCK 68 137 SAI 17 18 R141 0402 0 TRACE
PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 pag[3,4]
63 PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D1 122 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1 pag[3,8,9] 19 20
pag[3,9] PTB3/LPSPI0_SIN R148 0402 0 TRACE
PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7 PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE10 PTE2/LPSPI0_SOUT/FTM3_CH6/SAI1_SYNC/ADC1_SE10 pag[3,8,9] PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 pag[3,8,9]
ENET QSPI 41 21
pag[3,4] PTB4/MII_RMII_MDIO/QSPI_B_IO0 40 PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO0 PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT 9 PTE3/FTM0_FLT0/FTM2_FLT0/CMP0_OUT pag[3,9]
TRACE
pag[3,4] PTB5/MII_RMII_MDC PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDC PTE4/TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 pag[2,3] HDR_2X10
18 8 R80
pag[3] PTB6_XTAL PTB6/LPI2C0_SDA/XTAL PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN PTE5/TCLK2/FTM2_CH3/CAN0_TX/FXIO_D7 pag[2,3]
17 121 10K
pag[3] PTB7_EXTAL PTB7/LPI2C0_SCL/EXTAL PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 pag[3,9]
111 87
pag[3,8,9] PTB8/FTM3_CH0/SAI1_BCLK PTB8/FTM3_CH0/SAI1_BCLK PTE7/FTM0_CH7/FTM3_FLT0 PTE7/FTM0_CH7/FTM3_FLT0 pag[3,9]
109 39
pag[3,6,8,9] PTB9/FTM3_CH1/LPI2C0_SCLS PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D0 PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 pag[3,9]
ENET_I2C_SDA 108 30
pag[3,6,8,9] PTB10/FTM3_CH2/LPI2C0_SDAS PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLK PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 pag[3,8,9]
107 6 ENET_SPI_CS1
pag[3,9] PTB11/FTM3_CH3/LPI2C0_HREQ PTB11/FTM3_CH3/LPI2C0_HREQ PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT4 PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4 pag[3,6,8,9]
98 5
pag[3,9] PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE7 PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5 PTE11/FTM2_CH5/FXIO_D5 pag[3,8,9]
97 23
pag[3,9] PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE8 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 pag[3,9]
96 7 ENET_SPI_CS2
pag[3,9] PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 pag[3,6,9]
95 20
pag[3,9] PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTE14/FTM0_FLT1/FTM2_FLT1 PTE14/FTM0_FLT1/FTM2_FLT1 pag[3,9]
R6350402 0 PTB16 94 2
pag[9] PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT6 PTE15/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2 pag[3,8,9]
93 1
pag[3,9] PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT7 PTE16/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3 pag[3,8,9]
36 125
pag[3,9] PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTE19/FTM7_CH7/ADC1_SE25 PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25 pag[2,3,9]
37 126
pag[3,4,9] PTB20/FTM6_CH0/ADC0_SE17 PTB20/FTM6_CH0/ADC0_SE17 PTE20/FTM4_CH0/ADC1_SE26 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26 pag[2,3,9]
38 128 PTE21 R541 0402 0
pag[3,9] PTB21/FTM6_CH1/ADC0_SE18 PTB21/FTM6_CH1/ADC0_SE18 PTE21/FTM4_CH1/ADC1_SE27 PTE21/FTM4_CH1/FTM4_CH1/ADC1_SE27 pag[9]
58 129 PTE22 R538 0402 0
pag[3,9] PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTE22/FTM4_CH2/ADC1_SE28 PTE22/FTM4_CH2/FTM4_CH2/ADC1_SE28 pag[9]
60 131 PTE23 R524 0402 0
pag[3,9] PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTE23/FTM4_CH3/ADC1_SE29 PTE23/FTM4_CH3/FTM4_CH3/ADC1_SE29 pag[9]
ENET_SPI_CS0 62 132
pag[3,6,9] PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTE24/FTM4_CH4/CAN2_TX/ADC1_SE30 PTE24/FTM4_CH4/CAN2_TX/FTM4_CH4/ADC1_SE30 pag[3,9]
ENET_SPI_MISO 64 133
pag[3,6,9] PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTE25/FTM4_CH5/CAN2_RX/ADC1_SE31 PTE25/FTM4_CH5/CAN2_RX/CAN2_RX/FTM4_CH5/ADC1_SE31 pag[3,9]
ENET_SPI_MOSI 65
pag[3,6,9] PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23
ENET_SPI_SCK 69 R544 0402 0
pag[3,6,9] PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 LED_RED pag[11]
PS32K118UEX0MLQT R533 0402 0
LED_GREEN pag[11]
R529 0402 0
LED_BLUE pag[11]
pag[3,11] ADC_POT R634 0402 DNP PS32K118UEX0MLQT
U7D
U7C
4
53 PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/TRACE_D0/FXIO_D0/TRGMUX_OUT1 3 PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 pag[3,9]
ENET QSPI SAI
pag[3,4] PTC0/MII_RMII_RXD1/QSPI_B_RWDS PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH6/QSPI_B_RWDS/ADC0_SE8 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT2 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK pag[3,8,9]
ENET QSPI 52 102
pag[3,4] PTC1/MII_RMII_RXD0/QSPI_B_SCK PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH7/QSPI_B_SCK/ADC0_SE9 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/ADC1_SE2 pag[3,9]
ENET QSPI 43 101
pag[3,4] PTC2/MII_RMII_TXD0/QSPI_A_IO3 PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD0/TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CMP0_IN5 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI/ADC1_SE3 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/ADC1_SE3 pag[3,9]
ENET QSPI 42 100
pag[3,4] PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3 PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN4 PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6 PTD4/FTM0_FLT3/ADC1_SE6 pag[3,9]
pag[3,5] PTC4/FTM1_CH0/RTC_CLKOUT/JTAG_TCLK/SWD_CLK JTAG 140 46 ENET QSPI
JTAG 139 PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2 PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO2 45 PTD5/MII_TXD3/QSPI_B_IO2 pag[3,4]
ENET QSPI
pag[3] PTC5/FTM2_CH0/RTC_CLKOUT/JTAG_TDI PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN7 PTD6/MII_TXD2/QSPI_B_IO1 pag[3,4]
118 44 ENET QSPI
pag[3,5,9] PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4 PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD1/TRACE_D0/QSPI_A_IO1/CMP0_IN6 PTD7/MII_RMII_TXD1//QSPI_A_IO1 pag[3,4]
117 55 ENET QSPI
pag[3,5,9] PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5 PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO5 PTD8/MII_RXD3/QSPI_B_IO5 pag[3,4]
81 54 ENET QSPI
pag[3,5,9] PTC8/LPUART1_RX PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTS PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO4 PTD9/MII_RXD2/QSPI_B_IO4 pag[3,4]
80 49
pag[3,5,9] PTC9/LPUART1_TX PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTS PTD10/FTM2_CH0/FTM2_QD_PHB/TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCK PTD10/MII_RX_CLK/QSPI_A_SCK pag[3,4]
75 48 ENET QSPI TRACE
pag[3,9] PTC10/FTM3_CH4/TRGMUX_IN11 PTC10/FTM3_CH4/TRGMUX_IN11 PTD11/FTM2_CH1/FTM2_QD_PHA/TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO0 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 pag[3,4]
74 47 ENET QSPI
pag[3,9] PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTD12/FTM2_CH2/LPI2C1_HREQ/TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO2 PTD12/MII_RMII_TX_EN/QSPI_A_IO2 pag[3,4]
pag[9] PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS R5670402 0 PTC12 71 35
PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT pag[3,8,9]
R5610402 0 PTC13 70 34
pag[9] PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT pag[3,8,9]
61 29 TRACE
pag[3,9] PTC14/FTM1_CH2/LPSPI2_PCS0/ADC0_SE12 59 PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE12 PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 28 PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 pag[3,8,9]
ENET QSPI TRACE
pag[3,9] PTC15/FTM1_CH3/LPSPI2_SCK/QSPI_B_CS PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE13 PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/CMP0_RRT/TRACE_CLKOUT PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT pag[3,9]
pag[3,4] PTC16/MII_RMII_RX_ER/QSPI_B_IO7 ENET QSPI 57 25
56 PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE14 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 88 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 pag[3,9]
ENET QSPI
pag[3,4] PTC17/MII_RMII_RX_DV/QSPI_B_IO6 72 PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE15 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 89 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 pag[3,8,9]
C pag[3,9] PTC19/FTM7_CH5/ADC0_SE25 PTC19/FTM7_CH5/LPSPI2_PCS1/ADC0_SE25 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 pag[3,8,9] C
73 99
pag[3,9] PTC23/LPSPI0_SCK/ADC0_SE26 PTC23/LPSPI0_SCK/ADC0_SE26 PTD22/FTM6_CH3/ADC1_SE18 PTD22/FTM6_CH3/FTM6_CH3/ADC1_SE18 pag[3,9]
76 103
pag[3,9] PTC27/FTM4_CH4/FTM4_CH4/ADC0_SE27 PTC27/FTM4_CH4/ADC0_SE27 PTD23/FTM6_CH4/ADC1_SE19 PTD23/FTM6_CH4/FTM6_CH4/ADC1_SE19 pag[3,9]
pag[9] PTC28/FTM4_CH7/FTM4_CH7/ADC0_SE28 R246 0402 0 PTC28 79 106
82 PTC28/FTM4_CH7/ADC0_SE28 PTD24/FTM6_CH5/ADC1_SE20 110 PTD24/FTM6_CH5/FTM6_CH5/ADC1_SE20 pag[3,9]
pag[3,9] PTC29/FTM5_CH2/FTM5_CH2/ADC0_SE29 PTC29/FTM5_CH2/ADC0_SE29 PTD27/FTM7_CH0/ADC1_SE21 PTD27/FTM7_CH0/FTM7_CH0/ADC1_SE21 pag[3,9]
84 112
pag[3,8,9] PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/FXIO_D0/ADC0_SE30 PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/ADC0_SE30 PTD28/FTM7_CH1/ADC1_SE22 PTD28/FTM7_CH1/FTM7_CH1/ADC1_SE22 pag[3,9]
pag[3,8,9] PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31 86 114
PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/ADC0_SE31 PTD29/FTM7_CH2/ADC1_SE23 116 PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23 pag[3,6,9]
PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 pag[3,9]
PS32K118UEX0MLQT
PS32K118UEX0MLQT
pag[11] PTC12/BTN0 R565 0402 0
pag[11] PTC13/BTN1 R562 0402 0
pag[3,11] ADC_POT R583 0402 0

VDD_MCU VDDA_MCU
S32K148 Microcontroller
U8A 176pins LQFP
TOUCH PTA0 140
TOUCH PTA1 138 PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0
126 PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1
pag[2,3,9] PTA2/LPUART0_RX PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT/FXIO_D4/LPUART0_RX/ADC1_SE0
125
pag[2,3,9] PTA3/LPUART0_TX PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1
JTAG 173 18
pag[3,5] PTA4/CMP0_OUT/JTAG_TMS/SWD_DIO PTA4/CMP0_OUT/EWM_OUT/JTAG_TMS/SWD_DIO VDD1
170 39
pag[2,3,4,5,9] PTA5/TCLK1_2/RESET PTA5/TCLK1/RESET VDD2
104 59
pag[3,9] PTA6/FTM0_FLT1 PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE2 VDD3
102 77
pag[3,9] PTA7/FTM0_FLT2 PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE3 VDD4
SBC_LIN2RX 176 110
pag[2,3,9] PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1 VDD5
pag[2,3,9] PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2
SBC_LIN2TX 175 129
JTAG 164 PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT0 VDD6 152
pag[3] PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO VDD7
SAI 163 172
pag[3,8,9] PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC VDD8
162 TS1 TPAD9
pag[3,8,9] PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK SAI PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLK
158 20
pag[3,8,9] PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0 PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D0 VDDA
SAI 155
pag[3,8,9] PTA14/FTM0_FLT0/FTM3_FLT1/SAI0_D3

1
TOUCH PTA15 148 PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D3 21 VREFH_MCU
TOUCH PTA16 146 PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE12 VREFH
ENET QSPI 111 PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE13 22
pag[3,4,9] PTA17/FTM0_CH6/ENET_RESET PTA17/FTM0_CH6/FTM3_FLT0/EWM_OUT/FTM5_FLT0 VREFL
1
pag[9] PTA18/FTM4_CH0/LPUART1_TX/LPSPI1_SOUT/FTM6_CH0 PTA18/FTM4_CH0/LPUART1_TX/LPSPI1_SOUT/FTM6_CH0
2
pag[9] PTA19/FTM4_CH1/LPUART1_RX/LPSPI1_SCK PTA19/FTM4_CH1/LPUART1_RX/LPSPI1_SCK
3 19
pag[9] PTA20/FTM4_CH2/LPSPI1_SIN PTA20/FTM4_CH2/LPSPI1_SIN VSS1
pag[9] PTA21/FTM4_CH3/FXIO_D0/LPSPI1_PCS0 6 23
9 PTA21/FTM4_CH3/FXIO_D0/LPSPI1_PCS0 VSS2 38
pag[9] PTA22/FTM4_CH4/FXIO_D1/LPSPI1_PCS1 PTA22/FTM4_CH4/FXIO_D1/LPSPI1_PCS1 VSS3
13 58
pag[9] PTA23/FTM4_CH6/FXIO_D2 PTA23/FTM4_CH6/FXIO_D2 VSS4
16 76
pag[9] PTA24/FTM4_CH7/FXIO_D3 PTA24/FTM4_CH7/FXIO_D3 VSS5
17 109
pag[3,4,9] PTA25/FTM5_CH0 PTA25/FTM5_CH0 VSS6
SBC_SPI_CS 26 130
pag[2,3,9] PTA26/FTM5_CH1/LPSPI1_PCS0 PTA26/FTM5_CH1/LPSPI1_PCS0/LPSPI0_PCS0 VSS7
SBC_SPI_MISO 29 151
pag[2,3,9] PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX/CAN0_TX VSS8
SBC_SPI_CLK 31 171
pag[2,3,9] PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX/CAN0_RX VSS9
pag[2,3,9] PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN
SBC_SPI_MOSI 33
34 PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN
pag[3,9] PTA30/FTM5_CH5 PTA30/FTM5_CH5/LPUART2_RX/LPSPI0_SOUT
40
pag[3,9] PTA31/FTM5_CH6 PTA31/FTM5_CH6/LPSPI0_PCS1

PS32K118UEX0MLUT

U8B

97 U8E
B pag[3,9] PTB0/SBC_LPSPI0_PCS0 PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE14 B
96
pag[3,9] PTB1/LPSPI0_SOUT PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE15
78 166 SAI
pag[3,9] PTB2/LPSPI0_SCK PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D2 PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/SAI0_D2 pag[3,8,9]
73 165 SAI
pag[3,9] PTB3/LPSPI0_SIN PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D1 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1 pag[3,8,9]
ENET QSPI 49 150
pag[3,4] PTB4/MII_RMII_MDIO/QSPI_B_IO0 48 PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO0 PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE10 28 PTE2/LPSPI0_SOUT/FTM3_CH6/SAI1_SYNC/ADC1_SE10 pag[3,8,9]
pag[3,4] PTB5/MII_RMII_MDC PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDC PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT PTE3/FTM0_FLT0/FTM2_FLT0/CMP0_OUT pag[3,9]
25 15 TRACE
pag[3] PTB6_XTAL PTB6/LPI2C0_SDA/XTAL PTE4/TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT PTE4/TRACE_D1/FTM2_CH2/CAN0_RX/FXIO_D6 pag[2,3]
24 14
pag[3] PTB7_EXTAL PTB7/LPI2C0_SCL/EXTAL PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN PTE5/TCLK2/FTM2_CH3/CAN0_TX/FXIO_D7 pag[2,3]
136 149
pag[3,8,9] PTB8/FTM3_CH0/SAI1_BCLK PTB8/FTM3_CH0/SAI1_BCLK PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 pag[3,9]
ENET_I2C_SCL 133 106
pag[3,6,8,9] PTB9/FTM3_CH1/LPI2C0_SCLS PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D0 PTE7/FTM0_CH7/FTM3_FLT0 PTE7/FTM0_CH7/FTM3_FLT0 pag[3,9]
ENET_I2C_SDA 131 47
pag[3,6,8,9] PTB10/FTM3_CH2/LPI2C0_SDAS PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLK PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 pag[3,9]
128 37
pag[3,9] PTB11/FTM3_CH3/LPI2C0_HREQ PTB11/FTM3_CH3/LPI2C0_HREQ PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 pag[3,8,9]
119 11 ENET_SPI_CS1
pag[3,9] PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE7 PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT4 PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4 pag[3,6,8,9]
118 10
pag[3,9] PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE8 PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5 PTE11/FTM2_CH5/FXIO_D5 pag[3,8,9]
116 30
pag[3,9] PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 pag[3,9]
115 12 ENET_SPI_CS2
pag[3,9] PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 pag[3,6,9]
PTB6 114 27
112 PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 PTE14/FTM0_FLT1/FTM2_FLT1 5 PTE14/FTM0_FLT1/FTM2_FLT1 pag[3,9]
pag[3,9] PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT6 PTE15/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2 pag[3,8,9]
43 4
pag[3,9] PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT7 PTE16/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3 pag[3,8,9]
44 145
pag[9] PTB19/FTM5_CH7 PTB19/FTM5_CH7 PTE17/FTM7_CH5/FXIO_D5 PTE17/FTM7_CH5/FXIO_D5 pag[9]
45 147
pag[3,4,9] PTB20/FTM6_CH0/ADC0_SE17 PTB20/FTM6_CH0/ADC0_SE17 PTE18/FTM7_CH6/FXIO_D4 PTE18/FTM7_CH6/FXIO_D4 pag[9]
46 153
pag[3,9] PTB21/FTM6_CH1/ADC0_SE18 PTB21/FTM6_CH1/ADC0_SE18 PTE19/FTM7_CH7/ADC1_SE25 PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25 pag[2,3,9]
66 154
pag[3,9] PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTE20/FTM4_CH0/ADC1_SE26 PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26 pag[2,3,9]
68 156 PTE21
pag[3,9] PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 PTE21/FTM4_CH1/ADC1_SE27
69 157 PTE22
pag[9] PTB24/FTM6_CH4 PTB24/FTM6_CH4 PTE22/FTM4_CH2/ADC1_SE28
71 159 PTE23
pag[3,6,9] PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 PTE23/FTM4_CH3/ADC1_SE29
pag[9] PTB26/FTM6_CH6 72 160
ENET_SPI_MISO 74 PTB26/FTM6_CH6 PTE24/FTM4_CH4/CAN2_TX/ADC1_SE30 161 PTE24/FTM4_CH4/CAN2_TX/FTM4_CH4/ADC1_SE30 pag[3,9]
pag[3,6,9] PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTE25/FTM4_CH5/CAN2_RX/ADC1_SE31 PTE25/FTM4_CH5/CAN2_RX/CAN2_RX/FTM4_CH5/ADC1_SE31 pag[3,9]
ENET_SPI_MOSI 75 167
pag[3,6,9] PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTE26/FTM4_CH6 PTE26/FTM4_CH6 pag[9]
ENET_SPI_SCK 79 174
pag[3,6,9] PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTE27/FTM4_CH7 PTE27/FTM4_CH7 pag[9]
80
pag[9] PTB30/FTM7_CH2 PTB30/FTM7_CH2
82
pag[9] PTB31/FTM7_CH3 PTB31/FTM7_CH3 PS32K118UEX0MLUT

PS32K118UEX0MLUT

U8C
U8D
ENET QSPI 61
pag[3,4] PTC0/MII_RMII_RXD1/QSPI_B_RWDS PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH6/QSPI_B_RWDS/ADC0_SE8
ENET QSPI 60 8
pag[3,4] PTC1/MII_RMII_RXD0/QSPI_B_SCK PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD1/MII_RMII_RXD0/FTM1_CH7/QSPI_B_SCK/ADC0_SE9 PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/TRACE_D0/FXIO_D0/TRGMUX_OUT1 PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 pag[3,9]
ENET QSPI 51 7 SAI
pag[3,4] PTC2/MII_RMII_TXD0/QSPI_A_IO3 PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD0/TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CMP0_IN5 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT2 PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK pag[3,8,9]
ENET QSPI 50 123
pag[3,4] PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3 JTAG 169 PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN4 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2 122 PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/ADC1_SE2 pag[3,9]
pag[3,5] PTC4/FTM1_CH0/RTC_CLKOUT/JTAG_TCLK/SWD_CLK PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI/ADC1_SE3 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/ADC1_SE3 pag[3,9]
pag[3] PTC5/FTM2_CH0/RTC_CLKOUT/JTAG_TDI
JTAG 168 121
144 PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6 54 PTD4/FTM0_FLT3/ADC1_SE6 pag[3,9]
ENET QSPI
pag[3,5,9] PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4 PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO2 PTD5/MII_TXD3/QSPI_B_IO2 pag[3,4]
143 53 ENET QSPI
pag[3,5,9] PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5 PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN7 PTD6/MII_TXD2/QSPI_B_IO1 pag[3,4]
SBC 100 52 ENET QSPI
pag[3,5,9] PTC8/LPUART1_RX PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTS PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD1/TRACE_D0/QSPI_A_IO1/CMP0_IN6 PTD7/MII_RMII_TXD1//QSPI_A_IO1 pag[3,4]
SBC 99 63 ENET QSPI
pag[3,5,9] PTC9/LPUART1_TX PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTS PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO5 PTD8/MII_RXD3/QSPI_B_IO5 pag[3,4]
94 62 ENET QSPI
pag[3,9] PTC10/FTM3_CH4/TRGMUX_IN11 PTC10/FTM3_CH4/TRGMUX_IN11 PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO4 PTD9/MII_RXD2/QSPI_B_IO4 pag[3,4]
92 57
pag[3,9] PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10 PTD10/FTM2_CH0/FTM2_QD_PHB/TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCK PTD10/MII_RX_CLK/QSPI_A_SCK pag[3,4]
PTC12 84 56
ENET QSPI TRACE
PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS PTD11/FTM2_CH1/FTM2_QD_PHA/TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO0 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 pag[3,4]
PTC13 81 55 ENET QSPI
PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS PTD12/FTM2_CH2/LPI2C1_HREQ/TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO2 PTD12/MII_RMII_TX_EN/QSPI_A_IO2 pag[3,4]
70 42
pag[3,9] PTC14/FTM1_CH2/LPSPI2_PCS0/ADC0_SE12 ENET QSPI 67 PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE12 PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT 41 PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT pag[3,8,9]
pag[3,9] PTC15/FTM1_CH3/LPSPI2_SCK/QSPI_B_CS PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE13 PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT pag[3,8,9]
ENET QSPI 65 36 TRACE
pag[3,4] PTC16/MII_RMII_RX_ER/QSPI_B_IO7 PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE14 PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 pag[3,8,9]
ENET QSPI 64 35 TRACE
pag[3,4] PTC17/MII_RMII_RX_DV/QSPI_B_IO6 PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE15 PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/CMP0_RRT/TRACE_CLKOUT PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT pag[3,9]
83 32
pag[9] PTC18/FTM7_CH4 PTC18/FTM7_CH4 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 pag[3,9]
85 107
pag[3,9] PTC19/FTM7_CH5/ADC0_SE25 PTC19/FTM7_CH5/LPSPI2_PCS1/ADC0_SE25 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 pag[3,8,9]
pag[9] PTC20/FTM7_CH6 86 108
87 PTC20/FTM7_CH6 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 113 PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 pag[3,8,9]
pag[9] PTC21/FTM7_CH7/FTM7_FLT0 PTC21/FTM7_CH7/FTM7_FLT0 PTD20/FTM6_CH1 PTD20/FTM6_CH1 pag[9]
88 117
pag[9] PTC22/FTM7_FLT1 PTC22/FTM7_FLT1 PTD21/FTM6_CH2 PTD21/FTM6_CH2 pag[9]
89 120
pag[3,9] PTC23/LPSPI0_SCK/ADC0_SE26 PTC23/LPSPI0_SCK/ADC0_SE26 PTD22/FTM6_CH3/ADC1_SE18 PTD22/FTM6_CH3/FTM6_CH3/ADC1_SE18 pag[3,9]
90 124
pag[9] PTC24/FTM4_CH0 PTC24/FTM4_CH0 PTD23/FTM6_CH4/ADC1_SE19 PTD23/FTM6_CH4/FTM6_CH4/ADC1_SE19 pag[3,9]
91 127
pag[9] PTC25/FTM4_CH1 PTC25/FTM4_CH1 PTD24/FTM6_CH5/ADC1_SE20 PTD24/FTM6_CH5/FTM6_CH5/ADC1_SE20 pag[3,9]
93 132
pag[9] PTC26/FTM4_CH3 PTC26/FTM4_CH3 PTD25/FTM6_CH6 PTD25/FTM6_CH6 pag[9]
95 134
pag[3,9] PTC27/FTM4_CH4/FTM4_CH4/ADC0_SE27 PTC27/FTM4_CH4/ADC0_SE27 PTD26/FTM6_CH7/FXIO_D7 PTD26/FTM6_CH7/FXIO_D7 pag[9]
PTC28 98 135
101 PTC28/FTM4_CH7/ADC0_SE28 PTD27/FTM7_CH0/ADC1_SE21 137 PTD27/FTM7_CH0/FTM7_CH0/ADC1_SE21 pag[3,9]
pag[3,9] PTC29/FTM5_CH2/FTM5_CH2/ADC0_SE29 PTC29/FTM5_CH2/ADC0_SE29 PTD28/FTM7_CH1/ADC1_SE22 PTD28/FTM7_CH1/FTM7_CH1/ADC1_SE22 pag[3,9]
pag[3,8,9] PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/FXIO_D0/ADC0_SE30 103 139
105 PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/ADC0_SE30 PTD29/FTM7_CH2/ADC1_SE23 141 PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23 pag[3,6,9]
pag[3,8,9] PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31 PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/ADC0_SE31 PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24 pag[3,9]
142
PTD31/FTM7_CH4/FXIO_D6/FTM6_FLT0 PTD31/FTM7_CH4/FXIO_D6/FTM6_FLT0 pag[9]
PS32K118UEX0MLUT
PS32K118UEX0MLUT

A A

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ____ IUO: X PUBI: ____

Designer: Drawing Title:
Jesus Sanchez
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez I/O HEADERS
Approved: Size Document Number Rev
Juan Romero E SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 3 of 11

5 4 3 2 1
 5 4 3 2 1

D D

VDD_MCU_PERH TPAD40 TS8 VCCA_VTRANSL P3V3_SW

L7 P5V0
3.3 V / 5.0V TS14 TPAD45 R182 0603 0

1
MCU Reference
FER_BEAD 30 OHM
VCCB_VTRANSL
R242 0402 0 C59 C530 C61 C527 C46 C68 C80 C83 R181 0603 DNP

1
10uF 1000PF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C56 C55 C84 C81 C75 C41 C32 C53 3.3 Volts
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1000PF 10uF by Default
TPAD42

R553 0402 0
pag[3,9] PTA25/FTM5_CH0 R5520402 0
DNP

ENTHERNET Lines
ENABLED by
R576 R577 R578 R579 R557 R558 R559 R560 Default
51K 51K 51K 51K TXB0104 U13 51K 51K 51K 51K
DNP DNP DNP DNP 14 1 DNP DNP DNP DNP
VCCB VCCA
ENET QSPI R233 0402 0 PTD9/MII_RXD2/QSPI_B_IO4__A 13 2 PTD9/MII_RXD2/QSPI_B_IO4__B R198 0402 0 ENET
pag[3] PTD9/MII_RXD2/QSPI_B_IO4 ENET QSPI 0402 PTD8/MII_RXD3/QSPI_B_IO5__A 12 B1 A1 3 PTD8/MII_RXD3/QSPI_B_IO5__B 0402 ENET PTD9/MII_RXD2 pag[6]
R232 0 R197 0
pag[3] PTD8/MII_RXD3/QSPI_B_IO5 ENET QSPI 0402 PTC17/MII_RMII_RX_DV/QSPI_B_IO6__A 11 B2 A2 4 PTC17/MII_RMII_RX_DV/QSPI_B_IO6__B 0402 ENET PTD8/MII_RXD3 pag[6]
R231 0 R196 0
pag[3] PTC17/MII_RMII_RX_DV/QSPI_B_IO6 ENET QSPI 0402 PTC16/MII_RMII_RX_ER/QSPI_B_IO7__A 10 B3 A3 5 PTC16/MII_RMII_RX_ER/QSPI_B_IO7__B 0402 ENET PTC17/MII_RMII_RX_DV pag[6]
pag[3] PTC16/MII_RMII_RX_ER/QSPI_B_IO7 R230 0 R195 0
B4 A4 PTC16/MII_RMII_RX_ER pag[6]
6
9 NC 8
15 NC1 OE 7
EXP GND
C R572 R571 R570 R573 R602 R601 R600 R599 C
51K 51K 51K 51K TXB0104 U14 51K 51K 51K 51K
DNP DNP DNP DNP 14 1 DNP DNP DNP DNP
VCCB VCCA
ENET QSPI R227 0402 0 PTB4/MII_RMII_MDIO/QSPI_B_IO0__A 13 2 PTB4/MII_RMII_MDIO/QSPI_B_IO0__B R268 0402 0 ENET
pag[3] PTB4/MII_RMII_MDIO/QSPI_B_IO0 ENET QSPI 0402 PTD6/MII_TXD2/QSPI_B_IO1__A 12 B1 A1 3 PTD6/MII_TXD2/QSPI_B_IO1__B 0402 ENET PTB4/MII_RMII_MDIO pag[6]
R223 0 R269 0
pag[3] PTD6/MII_TXD2/QSPI_B_IO1 ENET QSPI 0402 PTD5/MII_TXD3/QSPI_B_IO2__A B2 A2 PTD5/MII_TXD3/QSPI_B_IO2__B ENET PTD6/MII_TXD2 pag[6]
R580 0 11 4 R270 0402 0
pag[3] PTD5/MII_TXD3/QSPI_B_IO2 ENET QSPI 0402 PTD7/MII_RMII_TXD1//QSPI_A_IO1__A 10 B3 A3 5 PTD7/MII_RMII_TXD1//QSPI_A_IO1__B PTD5/MII_TXD3 pag[6]
pag[3] PTD7/MII_RMII_TXD1//QSPI_A_IO1 R224 0
6 B4 A4 R271 0402 DNP HYPFLASH
NC PTD7/QSPI_A_IO1 pag[7]
9 8 R272 0402 0 ENET
NC1 OE PTD7/MII_RMII_TXD1 pag[6]
15 7
EXP GND HyperFLASH &
R593 R588 R584 R582 R598 R596 R592 R587
51K 51K 51K 51K TXB0104 U16 51K 51K 51K 51K Ethernet Connector
S32K148 DNP DNP DNP DNP 14
VCCB VCCA
1 DNP DNP DNP DNP
MCU SIGNALS pag[3] PTC0/MII_RMII_RXD1/QSPI_B_RWDS
ENET QSPI R259 0402 0 PTC0/MII_RMII_RXD1/QSPI_B_RWDS__A 13 2 PTC0/MII_RMII_RXD1/QSPI_B_RWDS__B R277 0402 0 ENET
PTC0/MII_RMII_RXD1 pag[6]
ENET QSPI R253 0402 0 PTC1/MII_RMII_RXD0/QSPI_B_SCK__A 12 B1 A1 3 PTC1/MII_RMII_RXD0/QSPI_B_SCK__B R264 0402 0 ENET
pag[3] PTC1/MII_RMII_RXD0/QSPI_B_SCK ENET QSPI 0402 PTC2/MII_RMII_TXD0/QSPI_A_IO3__A B2 A2 PTC2/MII_RMII_TXD0/QSPI_A_IO3__B PTC1/MII_RMII_RXD0 pag[6]
pag[3] PTC2/MII_RMII_TXD0/QSPI_A_IO3 R249 0 11 4
ENET QSPI R243 0402 0 PTD10/MII_RX_CLK/QSPI_A_SCK__A 10 B3 A3 5 PTD10/MII_RX_CLK/QSPI_A_SCK__B R260 0402 0 ENET
pag[3] PTD10/MII_RX_CLK/QSPI_A_SCK B4 A4 PTC2/MII_RMII_TXD0 pag[6]
6 R254 0402 DNP HYPFLASH
NC PTC2/QSPI_A_IO3 pag[7]
9 8
15 NC1 OE 7 R250 0402 0 ENET
EXP GND 0402 HYPFLASH PTD10/MII_RX_CLK pag[6]
R244 DNP PTD10/QSPI_A_SCK pag[7]
R548 R547 R546 R176 R566 R569 R568 R214
51K 51K 51K 51K TXB0104 U11 51K 51K 51K 51K
DNP DNP DNP 14 1 DNP DNP DNP
VCCB VCCA
ENET QSPI R165 0402 0 PTD12/MII_RMII_TX_EN/QSPI_A_IO2__A 13 2 PTD12/MII_RMII_TX_EN/QSPI_A_IO2__B R208 0402 0 ENET
pag[3] PTD12/MII_RMII_TX_EN/QSPI_A_IO2 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0__A B1 A1 PTD11/MII_RMII_TX_CLK/QSPI_A_IO0__B PTD12/MII_RMII_TX_EN pag[6]
ENET QSPI TRACE R173 0402 0 12 3 R209 0402 DNP HYPFLASH
pag[3] PTD11/MII_RMII_TX_CLK/QSPI_A_IO0 PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3__A B2 A2 PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3__B PTD12/QSPI_A_IO2 pag[7]
ENET QSPI R175 0402 0 11 4
pag[3] PTC3/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3 B3 A3 ENET
10 5 R210 0402 0
B4 A4 PTD11/MII_RMII_TX_CLK pag[6]
6 R211 0402 DNP HYPFLASH
NC PTD11/QSPI_A_IO0 pag[7]
9 8
15 NC1 OE 7 R212 0402 0 ENET
EXP GND 0402 HYPFLASH PTC3/MII_TX_ER pag[6]
R213 DNP
R603 R597 R594 R589 R273 R263 R258 R252 PTC3/QSPI_A_CS pag[7]
51K 51K 51K 51K TXB0104 U22 51K 51K 51K 51K
DNP DNP DNP DNP 14 1 DNP DNP DNP DNP
VCCB VCCA
R604 0402 0 PTB5/MII_RMII_MDC__A 13 2
pag[3] PTB5/MII_RMII_MDC ENET QSPI 0402 PTB20/FTM6_CH0/ADC0_SE17__A B1 A1 PTB5/ENET_MII_RMII_MDC pag[6]
R265 0 12 3
pag[3,9] PTB20/FTM6_CH0/ADC0_SE17 ENETSW_RESET_A B2 A2 PTB20/FTM6_CH0/ENET_INT pag[6]
ENET QSPI R261 0402 0 11 4
pag[3,9] PTA17/FTM0_CH6/ENET_RESET 0402 B3 A3 ENETSW_RESET pag[6]
R251 DNP 10 5
pag[2,3,5,9] PTA5/TCLK1_2/RESET B4 A4
6
9 NC 8
15 NC1 OE 7
EXP GND

B R234 C66 B
51K DNP
10uF

A A

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ____ IUO: X PUBI: ____

Designer: Drawing Title:
J.SANCHEZ
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez 06. LEVELTRANS_MUXDEMUX
Approved: Size Document Number Rev
<Approver> D SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 4 of 11

5 4 3 2 1
 5 4 3 2 1

OpenSDA Interface
D P3V3_SDA V_TGTMCU D

C540 C539 R616 R613 C542 C544

0.1UF 4.7uF 10.0K 10.0K R610 R614 R611 4.7uF 0.1UF
4.7K 180K 10.0K
RESET
U509

U510 P3V3_SDA 1 8
VCCA VCCB
SDA_RST_TGTMCU_J_B 2 7
P3V3_SDA TPAD48 3 A1 B1 6
R286 U23 A2 B2
1 74LVC2G14GV 4 5 LVLRST_EN
VDD1 10.0K GND OE
P3V3_SDA
C536 C535 C545 C538 SDA_SWD_EN_B_R 1 A1 Y1 6 SDA_SWD_EN
10uF 4.7uF 1.0UF 0.1UF NTSX2102GU8H
7 2 5
VDDA GND VCC
RST J22
P3V3_SDA 3 A2 Y2 4 SDA_SWD_OE Push HDR TH 1X3
R609 Button SW5

3
2
1
8 0 C97 Bypass R289 0
VSSA 12 SDA_JTAG_TCLK R285 0.1UF 1 2 SW1_RST_B
JTAG_TCLK/SWD_CLK/EZP_CLK/TSI0_CH1/PTA0/UART0_CTS/UART0_COL/FTM0_CH5 13 SDA_JTAG_TDI 10.0K 3 4
JTAG_TDI/EZP_DI/TSI0_CH2/PTA1/UART0_RX/FTM0_CH6 14 SDA_JTAG_TDO C543 V_TGTMCU
JTAG_TDO/TRACE_SWO/EZP_DO/TSI0_CH3/PTA2/UART0_TX/FTM0_CH7 15 SDA_JTAG_TMS SDA_SWD_OE_B_R 1000pF D11
JTAG_TMS/SWD_DIO/TSI0_CH4/PTA3/UART0_RTS/FTM0_CH0 SDA_SWD_EN_B EVQ-P2402W SDA_RST_LED R337
P5V_SDA 16 C A
L9 NMI/EZP_CS/TSI0_CH5/PTA4/FTM0_CH1/LLWU_P3 330 OHM
1 2 11
VBAT R284 RED
C111 SDA_EXTAL 0
J24 330 OHM 10uF SDA_VOUT33 P5V_SDA SDA_XTAL Y501
USB_MICRO_AB 1 3 TARGET MCU
8

EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0
17
18 C537 8.00MHZ C534
INTERFACE
SHELL3

SHELL4

SIGNALS

2
6 XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1 22PF 22PF
P5V0_SDA_USB_CONN_VBUS U515 VREGIN
1 5 DNP DNP J23 1
SDA_USBSHIELD

VBUS 2 SDA_USB_CONN_DN 4 3 R617 33 SDA_USB_DN 4 VOUT33 DNP 2 Output to system

10 D- 3 SDA_USB_CONN_DP R618 33 SDA_USB_DP 3 USB0_DM HDR 1X2 TH from Level shifter
SHELL5 D+ 4 TC_SDA_USB_ID_TP 5 2 USB0_DP
ID 5 TP512
TS6
SHELL2

SHELL1

GND 6 1 C541 20 SDA_SWD_OE_B

ADC0_SE8/TSI0_CH0/PTB0/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/LLWU_P5 21 SDA_RST_TGTMCU_B SDA_RST_TGTMCU_J_B R295 0
2.2UF PTA5/TCLK1_2/RESET pag[2,3,4,9]

1
10 ADC0_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB
9 EXTAL32
DNP
7

XTAL32 P3V3_SDA V_TGTMCU

L501 TC_EXTAL_TP
TP508
1 2 TP509 TC_XTAL_TP U514
C 1 6 C
19 SDA_RX_EN 5 VCCA VCCB
330 OHM RESET DIR
UART1_RX_TGTMCU_R 3 4 UART1_RX_TGTMCU_BUF R627 0 UART1_RX_TGTMCU
A B PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 pag[3,9]
R305DNP 0 UART1_RX_TGTMCU
PTC8/LPUART1_RX pag[3,9]
P3V3_SDA
P5V_SDA 22 SDA_SPI0_RST_B TP57 R630 R631 2
2 ADC0_SE15/TSI0_CH14/PTC1/SPI0_PCS3/UART1_RTS/FTM0_CH0/I2S0_TXD0/LLWU_P6 23 SDA_SPI0_CS TP511 10.0K 4.7K GND

R615
4.7K TP510
VSS1 ADC0_SE4B/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS/FTM0_CH1/I2S0_TX_FS
CMP1_IN1/PTC3/SPI0_PCS1/UART1_RX/FTM0_CH2/I2S0_TX_BCLK/LLWU_P7
PTC4/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT/LLWU_P8
24
25
26
UART1_TX_TGTMCU_R
UART1_RX_TGTMCU_R
SDA_SPI0_SCK
74LVCH1T45 Isolation Output to system
from Level shifter

SDA_RST
PTC5/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/CMP0_OUT/LLWU_P9
CMP0_IN0/PTC6/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/I2S0_MCLK/LLWU_P10
CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS
27
28
SDA_SPI0_SOUT
SDA_SPI0_SIN P3V3_SDA V_TGTMCU
Resistors
P3V3_SDA U513
R612
10.0K 7 8
UART1_TX_TGTMCU_R 6 VCCA VCCB 1 UART1_TX_TGTMCU_BUF R620 0 UART1_TX_TGTMCU
PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 pag[3,9]

A
33 D10 R308 SDA_SPI0_SIN 5 1A 1B 2 R619DNP 0 UART1_TX_TGTMCU

SDA_LED_R
EPAD 2A 2B PTC9/LPUART1_TX pag[3,9]
220 4 3
LED GREEN GND DIR
PU/PD LOGIC:
SERIAL INTERFACE 74LVC2T45GM,125 Output to system
IS ALWAYS RESET from Level shifter

C
WHEN USB PORT
IS DISCONNECTED
29 SDA_LED P3V3_SDA V_TGTMCU
PTD4/SPI0_PCS1/UART0_RTS/FTM0_CH4/EWM_IN/LLWU_P14 30
ADC0_SE6B/PTD5/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/EWM_OUT 31 POWER_EN U512 SWD_DIO_TGTMCU_BUF R294 0603 SWD_DIO_TGTMCU JTAG
ADC0_SE7B/PTD6/SPI0_PCS3/UART0_RX/FTM0_CH6/FTM0_FLT0/LLWU_P15 VTRG_FAULT_B PTA4/CMP0_OUT/JTAG_TMS/SWD_DIO pag[3]
32 1 6 SWD_DIO_TGTMCU
PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1 SDA_SWD_OE R625 0 SDA_SWD_OE_R 5 VCCA VCCB
P5V_SDA DIR SWD_CLK_TGTMCU_BUF R298 0603 JTAG
SDA_SPI0_SOUT PTC4/FTM1_CH0/RTC_CLKOUT/JTAG_TCLK/SWD_CLK pag[3]
3 4
A B
R628 R626 R621
4.7K 10.0K 4.7K 2
DNP GND
SDA_USB_P5V_SENSE
74LVCH1T45
R629
MK20DX128VFM5 HW Designer: Rafael del Rey 10.0K OPEN SDA
DNP P3V3_SDA V_TGTMCU POWER OUTPUTS
U511 OPEN SDA
SDA_SWD_EN
R624
0 SDA_SWD_EN_R
1
5 VCCA VCCB
6 INPUT POWER SDA_VOUT33 P3V3_SW
DIR
P3V3_SDA
i path TP55 i path
SDA_SPI0_SCK 3 4 R291 0603
A B R288 0603 DNP Note: You can power openSDA
R623 R622 with your own power supplies
B 10.0K 4.7K 2 3.3VDC, 10mA should be provided by replacing this rail B
GND to this rail (P3V3_SDA) (SDA_VOUT33)
in order to power openSDA with your 3.3V power supply rail
74LVCH1T45 module SHORTING HEADER ON BOTTOM LAYER

Jumper is shorted by a cut-trace

on bottom layer. Cutting the trace
will effectively isolate the on-board
P5V_SDA
OpenSDA INTERFACE JTAG CONNECTOR Isolation and level shift stage
PU/PD LOGIC (DIR PIN):
MCU from the OpenSDA
debug interface.
BUFFER IS TRISTATED WHEN

P3V3_SDA C89 C103 (for 1.8 to 5V compatibility) P3V3_SDA IS UNPOWERED

TPAD49 i path
18PF U24 P5V_SDA_PSW
0.1UF DNP 1 6
R606 R605 R281 R607 R293 VIN VOUT
10.0K 10.0K 10.0K 10.0K PWR SWITCH 10.0K MIC2005_CSLEW
5 4 P3V3_SDA SDA_VOUT33 can provide up to 120mA
DNP DNP CSLEW FAULT of power at 3.3VDC to your system
J20 (To enable 5v from VTRG_EN 3 2
1 2 SDA_JTAG_TMS USB connector) ENABLE GND R301 V_TGTMCU P5V_TRG_SDA can provide up to 450mA
3 4 SDA_JTAG_TCLK R296 MIC2005-0.8YM6 (per USB spec) of power at 5VDC
10.0K to your system
C533 5 6 SDA_JTAG_TDO 15K ACTIVE HIGH
0.1UF 7 8 SDA_JTAG_TDI VTRG_FAULT_B C546
9 10 SDA_RST
4.7uF
HDR 2X5
R608 I/O POWER
10.0K POWER_EN R300 1.0K i path
V_TGTMCU TPAD54 VDD INPUT
V_BRD is supported
R299 0603 0 from 1.8V to 5V

3.3 V / 5.0V Power should be provided

MCU Reference to this rail for the logic
related to your platform I/O

SDA_SPI0_RST_B R292 0 SDA_SWD_EN

DNP
SDA_SPI0_CS R290 0 SDA_SWD_OE

DNP
{For enablement purposes only}

A A

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ____ IUO: X PUBI: ____

Designer: Drawing Title:
Jesus Sanchez
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez I/O HEADERS
Approved: Size Document Number Rev
Juan Romero D SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 5 of 11

5 4 3 2 1
 5 4 3 2 1

Mating conn = Samtec QTH series

Compatible Ethernet Daughter Card

----------------------------------
NXPU_MXEK
P3V3_SW TPAD28
L4 120OHM
1 2

C550 C549 J16

D 0603 D
R133 0 10UF 0.1uF QSH-030-01-L-D-A-K-TR

SH1 SH2
P3V3_ENET 1 2 R137 0603 0
PTD10/MII_RX_CLK pag[4,6]
3 4 R123 0603 DNP
PTD11/MII_RMII_TX_CLK pag[4,6]
TPAD25 5 6
R108 0402 DNP SPI_MOSI 7 8 R115 0402 33 OHM
pag[6] ENETSW_SPI_MOSI 0402 0402 PTD5/MII_TXD3 pag[4]
pag[6] ENETSW_SPI_SCK R98 DNP SPI_SCK 9 10 R111 33 OHM
11 12 PTD6/MII_TXD2 pag[4]
R94 0402 DNP SPI_CS 13 14 R109 0402 33 OHM
pag[6] ENETSW_SPI_SC PTD7/MII_RMII_TXD1 pag[4]
15 16 R102 0402 33 OHM
TPAD22 PTC2/MII_RMII_TXD0 pag[4]
17 18
TPAD19 ENET_MII_TXC
19 20 R96 0603 DNP
PTD10/MII_RX_CLK pag[4,6]
21 22 R514 0603 0
0402
PTD11/MII_RMII_TX_CLK pag[4,6]
TPAD18 23 24 R91 33 OHM PTD12/MII_RMII_TX_EN pag[4]
25 26
27 28 R81 0402 33 OHM
TPAD16 PTC17/MII_RMII_RX_DV pag[4]
29 30
R75 0402 DNP SPI_MISO 31 32 R79 0402 33 OHM
pag[6] ENETSW_SPI_MISO PTD10/MII_RX_CLK pag[4,6]
33 34
35 36 R74 0402 33 OHM PTC1/MII_RMII_RXD0 pag[4]
37 38 R63 0402 33 OHM PTC0/MII_RMII_RXD1 pag[4]
39 40
41 42 R62 0402 33 OHM
TPAD11 0402 PTD9/MII_RXD2 pag[4]
TPAD10 43 44 R58 33 OHM
PTD8/MII_RXD3 pag[4]
45 46
R61 0402 0 47 48 R46 0402 33 OHM
pag[4] PTC16/MII_RMII_RX_ER 0402 PTB4/MII_RMII_MDIO pag[4]
49 50 R38 33 OHM PTB5/ENET_MII_RMII_MDC pag[4]
51 52 R8 0402 33 OHM
0402
ENETSW_SDA pag[6]
53 54 R7 33 OHM ENETSW_SCL pag[6]
R55 0402 0 55 56 R5 0402 33 OHM
pag[4] PTC3/MII_TX_ER PTB20/FTM6_CH0/ENET_INT pag[4]
57 58 R2 0402 33
0402
ENETSW_INH pag[6]
59 60 R1 33 OHM ENETSW_RESET pag[4]
SH3 SH4
Ethernet Card RESET
VSUP P5V0 P3V3_SW TPAD4 TPAD1
P3V3_SW
C R41 0603 0 R501 0603 DNP C
R35 DNP 0

4
TPAD21 Y500
R6 0603 0 VDD C500
R3 DNP 0 R513 DNP 3 CLK OE 1 0.1UF
OUT
C547 C548 GND
0.1uF 0.1uF 50MHZ

2
VDD_MCU_PERH TPAD36 VDD_MCU_ENETSW P3V3_ENETSW TPAD31 P3V3_SW P5V0
3.3 V / 5.0V
MCU Reference L6 0603
R521 0
R522 0603 DNP
FER_BEAD 30 OHM
R179 0402 0 C28 C27 C517 C19 C18 C17
1000PF 0.1UF 0.1UF R156 0.1UF 0.1UF 1000PF 3.3 Volts
10K by Default
U3
R190 R188 R142 R144
10K 10K 10K 10K TPAD33 TPAD34
DNP DNP 1 8 DNP DNP
VCCA VCCB
ENET_SPI_MOSI R183 0402 0 SPI_MOSI 2 7
pag[3,9] PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 0402 A1 B1 ENETSW_SPI_MOSI pag[6]
pag[3,9] PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24
ENET_SPI_SCK R184 0 SPI_SCK 3 6 ENETSW_SPI_SCK pag[6]
A2 B2
4 5
B GND OE B

NTSX2102GU8H
U12
R207 R217 R201 R202
10K 10K 10K 10K TPAD37 TPAD13
ENET_SPI_CS0 R218 0402
DNP 0 DNP DNP 1 8 DNP DNP
pag[3,9] PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 ENET_SPI_CS1 0402 VCCA VCCB
R219 0
pag[3,8,9] PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4 ENET_SPI_CS2 0402 SPI_CS 2 7
R220 DNP 0 ENETSW_SPI_SC pag[6]
pag[3,9] PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 0402 A1 B1
pag[3,9] PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22
ENET_SPI_MISO R221 0 SPI_MISO 3 6 ENETSW_SPI_MISO pag[6]
A2 B2
4 5
GND OE

NTSX2102GU8H

U10
R178 R200 R185 R199
10K 10K 10K 10K TPAD5 TPAD3
1 8
VCCA VCCB
ENET_I2C_SDA R187 0402 0 2 7
pag[3,8,9] PTB10/FTM3_CH2/LPI2C0_SDAS 0402 A1 B1 ENETSW_SDA pag[6]
pag[3,8,9] PTB9/FTM3_CH1/LPI2C0_SCLS
ENET_I2C_SCL R192 0 3 6 ENETSW_SCL pag[6]
A2 B2
4 5
GND OE

NTSX2102GU8H
U505
R545 R539 R556 R551
10K 10K 10K 10K TPAD503
DNP 1 8
VCCA VCCB
R549 0402 0 2 7
pag[3,9] PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23 A1 B1 ENETSW_INH pag[6]
3 6
A2 B2
4 5
GND OE
A A

NTSX2102GU8H C523
Automotive Product Group
0.1UF 6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

ICAP Classification: CP: ____ IUO: X PUBI: ____

Designer: Drawing Title:
J.SANCHEZ
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez 07. ETHERNET
Approved: Size Document Number Rev
<Approver> C SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 6 of 11

5 4 3 2 1
 5 4 3 2 1

D D

CMOS FLASH Memory 64M-BIT

TPAD504
L500 P3V3_SW
VCC_HYPRFLASH
FER_BEAD 30 OHM
R574 0402 0
R575 C532
10.0K 10uF C531 C529

8
U508 0.1UF 1000PF

VCC
C C
ENET HYPFLASH R595 33 OHM HYPFLASH/QSPI_A_IO0 5
pag[4] PTD11/QSPI_A_IO0 SI/SIO0
HYPFLASH/QSPI_A_IO1

MX25L6433FM2R-08G
ENET HYPFLASH R585 33 OHM 2
pag[4] PTD7/QSPI_A_IO1 SO/SIO1
ENET HYPFLASH R590 33 OHM HYPFLASH/QSPI_A_IO2 3
pag[4] PTD12/QSPI_A_IO2 WP/SIO2
ENET HYPFLASH R586 33 OHM HYPFLASH/QSPI_A_IO3 7
pag[4] PTC2/QSPI_A_IO3 HOLD/SIO3
ENET HYPFLASH R581 33 OHM HYPFLASH/QSPI_A_CS 1
pag[4] PTC3/QSPI_A_CS CS
ENET HYPFLASH R591 33 OHM HYPFLASH/QSPI_A_SCK 6

GND
pag[4] PTD10/QSPI_A_SCK SCLK GND1

1
B B

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
J.SANCHEZ
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez 09. HYPERFLASH
Approved: Size Document Number Rev
<Approver> B SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 7 of 11

5 4 3 2 1
 5 4 3 2 1

D D

SAI Audio P5V0 P3V3_SW TPAD50 TPAD51

C104 C99 C113 C112

10uF 0.1uF 10uF 0.1uF

P1
1 2
pag[3,9] PTA14/FTM0_FLT0/FTM3_FLT1/SAI0_D3
SAI R329 33 OHMSAI0_DATA3 3 4
C C
SAI R328 33 OHMSAI0_DATA2 5 6
pag[3,9] PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/SAI0_D2 SAI R327 33 OHMSAI0_DATA1 7 8
pag[3,9] PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1
pag[3,9] PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0
SAI R326 33 OHMSAI0_DATA0 9 10
pag[3,9] PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK
SAI R325 33 OHMSAI0_BCLK 11 12
pag[3,9] PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC
SAI R324 33 OHMSAI0_SYNC 13 14
pag[3,9] PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK
SAI R323 33 OHMSAI0_MCLK 15 16
R322 33 OHM(ENET0_TMR0) 17 18
pag[3,9] PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT
R321 33 OHM(I2C_SCL3) 19 20
pag[3,9] PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16
pag[3,9] PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/FXIO_D0/ADC0_SE30 R320 33 OHM(I2C_SDA3) 21 22
pag[3,6,9] PTB9/FTM3_CH1/LPI2C0_SCLS
ENET_I2C_SCL R319 33 OHM(SAI1_DATA0) 23 24
pag[3,9] PTB8/FTM3_CH0/SAI1_BCLK R318 33 OHM(SAI1_BCLK) 25 26
R317 33 OHM(ENET1_TMR2) 27 28
pag[3,9] PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT
R316 33 OHM(SAI1_SYNC) 29 30
pag[3,9] PTE2/LPSPI0_SOUT/FTM3_CH6/SAI1_SYNC/ADC1_SE10
pag[3,6,9] PTB10/FTM3_CH2/LPI2C0_SDAS
ENET_I2C_SDA R315 33 OHM(SAI1_MCLK) 31 32
R314 33 OHM(I2C_SCL2) 33 34
pag[3,9] PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17
pag[3,9] PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31 R313 33 OHM(I2C_SDA2) 35 36
pag[3,9] PTE15/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2 R312 33 OHM(SAI2_DATA0) 37 38
pag[3,9] PTE16/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3 R311 33 OHM(SAI2_BCLK) 39 40
pag[3,6,9] PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4
ENET_SPI_CS1 R310 33 OHM(SAI2_SYNC) 41 42
pag[3,9] PTE11/FTM2_CH5/FXIO_D5 R309 33 OHM(SAI2_MCLK) 43 44
TRACE R332 33 OHM(ENET0_TMR2) 45 46
pag[3,9] PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2
R331 33 OHM(GPIO Control) 47 48
pag[3,9] PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3
49 50
B B
TSW-125-07-F-D

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
J.SANCHEZ
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez 10. SAI AUDIO
Approved: Size Document Number Rev
<Approver> B SCH-29559 PDF: SPF-29559 A

Date: Wednesday, July 12, 2017 Sheet 8 of 11

5 4 3 2 1
 5 4 3 2 1

PTD20/FTM6_CH1 pag[3]
PTD21/FTM6_CH2 pag[3]
PTB24/FTM6_CH4 pag[3]
PTB26/FTM6_CH6 pag[3]
PTB30/FTM7_CH2 pag[3]
PTB31/FTM7_CH3 pag[3]
D D

SAI
PTA13/FTM1_CH7/FTM2_QD_PHA/SAI0_D0 pag[3,8]
SAI
PTA14/FTM0_FLT0/FTM3_FLT1/SAI0_D3 pag[3,8]
PTE2/LPSPI0_SOUT/FTM3_CH6/SAI1_SYNC/ADC1_SE10 pag[3,8]
PTE3/FTM0_FLT0/FTM2_FLT0/CMP0_OUT pag[3]
PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11 pag[3]
PTE7/FTM0_CH7/FTM3_FLT0 pag[3]
PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3 pag[3]
PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3 pag[3,8]

PTE17/FTM7_CH5/FXIO_D5 pag[3]
PTE18/FTM7_CH6/FXIO_D4 pag[3]
PTB19/FTM5_CH7 pag[3]
PTE27/FTM4_CH7 pag[3]
PTE26/FTM4_CH6 pag[3]
PTA20/FTM4_CH2/LPSPI1_SIN pag[3]
PTA21/FTM4_CH3/FXIO_D0/LPSPI1_PCS0 pag[3]
pag[3] PTC18/FTM7_CH4 PTA22/FTM4_CH4/FXIO_D1/LPSPI1_PCS1 pag[3]
pag[3] PTC20/FTM7_CH6 PTA23/FTM4_CH6/FXIO_D2 pag[3]
pag[3] PTC21/FTM7_CH7/FTM7_FLT0 PTA24/FTM4_CH7/FXIO_D3 pag[3]
pag[3] PTC22/FTM7_FLT1
pag[3] PTC24/FTM4_CH0
pag[3] PTC25/FTM4_CH1
pag[3] PTC26/FTM4_CH3
pag[3] PTD25/FTM6_CH6 TRACE
pag[3] PTD26/FTM6_CH7/FXIO_D7 PTD0/FTM0_CH2/FTM2_CH0/TRACE_D0/FXIO_D0 pag[3]
pag[3] PTD31/FTM7_CH4/FXIO_D6/FTM6_FLT0 PTE14/FTM0_FLT1/FTM2_FLT1 pag[3]
PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0 pag[3,6]
PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0 pag[3]
PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2 pag[3,5]
pag[3,4] PTA25/FTM5_CH0 PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3 pag[3,5]
pag[3] PTA7/FTM0_FLT2 PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS pag[3]
pag[3,9] PTA6/FTM0_FLT1 PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS pag[3]
pag[3] PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16 VDD_MCU_PERH
pag[3,9] PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1
pag[3] PTB11/FTM3_CH3/LPI2C0_HREQ
ENET_SPI_CS1
pag[3,6,8] PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4
C2
pag[3,8] PTE11/FTM2_CH5/FXIO_D5
pag[3] PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX 0.1uF
pag[3] PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX

C C

VDD_MCU_PERH

30
29
27
26
24
23
21
20
18
17
15
14
12
11

24
23
21
20
18
17
15
14
12
11

30
29
27
26
24
23
21
20
18
17
15
14
12
11
9
8
6
5
3
2

9
8
6
5
3
2

9
8
6
5
3
2
J2 J1 J6
ESQ-110-33-T-T ESQ-108-33-T-T ESQ-110-33-T-T
R36 R37
10K 10K
DNP DNP

28

25

22

19

16

13

10

22

19

16

13

10

28

25

22

19

16

13

10

1
TPAD6 pag[3,8] PTE15/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2
pag[3,8] PTE16/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3
VREFH
pag[3] VREFH
GPIO/SCK
pag[3] PTB2/LPSPI0_SCK GPIO/MISO
C1
pag[3] PTB3/LPSPI0_SIN GPIO/MOSI
PTB20/FTM6_CH0/ADC0_SE17 pag[3,4]
0.1uF pag[3] PTB1/LPSPI0_SOUT PTB21/FTM6_CH1/ADC0_SE18 pag[3]
GPIO/SS
pag[3] PTB0/SBC_LPSPI0_PCS0 PWM
PTB10/FTM3_CH2/LPI2C0_SDAS pag[3,6,8]
pag[3] PTA30/FTM5_CH5 PWM RX
PTB9/FTM3_CH1/LPI2C0_SCLS pag[3,6,8]
pag[3] PTA31/FTM5_CH6 TX
PTA19/FTM4_CH1/LPUART1_RX/LPSPI1_SCK pag[3]
PTA18/FTM4_CH0/LPUART1_TX/LPSPI1_SOUT/FTM6_CH0 pag[3]
GND SPI2_MISO RX4
PWM PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16 pag[3,8]
SPI2_MOSI TX4
pag[3,8] PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT PWM TRACE PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17 pag[3,8]
SPI2_SCK RXD5
pag[3,8] PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2 PWM TRACE PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/ADC1_SE2 pag[3]
SPI2_SS TXD5
pag[3] PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/TRACE_CLKOUT PWM PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/ADC1_SE3 pag[3]
pag[3] PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1 PWM
pag[3] PTC10/FTM3_CH4/TRGMUX_IN11 PWM
pag[3] PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10
TX R39 0402 0
pag[2,3] PTA3/LPUART0_TX RX R40 0402
pag[2,3] PTA2/LPUART0_RX 0
R14 0402 DNP
pag[3,5] PTC9/LPUART1_TX 0402
pag[3,5] PTC8/LPUART1_RX R34 DNP

ADC
pag[2,3] PTE20/FTM4_CH0/FTM4_CH0/ADC1_SE26
ADC
pag[2,3] PTE19/FTM7_CH7/FTM7_CH7/ADC1_SE25
ADC
pag[3,8] PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/FXIO_D1/ADC0_SE31 ADC
pag[3,8] PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/FXIO_D0/ADC0_SE30 ADC
pag[3] PTC29/FTM5_CH2/FTM5_CH2/ADC0_SE29 ADC ADC
pag[3] PTC28/FTM4_CH7/FTM4_CH7/ADC0_SE28 ADC ADC PTE21/FTM4_CH1/FTM4_CH1/ADC1_SE27 pag[3]
pag[3] PTC27/FTM4_CH4/FTM4_CH4/ADC0_SE27 ADC ADC PTE22/FTM4_CH2/FTM4_CH2/ADC1_SE28 pag[3]
pag[3] PTC23/LPSPI0_SCK/ADC0_SE26 ADC PTE23/FTM4_CH3/FTM4_CH3/ADC1_SE29 pag[3]
TP52 TP53 TP6 ADC PTE24/FTM4_CH4/CAN2_TX/FTM4_CH4/ADC1_SE30 pag[3]
VBAT
ADC PTE25/FTM4_CH5/CAN2_RX/CAN2_RX/FTM4_CH5/ADC1_SE31 pag[3]
P5V0 P3V3_SW VDD_MCU_PERH PTC19/FTM7_CH5/ADC0_SE25 pag[3]
ADC
PTC14/FTM1_CH2/LPSPI2_PCS0/ADC0_SE12 pag[3]
TS13 TP50 ADC
PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9 pag[3]
ADC
0603 ADC
PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14 pag[3]
pag[2,3,4,5] PTA5/TCLK1_2/RESET R266 0 PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15 pag[3]
1

R267 0603 DNP

B
pag[3,4] PTA17/FTM0_CH6/ENET_RESET B
VBAT VBAT
C79 C85 C87
0.1uF 0.1uF 0.1uF C86 C82
0.1uF 0.1uF

10

13

16

19

22

10

13

16

19

22

11
13
15
17
19
1

1
3
5
7
9
J3 J4 J5
ESQ-108-33-T-T CON 2X10

ESQ-108-33-T-T

2
4
6
8
10
12
14
16
18
20
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24

2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT pag[3,8]
TP2 SAI
PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK pag[3,8]
SAI
SAI PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/SAI0_D2 pag[3,8]
VDD_MCU_PERH
PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/SAI0_D1 pag[3,8]

pag[3]PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20 SAI
pag[3]PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19 PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/SAI0_BCLK pag[3,8]
ENET_SPI_SCK SAI C88
pag[3,6] PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24 PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC pag[3,8]
ENET_SPI_MISO 0.1uF
pag[3,6] PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22 PTB8/FTM3_CH0/SAI1_BCLK pag[3,8]
ENET_SPI_MOSI
pag[3,6] PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23 PTC15/FTM1_CH3/LPSPI2_SCK/QSPI_B_CS pag[3]
ENET_SPI_CS0
pag[3,6] PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21 SBC_LIN2RX
pag[2,3] PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3 SBC_LIN2TX
pag[2,3] PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2

pag[2] LIN1_OUT
pag[2] LIN2_OUT

pag[2] CANH_OUT
pag[2] CANL_OUT

ADC
pag[3] PTD4/FTM0_FLT3/ADC1_SE6 ADC
pag[3] PTD22/FTM6_CH3/FTM6_CH3/ADC1_SE18 ADC
pag[3] PTD23/FTM6_CH4/FTM6_CH4/ADC1_SE19 ADC
pag[3] PTD24/FTM6_CH5/FTM6_CH5/ADC1_SE20 ADC
pag[3] PTD27/FTM7_CH0/FTM7_CH0/ADC1_SE21 ADC
pag[3] PTD28/FTM7_CH1/FTM7_CH1/ADC1_SE22 ADC
pag[3,6] PTD29/FTM7_CH2/FTM7_CH2/ADC1_SE23 ADC
pag[3] PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24
A A

R282 0402
DNP 0
pag[3,9] PTA6/FTM0_FLT1 0402
pag[3,9]
PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1 R287 0
pag[2,3] PTA26/FTM5_CH1/LPSPI1_PCS0 R283 DNP 0 SBC_SPI_CS
0402
SBC_SPI_MISO
pag[2,3] PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX SBC_SPI_CLK
pag[2,3] PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX SBC_SPI_MOSI
Automotive Product Group
pag[2,3] PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN 6501 William Cannon Drive West
pag[3] PTA0/ACMP0_IN0/ADC0_SE0 Austin, TX 78735-8598
pag[3] PTA1/ACMP0_IN1/ADC0_SE1
This document contains information proprietary to NXP and shall not be used for engineering design,
pag[3] PTA15/FTM1_CH2/ADC1_SE12
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
pag[3] PTA16/FTM1_CH3/ADC1_SE13
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Jesus Sanchez
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez I/O HEADERS
Approved: Size Document Number Rev
Juan Romero D SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 9 of 11

5 4 3 2 1
 5 4 3 2 1

D D

TPAD52

TOUCH
pag[3] TOUCH_ADC0_A
C108
4.7pF
Touch PADs
R330
4.7K

TPAD53
SW2

pag[3] TOUCH_ADC1_A R333 0 1

1
C C
Electrode

TPAD46

pag[3] TOUCH_ADC0_B
C78
4.7pF
R278
4.7K

TPAD47
SW1
TOUCH R280 0 1
pag[3] TOUCH_ADC1_B 1
Electrode

B B

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
J.SANCHEZ
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez 11. TOUCHPAD
Approved: Size Document Number Rev
<Approver> B SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 10 of 11

5 4 3 2 1
 5 4 3 2 1

D D

VDD_MCU_PERH
User buttons
P5V0 RGB LED SW3 EVQ-P2402W TP60 TP507

TP43 TP46 TP48 TP42 TP44 TP49 1 2 R306 PTC12/BTN0 pag[3]

D6 3 4 220

A1 C1 LEDRGB_REDR256 560
SW4 EVQ-P2402W TP61 TP506

A2 C2 LEDRGB_GREEN
R247 560 1 2 R307 PTC13/BTN1 pag[3]
3 4 220

A3 C3 LEDRGB_BLUE R229 560 C114 C115 R335 R336 C109 C110

0.1uF 0.1uF 10.0K 10.0K 0.1uF 0.1uF

LED RED/GRN/BL

C C
TPAD38

3
R222 10.0K 1 Q1
pag[3] LED_BLUE
MMBT3904TT1G
R228 33K

2
VDD_MCU_PERH 3.3 V / 5.0V
TPAD41 MCU Reference
Potentiometer
3
R161 0603 0
R245 10.0K 1 Q2
pag[3] LED_GREEN
MMBT3904TT1G

1
R248 33K 2 TS9 TP27

TPAD43 R186 2 R194 ADC_POT pag[3]

1
3

5K 220
R255 10.0K 1 Q3
pag[3] LED_RED
MMBT3904TT1G C49 C48

3
R257 33K 0.1uF 0.1uF
2

B B

Automotive Product Group

6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.
A A
ICAP Classification: CP: ____ IUO: X PUBI: ____
Designer: Drawing Title:
Jesus Sanchez
X-S32K148EVB-Q176
Drawn by: Page Title:
Jesus Sanchez USER PERIPHERALS
Approved: Size Document Number Rev
Juan Romero B SCH-29642 PDF: SPF-29642 A

Date: Wednesday, July 12, 2017 Sheet 11 of 11

5 4 3 2 1