Chittagong University of Engineering and Technology

Department of
Electrical and Electrical Engineering

EEE 490: VLSI Technology Sessional

Experiment No. # 2

Name of the Experiment:

To Create a layout View of the basic two input nand circuit from scretch

Prepared By

Student Name: Mozumdar Md. Samee Al Zaber

Student ID: 1502128
Group No.: 26
Student IDs of Group Members: 1502127, 1502128
Section: B2
Date of Experiment: 02/12/2019
Date of Report: 16/12/2019
Mozumdar Md. Samee Al Zaber 1502128

ABSTRACT

1)To create a layout view of two input NAND gate circuit.

KEYWORDS

1. NAND

2. cadence

3. analoglib

4. virtuoso

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Table of Contents
1 INTRODUCTION 5

2 THEORY 5
2.1 NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Layout of NMOS of NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Layout of PMOS of NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Metal connection Of series NMOS and Parallel PMOS layout . . . . . . . . . . . 7

3 TOOLS USED 8

4 CONCLUSION 8

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List of Figures
1 NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 NMOS of NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 PMOS of NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Metal Connection of Series and Parallel PMOS Layout. . . . . . . . . . . . . . . 7
5 Layout Of two Input NAND Gate Design. . . . . . . . . . . . . . . . . . . . . . . 7

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1 INTRODUCTION
In this experiment, we have used cadence virtuoso software to create a layout of nand gate.

• To login in to the Cadence Server shell and start the Cadence virtuoso software,

• To create a working library.

• To create series NMOS and parallel PMOS layout.

• To connect the metal and design the final layout of two input nand gate.

2 THEORY
In this simulation software, we have learnt how to chnages the size of the p-mos or n-mos
transistor size. We have performed this experiment using gdpk-90 technology. It means that
the channel length is 90nm.

2.1 NAND gate

Two p-mos are in parallel and two n-mos are in series. Fig 3. The figure is adopted from [1].

Figure 1: NAND Gate

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2.2 Layout of NMOS of NAND gate

Figure 2: NMOS of NAND gate

2.3 Layout of PMOS of NAND gate

Figure 3: PMOS of NAND gate

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2.4 Metal connection Of series NMOS and Parallel PMOS layout

Figure 4: Metal Connection of Series and Parallel PMOS Layout.

Figure 5: Layout Of two Input NAND Gate Design.

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3 TOOLS USED
In this experiment we used:

• cadence software

4 CONCLUSION
The objective of the experiment was to get familiar with the virtuoso design environment. In
the lab we practiced NAND gate Layout design.Using series NMOS and parallel PMOS two
input NAND gate layout has been designd properly.

References
[1] S. Brown,Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, Section 7.8, Ap-
pendix A, McGraw-Hill, 2007

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