Design a NAND gate using CMOS Design technology

Rishabh Soni(T19125)
CMOS Digital IC Design Practicum
IIT MANDI, Himanchal Pradesh, India
Instructor: Dr. Rahul Shrestha

Abstract- In this report, we have designed a NAND gate

with the help of the CMOS technology in Cadence Virtuoso
designing system using 130nm technology node. We made
the schematic diagram, symbol,and layout for NAND gate
with area is equal to 16.382um2 and performed the DC
analysis for the calculation of average power, peak power
dissipation and delay for both pre-layout and post-layout
configuration.
I. INTRODUCTION
The NAND gate generally has an output at high logic(1)
and its output goes to low logic(0) only when both the inputs
are high as we can see from the table 1.
Nand gate is one of the universal gate, as we can make any
logic gate using NAND gate. Truth table of NAND logic is
shown in table(I). The NAND gate is the complement of the Fig. 2. Schematic of NAND gate
AND gate logic.
Table 1. Truth Table of NAND gate A. Boolean Logic
A B OUT
The boolean expression for the NAND gate is given as
0 0 1
follows=A.B.
0 1 1
1 0 1 III. SIMULATION AND ANALYSIS
1 1 0
For the pre-layout analysis we made the schematic and
II. SYMBOL AND SCHEMATIC symbol of the NAND gate and then we have made the test
We have used static CMOS design technology for making bench for analysis of the NAND circuit. In the test bench we
the proposed NAND gate, to achieve full swing in the output put the symbol of the NAND gate which we have drawn and
and zero static power loss. We can see in the proposed applied some random input pattern as A and B for analyze the
schematic from fig(1) that two NMOS are connected in series output of the drawn symbol.
working as pull down network and two PMOS are connected
in parallel to each other working as pull up network of the A. Input, Output, and Power Plot
circuit. As shown in the figure 3 we have given the random
input pattern’s as A= 00111011 and B= 01101111, so that
according to the NAND logic we got the output= 11010100.
The waveforms sequence is A, B, OUT and power from top
to bottom in figure 3.
Table 2. Power Analysis
avg/peak power Pre Layout Post Layout
avg power(nW) 143.2 200.3
peak power(uW) 202.8 222.9
In the power plot in figure.3 whenever output goes from 1
Fig. 1. Symbol to 0 or 0 to 1 there is a power dissipation takes place in the
circuit, which is called as dynamic power dissipation.
After designing of schematic we have designed the symbol Table.2 shows the values of the peak and average power
for NAND gate in which we have provided the input, output, dissipation during pre layout and post layout simulation. Due
VDD and ground terminal as shown below. to the effect of the parasitic components in the post layout
 Post layout delay analysis described by the below fig and
table, which shows that there is an increase in the delay due
to the parasitic resistors and capacitors effect.

Fig. 3. Pre Layout Waveforms (Input,Output,Power,Energy)

simulation the peak and the average power dissipation is

increased.

B. Delay Analysis Fig. 5. Waveforms for post layout delay analysis

The transient output response for the given input pattern is

shown below in the fig.4. In this analysis we have calculated Table 4. Post-Layout Delay Analysis
the maximum and minimum low to high and high to low delay transition(A,B ) TpLH (ps) transition(A,B ) TpH L (ps)
for the designed NAND gate. (1,1)→ (0, 0) 9.8 (0,0)→ (1, 1) 26.4
(1,1)→ (0, 1) 15.2 (0,1)→ (1, 1) 21.7
(1,1)→ (1, 0) 17.7 (1,0)→ (1, 1) 24.3
IV. LAYOUT
By now, we have simulated the schematic of the NAND
gate in test-bench shown below.

Fig. 4. Waveforms for delay analysis

The important results of the delay analysis:

• when both A and B is going 1 to 0 then the output takes
minimum time to charge to Vdd.
• when both A and B is going 0 to 1 then output takes Fig. 6. Test-Bench
maximum time to discharge to ground.
• when AB (1,1) goes to (1,0) that takes maximum time to The next stage in the process of designing an integrated
charge output to Vdd. circuit chip is layout designing. Fig(7) shows the layout
• when AB (0,1) goes to (1,1) that takes minimum time to for the NAND gate. There are two ways of doing layout
discharge output to ground. designing, manual and automatic. Manual designing give us an
Below table shows the delay for all the expected low to high opportunity to make smaller layout in comparison to automatic
and high to low transitions in the output. designing but it is tedious and more time consuming process.
Whereas automatic designing is much faster than manual
Table 3. Pre-Layout Delay Analysis designing process.
transition(A,B ) TpLH (ps) transition(A,B ) TpH L (ps)
V. RESULT AND DISCUSSION
(1,1)→ (0, 0) 7.2 (0,0)→ (1, 1) 19.5
(1,1)→ (0, 1) 10.8 (0,1)→ (1, 1) 15.5 • The pre layout and post layout simulation of the NAND
(1,1)→ (1, 0) 13.4 (1,0)→ (1, 1) 18.4 gate has been done successfully.
 Fig. 7. Layout

• The area of the designed layout of NAND gate is

16.382um2 .
• Average and peak power dissipation for the NAND gate
circuit is calculated.
• Effect of the parasitic component in the circuit is ob-
served. It increases both the power dissipation and delay
of the circuit.
R EFERENCES
[1] Millmans, “Integrated electronics: Analog and Digital Circuist and sys-
tem,” second ed., apr 2011.
[2] Jan M. Rabaey, “ Digital inte. circuit, A Design prospective,” 2nd edi.,
2002.