THE NATIONAL INSTITUTE OF ENGINEERING -MYSURU

DEPARTMENT OF ELECTRONICS
AND COMMUNICATION

SEM: 7th A
SUB: CMOS VLSI SUBMITTED BY:
SUB CODE: EC0509 KESHAVAMURTHY L ( 4NI17EC111)

1. Inverter using FET

SCHEMATIC SIMULATION
Timing Diagram
LAYOUT SIMULATION
 The midpoint value is 0.59V, for the above design.

2. Basic Logic Gates (Any two)

 a. Two input NAND gate

Timing diagram
LAYOUT SIMULATION
 b. Two input NOR gate

Timing diagram
LAYOUT SIMULATION
 c. Two input XOR gate

Timing diagram

3. Boolean Functions

Example: F= (A' + B'C)

F = (A' + B'C)
= ((A' + B'C)')'
= (A (B'C)')'
= (A (B + C'))'
Timing Diagram

LAYOUT SIMULATION
4. Common Source Amplifier

LAYOUT SIMULATION
(In schematic simulation, only dc output can be viewed)
5. Common Drain Amplifier
LAYOUT SIMULATION

6. Differential Amplifiers
LAYOUT SIMULATION