Ajman University

College of Information Technology

Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (1): Introduction to Spice Simulation and Netlist

Background:

PSPICE:

OrCAD is a proprietary software tool suite used primarily for electronic design automation (EDA). The software is used
mainly by electronic design engineers and electronic technicians to create electronic schematics and electronic prints for
manufacturing printed circuit boards.

OrCAD PSpice is a SPICE circuit simulator application for simulation and verification of analog and mixed-signal
circuits.[16] OrCAD EE typically runs simulations for circuits defined in OrCAD Capture, and can optionally integrated
with MATLAB/Simulink, using the Simulink to PSpice Interface (SLPS).

PSpice is an acronym for Personal Simulation Program with Integrated Circuit Emphasis. A circuit to be analyzed using
PSpice is described by a circuit description file, which is processed by PSpice and executed as a simulation. PSpice
creates an output file to store the simulation results, and such results are also graphically displayed within the OrCAD EE
interface.

OrCAD is an upgraded version of the PSpice simulator, and includes automatic circuit optimization and support for
waveform recording, viewing, analysis, curve-fitting, and post-processing. OrCAD contains an extensive library of models
for physical components, including around 30,000 analog and mixed-signal devices and mathematical functions. OrCAD
also includes a model editor, support for parameterized models, auto-convergence and checkpoint restart, several
internal solvers and a magnetic part editor.

Netlist:

In electronic design, a netlist is a description of the connectivity of an electronic circuit. A single netlist is effectively a
collection of several related lists. In its simplest form, a netlist consists of a list of the terminals ("pins") of the electronic
components in a circuit and a list of the electrical conductors that interconnect the terminals. A net is a conductor that
interconnects two or more component terminals.

The structure, complexity and representation of netlists can vary considerably, but the fundamental purpose of every
netlist is to convey connectivity information. Netlists usually provide nothing more than instances, nets, and perhaps
some attributes. An "instance" could be anything from a MOSFET transistor or a bipolar transistor, to a resistor,
capacitor, or integrated circuit chip. If they express much more than this, they are usually considered to be a hardware
description language such as Verilog or VHDL, or one of several languages specifically designed for input to simulators.
The following code shows the equivalent netlist description of the given circ uit. The circuit file (.cir) have the following
structure:

 Title as comment in the beginning.

 Netlist Description: describe the components as elements between nodes.
 Spice commands.
 End on file.

9k

1k

* RRC Circuit (This is a comment, and must have one in the beginning)
* Text after * or ; is described as comment

*Netlist Description
V1 1 0 10V ; Label +ve -ve value(with unit without space)
R1 1 2 9k ; better specified it according to direction of the current
R2 2 0 1k
C1 2 0 1u
; (node 0) is always had to be specified as the ground

*Spice Commands
;
;

*End of file
.END
Exercises:

PART (1):
Use OrCAD PSpice to simulate the following code:
* RRC Circuit

*Netlist Description
V1 1 0 10V
R1 1 2 {Rval} ; use parameter instead of direct value
R2 2 0 1k
C1 2 0 1u

*Spice Commands

.PARAM Rval 9k ; define a parameter

;generate linearized parameters for nonlinear sources

.OP

*End of file
.END
Run the simulation then open the output file and find the following:
1. Voltage at Node (1)
2. Voltage at Node (2)
3. Current of Voltage Source.
4. Total power dissipation

PART (2):
Add the following command after the (.OP) command:
;DC sweep analysis over a range of values for V1; LIN for Linear; for Logarithmic reading must not start with 0
.DC LIN V1 0V 10V 0.1V

;Writes results of DC, AC, and transient to a output file

.PRINT DC V(2) I(R1) V(1,2)

Run the simulation then open the output file:

1. Find the change in Voltage over range of values for V1 from 0V to 10V, with increment value of (0.1V) for the
following: Voltage at node (2), Current through (R1) and Voltage between node (1) and (2).
2. Modify the code to find the value of current and voltage over R1 and R2. Start change in V1 from 0 to 5 with
increment value of (1V)
3. Use the data in the previous step to calculate the Power over R1 and R2.
PART (3):
Erase the commands of step 2, and add the following command after the (.OP) command:
;DC sweep analysis over a range of values for V1; LIN for Linear; for Logarithmic reading must not start with 0
.DC LIN V1 0V 10V 0.1V

;Writes results of DC, AC, and transient to a data file

.PROBE

Run the simulation then open the data file (.PROBE will open it):
1. Add traces for V(1,2) and V(2,0). And find if the voltage divider is implemented.
2. Remove the previous traces, then add traces for I(R1) and I(R2). How the Spice deal with the capacitor?

PART (4):
Erase the commands of step 3, and add the following command after the (.OP) command:
;DC sweep analysis over a range of values for V1; DEC for decade; for Logarithmic reading must not start with 0
.DC DEC V1 0.1V 100V 5V

;Writes results of DC, AC, and transient to a data file

.PROBE

Run the simulation then open the data file (.PROBE will open it):
1. Add traces for V(2), and mark data points.
2. Change the X-Axes to Log scale instead of Linear Scale.
3. Define your results.

PART (5):
Erase the commands of step 4, and add the following command after the (.OP) command:
;DC sweep analysis over a range of values for R1 value
;DEC for decade; for Logarithmic reading must not start with 0
.DC DEC PARAM Rval 1 100K 10

;Writes results of DC, AC, and transient to a data file

.PROBE

Run the simulation then open the data file (.PROBE will open it):
1. Add traces for V(1, 2).
2. Change the X-Axes to Log scale instead of Linear Scale.
3. Find how the (Toggle Curser) works, and define your observation.
PART (6):
Write the following code:
* RRC Circuit

*Netlist Description
V1 1 0 10V
R1 1 2 {R1val} ; use parameter instead of direct value
R2 2 0 1k
C1 2 0 1u IC=0 ; initial condition

*Spice Commands

.PARAM R1val 9k ;define a parameter

;Generate linearized parameters for nonlinear sources

.OP

;Transient analysis on circuit over time period

;.TRAN [Print Step] [Final Time] [No Print Time] [Max Step Time]
.TRAN 1m 5m 0

;Writes results of DC, AC, and transient to a data file

.PROBE

*End of file
.END

Run the simulation then open the data file (.PROBE will open it):
1. Add traces for V(2), and set the X-Axes to Linear Scale.
2. Use the (Toggle Curser) and define your observation.

PART (7):
Add the following command before the (.OP) command:
; .STEP command performs a parametric sweep for all of the analyses of the circuit.
; .STEP [sweep variable name] LIST [values separated by space]
.STEP PARAM R1val LIST 1k 2k
Run the simulation then open the data file (.PROBE will open it):
1. Use the (Section Information) and define your observation over the V(2).

PART (8):
Erase the commands of step 6, and add the following command before the (.OP) command:
; .STEP command performs a parametric sweep for all of the analyses of the circuit.
;.STEP [sweep variable name] [Start Value] [Final Value] [Step Value]
.STEP PARAM R1val 1k 10k 2k
Run the simulation then open the data file (.PROBE will open it):
1. Use the (Section Information) and define your observation.
 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (2): Diode-Resistor Logic (DRL) Gates

Objectives

• To be fa iliar with the operatio of diode-resistor logic circuits.

Background:

Diode-resistor logic:

The diode-resistor logic circuits consist of diodes and resistor only, the logic functions available are AND, OR, level-
shifted AND, and level-shifted OR.

AND Gate:

Figure (2a) illustrates the diode-resistor AND gate. The output voltage can be represented in the truth table, 1 for input
high, 0 for input low .

Figure 2a
If any of the input is low, the corresponding diode is allowed to conduct, and
Vout = VD + Vin ,VD = 0.7V
IR = (VCC – Vout) / R

If the two inputs are high, the diodes are off and
Vout = Vcc.
IR = 0
OR Gate:

Figure (2b) illustrates the diode-resistor OR gate. The output voltage can be represented in the truth table, 1 for input
high, 0 for input low .

Figure 2b
If any of the input is high, the corresponding diode is allowed to conduct, and
Vout = Vin - VD ,VD = 0.7V
IR = Vout / R

If the two inputs are low, the diodes are off and
Vout = 0.
IR = 0.

Level-Shifted AND Gate:

A level-shifting diode D has been added to the diode-resistor AND gate as in figure (2c).
If any input is low, its corresponding diode is conducting, and the output voltage
Vout = Vin + VD1 – VD = Vin.
If both VA and VB is < -VEE, the diodes D1,D2 are off, and the output voltage
Vout = V(out low) = -VEE
For all inputs are high (> VCC)
ID = (Vcc + VEE – VD) / (2*R)
Vout = V(out high) = -VEE + ID*R

Level-Shifted OR Gate:

A level-shifting diode D has been added to the diode-resistor OR gate as in figure (2d).
If any input is high, its corresponding diode is conducting, and the output voltage
Vout = Vin + VD1 – VD = Vin
If both VA and VB is > VCC, the diodes D1,D2 are off, and the output voltage
Vout = V(out high) = VCC
For all inputs are low (< -VEE)
ID = (Vcc + VEE – VD) / (2*R)
Vout = V(out low) = VCC + ID*R
 Figure 2c Figure 2d

Exercises:
PART (1)
Write the following code which is spice netlist simulation for figure (1b), then:

1. Investigate the following truth table, by changing * DRL AND

the value of Va and Vb: *Netlist Description
Va Vb Vout (Value) Vout (Logic) Vcc 1 0 5V
0 0 .7521 VOL R1 1 2 500
0 (0V) 1 (5V) Va 3 0 0V
1 (5V) 0 (0V) Vb 4 0 5V
1 (5V) 1 (5V) ; implement the Diode [Name] [Start] [End] [Model Name]
Da 2 3 Dx
2. From the code, set Vb = 5V, remove the comment Db 2 4 Dx
sign before the .DC , .PRINT and .PROBE :
a. Prove the DRL AND gate characteristics. *Spice Commands
b. ;Generate linearized parameters for nonlinear sources
.OP

;Define the diode model

.model Dx D (Is=1e-15)

;DC sweep analysis over a range of values for Va

; .DC LIN Va 0V 10V 0.5V

;Writes results of DC, AC, and transient to a output file

;.PRINT DC V(2) I(R1)

;Writes results of DC, AC, and transient to a data file

;.PROBE

*End of file
.END
PART (2)
Write the following code which is spice netlist simulation for figure (1b), then:
1. Investigate the following truth table, by changing * DRL OR
the value of Va and Vb: *Netlist Description
Va Vb Vout (Value) Vout (Logic) R1 1 0 500
0 0 Va 2 0 0V
0 (0V) 1 (5V) Vb 3 0 0V
1 (5V) 0 (0V) ; implement the Diode [Name] [Start] [End] [Model Name]
1 (5V) 1 (5V) Da 2 1 Dx
Db 3 1 Dx
2. From the code, set Vb = 0V, remove the comment
sign before the .DC , .PRINT and .PROBE : *Spice Commands
a. Prove DRL OR gate characteristics.
b. ;Generate linearized parameters for nonlinear sources
.OP

;Define the diode model

.model Dx D (Is=1e-15)

;DC sweep analysis over a range of values for Va

;.DC LIN Va 0V 10V 0.5V

;Writes results of DC, AC, and transient to a output file

;.PRINT DC V(1) I(R1)

;Writes results of DC, AC, and transient to a data file

;.PROBE

*End of file
.END

PART (3):
As a homework exercise change the code in part (1) and (2) to test the Level-Shifted Gates (AND, OR) and prove:

Level-Shifted AND Gate Characteristics: Level-Shifted OR Gate Characteristics:

 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (3): BJT Gates

Objectives

• To be fa iliar ith the operatio of BJT A plifier.

• To deter i e VTC of the i erter.

Background:

Ideal Inverter Digital Gate

The ideal Inverter model is important because it gives a metric by which we can judge the quality of actual
implementation. Infinite gain in the transition region, and gate threshold located in the middle of the logic swing, with
high and low margins equal to the half of the swing. The input and output impedance of the ideal gate are infinity and
zero, respectively.

Dynamic Behavior of Inverter Digital Gate

There are three regions for the above voltage transfer characteristic

1. Cut-off region: Vin < VBE(ON) (0.7)  IC ≈ 0  Vout = VOH = VCC

VIL = 0.7 VOH = VCC
2. Forward Active region: VBE(ON) (0.7) < Vin < VBE(SAT) (0.8)  IC = β IB  Vout = VCC - IC RC
3. Saturation region: Vin > VBE(SAT) (0.8)  IC = (VCC - VCE(SAT) (0.1))/ RC  Vout = VOL = VCE(SAT) = 0.1

VOL = VCE(SAT)
Metrics:

 A measure of sensitivity to noise is called Noise Margin (NM) which can be expressed by:
o NML = VIL – VOL.
o NMH = VOH – VIH.
 Between the two levels the transistor is in the active region, output level is not uniquely determined, where
because of the loose control on the transistor parameters. This cab defined as Transition Width (TW) and can be
expressed by:
o TW = VIH - VIL
 The difference between the two output voltage levels is defined as Logic Swing (LS) and can be expressed by:
o LS = VOH - VOL

Propagation Delay:

For an AC input, the propagation delay can be defined as:

 TPHL: the response from a low to high transition

 TPLH: the response from a high to low transition.
 TP: Overall propagation delay = (TPHL + TPLH)/2.
 TR: Rising Time.
 TF: Falling Time.
Exercises:
Exercise (1):
* Bipolar Transistor Gate
*Netlist Description
Vcc 3 0 5V
Rc 3 2 1k
Rb 4 1 10k
Q1 2 1 0 my-npn ; Q<name> <nc> <nb> <ne> <model-name>
Vin 4 0 0V

*Spice Commands
;Generate linearized parameters for nonlinear sources
.OP
;Define the transistor BJT model
.MODEL my-npn npn ( BF = 175 IS=1e-17 VA=75 BR=2 )
;DC sweep analysis over a range of values for Va
.DC LIN Vin 0V 5V 0.1V
;Writes results of DC for the Ic and Vout to a output file
.PRINT DC V(2)
;Writes results of DC for the Vout to a data file
.PROBE
*End of file
.END

Use the spice code above with corresponding to the netlist description, then find the following:
SPICE Theoretically
IC (Cut-off)

IC (Forward)

IC (Sat)
VIL

VIH
VOL

VOH

NML

NMH

TW
LS

Note: you may need to modify the SPICE Code (.PRINT) or add Trace to find your results.
Exercise (2):
* Bipolar Transistor Gate

*Netlist Description
Vcc 3 0 5V
Rc 3 2 1k
Rb 4 1 10k
Q1 2 1 0 my-npn ;Q<name> <nc> <nb> <ne> <model-name>
;type=pulse v1=<float> v2=<float> td=<float> tr=<float> tf=<float> pw=<float> per=<float>
Vs 4 0 AC 1 PULSE(0V 5V 1ms 0us 0s 5ms 8ms)

*Spice Commands
;Generate linearized parameters for nonlinear sources
.OP
;Define the transistor BJT model
.MODEL my-npn npn ( BF = 175 IS=1e-17 VA=75 BR=2 )
;Transient analysis on circuit over time period
;.TRAN [Print Step] [Final Time] [No Print Time] [Max Step Time]
.TRAN 1u 8.5ms 0
;Writes results of DC for the Vout to a data file
.PROBE
*End of file
.END

Write the spice code above with corresponding to the netlist description. The SPICE code is for a circuit which include an AC square
wave voltage source that described as:
type=pulse v1=<float> v2=<float> td=<float> tr=<float> tf=<float> pw=<float> per=<float>
Vs 4 0 AC 1 PULSE(0V 5V 1ms 0us 0s 5ms 8ms)

Find the following:

TPHL

TPLH

TP

TR

TF
 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (4): Resistor Transistor Logic (RTL)

Objectives
 Calculate the RTL NAND Gate Fan-in.
 Calculate the Basic RTL Fan-out.
 Calculate the RTL Power Dissipation.
 Calculate the RTL with Active Pull-Up and compare it with the Basic RTL fan-out.

Background:

The RTL NAND Gate Fan-in:

For the RTL inverter (Figure 4-1):

VIL= VBE(FA) , VOL = N * VCE (Sat)  N * VCE (Sat) < VBE (FA) 

RTL Fan-out:

From Figure 4-2:

IRC = N * IBi 

At maximum Fan-out: Vout = VIH = VBE(sat) + IRB * RB = VBE(sat) + IRC / βF * RB 

RTL Power Dissipation:

No Load (RB) ICC(OH) = 0

With Load (N of RB)

 Figure 4.1 Figure 4.2

Fan-out of RTL with Active Pull-Up:

As shown in Figure (4.3), Maximum fan-out occurs when

VOH(min) = VIH =

Fan-out with active pull-up:

Figure 4.3
Exercises:
Exercise (1):
What is the maximum fan-in for the basic RTL NAND gate of figure 4.1, if all stack BJTs have VCE(SAT) = 0.17 V and all load
gates have VBE(FA) = 0.7V?

Exercise (2):
What is the maximum fan-out for the basic RTL gate with VCC = 5 V, RB = kΏ, RC = kΏ, βF = 25, VBE(SAT) = 0.8 V, and
VCE(SAT) = 0.2 V?

Exercise (3):
Find the average power in a basic RTL inverter with:
a- No load.
b- A fan-out of 1.
c- A fan-out of 2.
Use VCC = 5 V, RB = kΏ, RC = kΏ, βF = 25, VBE(SAT) = 0.8 V, and VCE(SAT) = 0.2 V.

Exercise (4):
Compare the maximum fan-out for the RTL inverter with active pull-up (figure 4.3) with that of basic RTL obtained in
Exercise (2). Use VCC = 5 V, RBP = RBs = RBO = kΏ, RC = kΏ, βF = 25, VBE(SAT) = 0.8 V, VCE(SAT) = 0.2 V, and RCP = Ώ.
Assignment:
Write both SPICE codes to compare between Basic RTL and Active Pull-up in term of Noise Margin, Transition Width, and
Logic Swing.

*RTL Basic *RTL Active Pull-up

Vcc 3 0 DC 5V Vcc 7 0 DC 5V
Vin 1 0 DC 0V
Vin 4 0 DC 0V
Rbs 1 2 10k
Rb 4 1 10k Rbo 1 3 10k
Rc 3 2 1k Rbp 6 5 10k

Q1 2 1 0 Qnpn Rc 7 6 1k

Rcp 7 8 100
.MODEL Qnpn npn (BF= 25 CJC=2PF CJE=4PF)
Qs 6 2 0 Qnpn
.DC Vin 0V 5V 0.1V Qp 8 5 4 Qnpn
Qo 4 3 0 Qnpn
;PLOT at V(2) by add trace
.PLOT DC V(4) .MODEL Qnpn npn (BF= 25 CJC=2PF CJE=4PF)
.PROBE
.DC Vin 0V 5V 0.1V
.END
;PLOT at V(4) by add trace
.PLOT DC V(4)
.PROBE

.END
 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (5): Diode Transistor Logic (DTL)

Objectives
 Calculate the VTC of Basic DTL Inverter.
 Calculate the VTC of Modified DTL Inverter.
 Calculate the Fan-out of Modified DTL Inverter.
 Calculate the Power Dissipation of Modified DTL Inverter.

Background:

Basic DTL Inverter:

Vout= VCC – IRC * RC

If Vin= 0, DI is forward biased, Vx= VD,I(ON). However, this is not enough to turn on both DL and QO. Therefore, they both
will be off  IC,O= 0.  IRC= 0  Vout = VOH = VCC

If Vin is high enough, DI, DL and QO will all be on. Eventually, QO will saturate  Vout= VOL= VCE,O(Sat)

VIL is the input voltage that causes QO to switch from cut-off to forward active.
QO needs VBE(FA) between its base and emitter to switch on. VX= VD,L(ON) + VBE(FA)
Since Vin= VX–VD,I(ON)  Vin= VIL = VBE(FA)

VIH is the input voltage that causes QO to saturate.

QO needs VBE(Sat) between its base and emitter to saturate  Vin = VBE(Sat) + VD,L(ON) –VD,I(ON)  VIH= VBE(Sat)
Modified DTL Fan-out:

FA

SAT
Power Dissipation:

Exercises:
Exercise (1):
Define the VTC of the circuit in Figure (5.1), assume: V D(ON) = 0.7 V, VBE(FA) = 0.7 V, VBE(SAT) = 0.8 V, and
VCE(SAT) = 0.2 V.

Exercise (2):
Define the VTC of the circuit in Figure (5.2), assume: V D(ON) = 0.7 V, VBE(FA) = 0.7 V, VBE(SAT) = 0.8 V, and
VCE(SAT) = 0.2 V.

Figure (5.1) Figure (5.2)

Exercise (3):
Calculate the Fan-out for the DTL inverter of Figure (5.3). Assume: βF = 49, VBE(SAT) = 0.8 V, VBE(FA) = 0.7 V,
VCE(SAT) = 0.2 V, VD(ON) = 0.7 V, and σOL = 0.85 for output low state.

Figure (5.3)

Exercise (4):
Calculate the Power Dissipation from Exercise (3).

Assignment:
Write the SPICE code to find the VTC of the modified DTL inverter, compare it with Exercise (2), and find the
Noise Margin, Transition Width, and Logic Swing.

*DTL Mod Inv

VCC 7 0 DC 5V
VIN 1 0 DC 5V
RB1 7 3 1.75k
RB2 3 2 2k
RC 7 6 6k
RD 5 0 5k
DI 2 1 Diode
DL 4 5 Diode
.Model Diode D(CJO=0.5PF)
QL 3 2 4 QNPN
QO 6 5 0 QNPN
.Model QNPN NPN(BF=49 CJC=2PF CJE=4PF)
.DC VIN 0V 5V 0.01V
.Probe
.END
 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (6): Transistor-Transistor Logic (TTL)

Objectives
 Calculate the VTC of Basic TTL Inverter.
 Calculate the VTC of Standard TTL Inverter.
 Calculate the Fan-out of Standard DTL Inverter.
 Calculate the Power Dissipation of Standard DTL Inverter.

Background:

Basic TTL Inverter:

QO is cutoff for low Vin  Vout = VOH = VCC

QO is saturation for high Vin  Vout= VOL= VCE,O(Sat)

As VIN is increased, QO turns in when VIN reaches  Vin= VIL = VBE,O (FA) – VCE,I (SAT)

The input voltage for which QO just saturates  VIH= VBE,O (SAT) – VCE,I (SAT)

Figure 6.1
Standard TTL:

VOH: Output breakpoint Voltage VIB

VIL: VIH:

Input breakpoint Voltage VIB VOL:

Figure 6.2
Standard TTL Fan-out:

Figure 6.3
Power Dissipation of Standard TTL:

Exercises:
Exercise (1):
Define the VTC of the circuit in Figure (6.1), assume: VBE(FA) = 0.7 V, VBE(SAT) = 0.8 V, and VCE(SAT) = 0.2 V.

Exercise (2):
Define the VTC of the circuit in Figure (6.2), assume: VD(ON) = 0.7 V, VBE(FA) = 0.7 V, VBE(SAT) = 0.8 V, and
VCE(SAT) = 0.2 V.

Exercise (3):
Calculate the Fan-out for the TTL inverter of Figure (6.3). Assume: βR= 0.1, βF= 25, VBE(SAT) = 0.8 V, VBE(FA)=
VBE(RA) = 0.7 V, VCE(SAT) = 0.2 V, VD(ON) = 0.7 V, and σOL = 0.85 for output low state.

Exercise (4):
Calculate the Power Dissipation from Exercise (3).

Assignment:
Rewrite the SPICE code in the tutorial 5, to find the VTC of the Standard TTL inverter, compare it with Exercise
(2), and find the Noise Margin, Transition Width, and Logic Swing.
 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (7): Schottky Transistor-Transistor Logic (STTL)

Objectives
 Calculate the VTC of STTL.
 Calculate the Fan-out of STTL.
 Calculate the Power Dissipation of STTL.

Background:

STTL Gate:

Trasistor Status
VTC Equation
QI QS QP QP2 QD QO
VOH HARD OFF FA FA OFF OFF
VOL HARD HARD FA OFF HARD HARD
VIH HARD HARD FA OFF HARD HARD
VIL HARD EOC EOC EOC OFF OFF

Figure 1

STTL Fan-out:
STTL Power Dissipation:
Exercises:
Exercise (1):
Find the logic swing of the following figure, assume: VCE (HARD) = 0.5 V. And Define the difference with the
Basic TTL.

Exercise (2):
Find the VTC of figure 1, assume: VCE (HARD) = 0.5 V, VBE (FA) = 0.7 V, VBE (HARD) = 0.8 V

Exercise (3):
Find the Fan-out of the circuit in the figure 1, assume: VCE (HARD) = 0.5 V, VBE (FA) = 0.7 V, VBE (HARD) = 0.8 V,
VBC(RS) = 0.3, βF = 49

Exercise (4):
Find the power dissipation of the circuit in the figure 1, assume: VCE (HARD) = 0.5 V, VBE (FA) = 0.7 V, VBE (HARD)
= 0.8 V, VBC(RS) = 0.3
 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (8): MOSFET

Objectives
 MOSFT Overview.
 Modes of Operation.
 Drain Current.
 Power Dissipation.

Background:
Power Dissipation:

PDynamic = Power during switching = CL . v .VDD2

PStatic = Power during static case = VDD . ( IDD(OH) + IDD(OL) ) / 2
Ptotal(avg) = PDynamic + PStatic

Parameter Meaning
VT Threshold Voltage
W Width of the semiconductor
L Length of the semiconductor
μ Free charge mobility
Cox Oxide Capacitance per Unit Area
Ɛox Permittivity of SiO2
tox Thickness of gate oxide
K’ Process trans conductance parameter
K Device trans conductance parameter
CL Total load capacitance
v Switching frequency

Exercises:
Exercise (1):
Calculate the power dissipated due to switching and that due average current for the output high and low
states. Consider an NMOS inventer with VDD = 5 V, v = 0.5 MHz, CL = 10 pF , IDD OH = 5 μA, IDD OL = μA

Exercise (2):
Calculate the drain current for the edge of saturation using both the linear and saturation drain current expressions of
the NMOS transistor with the following: VGS = V , VDS = V , VT = V , W = μ , L = 5 μ , K’ = μA/V2

Exercise (3):
Repeat uestio with L = μ ,W=5μ , and discuss the difference.

Exercise (4):
Repeat uestio with L = 5 μ ,W=5μ , a d discuss the diffe e ce.
 Ajman University
College of Information Technology
Computer Engineering
Digital Integrated Circuits (312440)

Tutorial (9): MOSFET SPICE

Exercise (1):

*inverter
M1 2 1 0 0 NMOS1 L=1.5u W=3u
R1 3 2 20k
Vdd 3 0 dc 5
Vin 1 0 dc 0
.MODEL NMOS1 NMOS LEVEL=2 LD=0.15U
TOX=200E-10
.dc Vin 0 5 0.1
.PROBE V(2)
.end

Find the VTC for the previous Netlist?

Exercise (2):
* VTC FOR CMOS INVERTER
VIN 2 0 DC 0V
VDD 1 0 DC 5V
MP 3 2 1 1 CMOSP W=5U L=1U
MN 3 2 0 0 CMOSN W=2U L=1U
.DC VIN 0 5 0.05
.MODEL CMOSP PMOS KP=1.0E-5 VTO=-1.0 LAMBDA=0.05
.MODEL CMOSN NMOS KP=2.5E-5 VTO=1.0 LAMBDA=0.05
.PROBE V(3)
.END

Find the VTC for the previous Netlist?