Memory

1
 Memory

° SRAM : Static Random Access Memory

• No refresh (6 transistors/bit vs. 1 transistor)

° DRAM : Dynamic Random Access Memory

• Dynamic since needs to be refreshed periodically (8 ms)

6-Transistor SRAM Cell Static RAM Cell

word
0 1 (row select) word

0 1

bit bit
bit bit
° Write:
1. Drive bit lines (bit=1, bit=0)
2.. Select row
° Read:
1. Precharge bit and bit to Vdd or Vdd/2 => make sure equal!
2.. Select row
3. Cell pulls one line low
4. Sense amp on column detects difference between bit and bit
 Simple CMOS Memory Circuits: The SRAM Cell

• Circuit Schematic: sometimes

– 4 N-FETs and 2 P-FETs: T1 & T2 called active devices; called loads.
T3 & T4 calld the I/O devices; T5 & T6 sometimes I/O devices
called loads.
– The cell is comprised of two cross-coupled inverters B0 B1
(positive feedback). Vdd
– 2 vertical lines (bit lines B0 & B1) are used for sensing
state of cell and writing data in the cell T5 T6
– 1 horizontal line (word line WL) is used to select a row T4
T3 X0
X1
of cells for writing or reading and to prevent the
unselected rows of cells from being disturbed. T1 T2

• Circuit Operation:
– The cell has two stable states: “0” and “1” WL
• “0” State = Node X0 high and Node X1 low; T2 &
T5 are ON, T1 & T6 are OFF.
• “1” State = Node X1 high and Node X0 low; T1 &
active devices
T6 are ON; T2 & T5 are OFF.
• No dc current flows in either state.
– Read: raise WL to Vdd; pull one bit line high & pull the
other bit line low two cross-coupled inverters
– Write: raise WL to Vdd; precharge bit lines to ½ Vdd
Simple CMOS Memory Circuits: The SRAM Cell
 Simple CMOS Memory Circuits: The SRAM Array

• READ Operation:
– Word Decode circuitry selects one of n Data In

word lines and drives high to Vdd (say Bit

Addr
WL2); other word lines held at gnd.
Bit Decode (Column Decode)
Word and Write Drivers

– Bit Lines all precharged to half Vdd

Addr

– Selected cell’s I/O devices turned ON SRAM

Cell
SRAM
Cell
SRAM
Cell

and apply a DV to bit line pair 11 12 13

– Sense amp triggers on bit line DV and SRAM SRAM SRAM

Word
stores read data “0” or “1” Decode
Cell
21
Cell
22
Cell
23

•
(Row
WRITE Operation: Decode)
SRAM SRAM SRAM
– Selected WL is driven high to Vdd by Cell
31
Cell
32
Cell
33
word decode circuitry turning ON I/O
devices in selected cells
– Selected bit column has one BL pulled
Sense Amplifiers
high to Vdd and the other pulled low to and Off-Chip Drivers/Buffers

gnd, thus writing the selected cell.

Data Out
– Unselected bit columns merely perform a
READ operation.
 Typical SRAM Organization: 16-word x 4-bit

Din 3 Din 2 Din 1 Din 0

WrEn
Precharge

Wr Driver & Wr Driver & Wr Driver & Wr Driver &

- Precharger + - Precharger + - Precharger + - Precharger +
Word 0 A0

Address Decoder
SRAM SRAM SRAM SRAM
Cell Cell Cell Cell A1

Word 1 A2
SRAM SRAM SRAM SRAM
Cell Cell Cell Cell A3

: : : :
Word 15
SRAM SRAM SRAM SRAM
Cell Cell Cell Cell
- Sense Amp + - Sense Amp + - Sense Amp + - Sense Amp + Q: Which is longer:
word line or
bit line?
Dout 3 Dout 2 Dout 1 Dout 0
 (DRAM)

row select

° Write:
• 1. Drive bit line
• 2.. Select row

° Read:
• 1. Precharge bit line to Vdd
bit
• 2.. Select row
• 3. Cell and bit line share charges
- Very small voltage changes on the bit line
• 4. Sense (fancy sense amp)
- Can detect changes of ~1 million electrons
• 5. Write: restore the value

° Refresh
• 1. Just do a dummy read to every cell.

Lec17.8
 row select

General Characteristics

bit

• Optimized for high density and therefore low cost/bit

• Needs periodic refresh (needs to be refreshed periodically. Handled in background by
memory controller
• Relatively slow because of high capacity leads to large cell arrays with high word-and bit-
line capacitance

Lec17.9